--- /dev/null
+#!/bin/bash
+
+openmsp430_mods="
+omsp_alu
+omsp_clock_module
+omsp_dbg
+omsp_dbg_uart
+omsp_execution_unit
+omsp_frontend
+omsp_mem_backbone
+omsp_multiplier
+omsp_register_file
+omsp_sfr
+omsp_sync_cell
+omsp_sync_reset
+omsp_watchdog
+openMSP430"
+
+or1200_mods="
+or1200_alu
+or1200_amultp2_32x32
+or1200_cfgr
+or1200_ctrl
+or1200_dc_top
+or1200_dmmu_tlb
+or1200_dmmu_top
+or1200_du
+or1200_except
+or1200_fpu
+or1200_freeze
+or1200_ic_fsm
+or1200_ic_ram
+or1200_ic_tag
+or1200_ic_top
+or1200_if
+or1200_immu_tlb
+or1200_lsu
+or1200_mem2reg
+or1200_mult_mac
+or1200_operandmuxes
+or1200_pic
+or1200_pm
+or1200_qmem_top
+or1200_reg2mem
+or1200_rf
+or1200_sb
+or1200_sprs
+or1200_top
+or1200_tt
+or1200_wbmux"
+
+grep_regs() {
+ x=$(grep '^ Number of Slice Registers:' $1.syr | sed 's/.*: *//;' | cut -f1 -d' ')
+ echo $x | sed 's,^ *$,-1,'
+}
+
+grep_luts() {
+ x=$(grep '^ Number of Slice LUTs:' $1.syr | sed 's/.*: *//;' | cut -f1 -d' ')
+ echo $x | sed 's,^ *$,-1,'
+}
+
+grep_freq() {
+ x=$(grep 'Minimum period.*Maximum Frequency' $1.syr | sed 's/\.[0-9]*MHz.*//;' | cut -f3 -d:)
+ echo $x | sed 's,^ *$,-1,'
+}
+
+for mod in $openmsp430_mods $or1200_mods; do
+ printf '%-30s s,$, \\& %6d \\& %6d \\& %4d MHz \\& %6d \\& %6d \\& %4d MHz \\\\\\\\,;\n' "/${mod//_/\\\\_}}/" \
+ $(grep_regs ${mod}) $(grep_luts ${mod}) $(grep_freq ${mod}) \
+ $(grep_regs ${mod}_ys) $(grep_luts ${mod}_ys) $(grep_freq ${mod}_ys)
+done
+
+# for mod in $openmsp430_mods $or1200_mods; do
+# [ $mod = "or1200_top" -o $mod = "or1200_dmmu_top" -o $mod = or1200_dmmu_tlb -o $mod = or1200_immu_tlb ] && continue
+# regs=$(grep_regs ${mod}) regs_ys=$(grep_regs ${mod}_ys)
+# luts=$(grep_luts ${mod}) luts_ys=$(grep_luts ${mod}_ys)
+# freq=$(grep_freq ${mod}) freq_ys=$(grep_freq ${mod}_ys)
+# if [ $regs -gt 0 -a $regs_ys -gt 0 ]; then regs_p=$(( 100*regs_ys / regs )); else regs_p=NaN; fi
+# if [ $luts -gt 0 -a $luts_ys -gt 0 ]; then luts_p=$(( 100*luts_ys / luts )); else luts_p=NaN; fi
+# if [ $freq -gt 0 -a $freq_ys -gt 0 ]; then freq_p=$(( 100*freq_ys / freq )); else freq_p=NaN; fi
+# printf '%-30s %3s %3s %3s\n' $mod $regs_p $luts_p $freq_p
+#
+# done
+
--- /dev/null
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sync_cell.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sync_reset.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_register_file.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_dbg_uart.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_alu.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_watchdog.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sfr.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_multiplier.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_mem_backbone.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_frontend.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_execution_unit.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_dbg.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_clock_module.v"
+verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/openMSP430.v"
--- /dev/null
+verilog work "openmsp430_ys.v"
--- /dev/null
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_spram.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_reg2mem.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_mem2reg.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_dpram.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_amultp2_32x32.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_wbmux.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_sprs.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_rf.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_operandmuxes.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_mult_mac.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_lsu.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_immu_tlb.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_if.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ic_tag.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ic_ram.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ic_fsm.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_genpc.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_freeze.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_fpu.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_except.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_dmmu_tlb.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ctrl.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_cfgr.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_alu.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_wb_biu.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_tt.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_sb.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_qmem_top.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_pm.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_pic.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_immu_top.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ic_top.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_du.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_dmmu_top.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_dc_top.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_cpu.v"
+verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_top.v"
--- /dev/null
+verilog work "or1200_ys.v"
--- /dev/null
+#!/bin/bash
+
+openmsp430_mods="
+omsp_alu
+omsp_clock_module
+omsp_dbg
+omsp_dbg_uart
+omsp_execution_unit
+omsp_frontend
+omsp_mem_backbone
+omsp_multiplier
+omsp_register_file
+omsp_sfr
+omsp_sync_cell
+omsp_sync_reset
+omsp_watchdog
+openMSP430"
+
+or1200_mods="
+or1200_alu
+or1200_amultp2_32x32
+or1200_cfgr
+or1200_ctrl
+or1200_dc_top
+or1200_dmmu_tlb
+or1200_dmmu_top
+or1200_du
+or1200_except
+or1200_fpu
+or1200_freeze
+or1200_ic_fsm
+or1200_ic_ram
+or1200_ic_tag
+or1200_ic_top
+or1200_if
+or1200_immu_tlb
+or1200_lsu
+or1200_mem2reg
+or1200_mult_mac
+or1200_operandmuxes
+or1200_pic
+or1200_pm
+or1200_qmem_top
+or1200_reg2mem
+or1200_rf
+or1200_sb
+or1200_sprs
+or1200_top
+or1200_tt
+or1200_wbmux"
+
+yosys_cmds="hierarchy -check; proc; opt; fsm; opt; memory; opt; techmap; opt; abc; opt"
+
+yosys -p "$yosys_cmds" -o openmsp430_ys.v $( cut -f2 -d'"' openmsp430.prj )
+yosys -p "$yosys_cmds" -o or1200_ys.v $( cut -f2 -d'"' or1200.prj )
+
+. /opt/Xilinx/14.5/ISE_DS/settings64.sh
+
+run_single() {
+ prj_file=$1 top_module=$2 out_file=$3
+ sed "s/@prj_file@/$prj_file/g; s/@out_file@/$out_file/g; s/@top_module@/$top_module/g;" < settings.xst > ${out_file}.xst
+ xst -ifn ${out_file}.xst -ofn ${out_file}.syr
+}
+
+for mod in $openmsp430_mods; do
+ run_single openmsp430.prj ${mod} ${mod}
+ run_single openmsp430_ys.prj ${mod} ${mod}_ys
+done
+
+for mod in $or1200_mods; do
+ run_single or1200.prj ${mod} ${mod}
+ run_single or1200_ys.prj ${mod} ${mod}_ys
+done
+
--- /dev/null
+run -ifn @prj_file@ -ofn @out_file@ -ofmt NGC -top @top_module@ -p artix7
+-use_dsp48 NO -iobuf NO -ram_extract NO -rom_extract NO -fsm_extract YES -fsm_encoding Auto
\section{Example Module}
-\lstinputlisting[title=stubnets.cc,numbers=left,frame=single,language=C++]{FILES_Prog/stubnets.cc}
+\lstinputlisting[title=stubnets.cc,numbers=left,frame=single,language=C++]{CHAPTER_Prog/stubnets.cc}
-\lstinputlisting[title=Makefile,numbers=left,frame=single,language=make]{FILES_Prog/Makefile}
+\lstinputlisting[title=Makefile,numbers=left,frame=single,language=make]{CHAPTER_Prog/Makefile}
-\lstinputlisting[title=test.v,numbers=left,frame=single,language=Verilog]{FILES_Prog/test.v}
+\lstinputlisting[title=test.v,numbers=left,frame=single,language=Verilog]{CHAPTER_Prog/test.v}
--- /dev/null
+test: stubnets.so
+ yosys -ql test1.log -m ./stubnets.so test.v -p "stubnets"
+ yosys -ql test2.log -m ./stubnets.so test.v -p "opt; stubnets"
+ yosys -ql test3.log -m ./stubnets.so test.v -p "techmap; opt; stubnets -report_bits"
+ tail test1.log test2.log test3.log
+
+stubnets.so: stubnets.cc
+ yosys-config --exec --cxx --cxxflags --ldflags -o $@ -shared $^ --ldlibs
+
+clean:
+ rm -f test1.log test2.log test3.log
+ rm -f stubnets.so stubnets.d
--- /dev/null
+// This is free and unencumbered software released into the public domain.
+//
+// Anyone is free to copy, modify, publish, use, compile, sell, or
+// distribute this software, either in source code form or as a compiled
+// binary, for any purpose, commercial or non-commercial, and by any
+// means.
+
+#include "kernel/rtlil.h"
+#include "kernel/register.h"
+#include "kernel/sigtools.h"
+#include "kernel/log.h"
+
+#include <string>
+#include <map>
+#include <set>
+
+// this function is called for each module in the design
+static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool report_bits)
+{
+ // use a SigMap to convert nets to a unique representation
+ SigMap sigmap(module);
+
+ // count how many times a single-bit signal is used
+ std::map<RTLIL::SigSpec, int> bit_usage_count;
+
+ // count ouput lines for this module (needed only for summary output at the end)
+ int line_count = 0;
+
+ log("Looking for stub wires in module %s:\n", RTLIL::id2cstr(module->name));
+
+ // For all ports on all cells
+ for (auto &cell_iter : module->cells)
+ for (auto &conn : cell_iter.second->connections)
+ {
+ // Get the signals on the port
+ // (use sigmap to get a uniqe signal name)
+ RTLIL::SigSpec sig = sigmap(conn.second);
+
+ // split the signal up into single-bit chunks
+ sig.expand();
+
+ // add each chunk to bit_usage_count, unless it is a constant
+ for (auto &c : sig.chunks)
+ if (c.wire != NULL)
+ bit_usage_count[c]++;
+ }
+
+ // for each wire in the module
+ for (auto &wire_iter : module->wires)
+ {
+ RTLIL::Wire *wire = wire_iter.second;
+
+ // .. but only selected wires
+ if (!design->selected(module, wire))
+ continue;
+
+ // add +1 usage if this wire actually is a port
+ int usage_offset = wire->port_id > 0 ? 1 : 0;
+
+ // we will record which bits of the (possibly multi-bit) wire are stub signals
+ std::set<int> stub_bits;
+
+ // get a signal description for this wire and split it into seperate bits
+ RTLIL::SigSpec sig = sigmap(wire);
+ sig.expand();
+
+ // for each bit (unless it is a constant):
+ // check if it is used at least two times and add to stub_bits otherwise
+ for (size_t i = 0; i < sig.chunks.size(); i++)
+ if (sig.chunks[i].wire != NULL && (bit_usage_count[sig.chunks[i]] +
+ usage_offset) < 2)
+ stub_bits.insert(i);
+
+ // continue if no stub bits found
+ if (stub_bits.size() == 0)
+ continue;
+
+ // report stub bits and/or stub wires, don't report single bits
+ // if called with report_bits set to false.
+ if (int(stub_bits.size()) == sig.width) {
+ log(" found stub wire: %s\n", RTLIL::id2cstr(wire->name));
+ } else {
+ if (!report_bits)
+ continue;
+ log(" found wire with stub bits: %s [", RTLIL::id2cstr(wire->name));
+ for (int bit : stub_bits)
+ log("%s%d", bit == *stub_bits.begin() ? "" : ", ", bit);
+ log("]\n");
+ }
+
+ // we have outputted a line, increment summary counter
+ line_count++;
+ }
+
+ // report summary
+ if (report_bits)
+ log(" found %d stub wires or wires with stub bits.\n", line_count);
+ else
+ log(" found %d stub wires.\n", line_count);
+}
+
+// each pass contains a singleton object that is derived from Pass
+struct StubnetsPass : public Pass {
+ StubnetsPass() : Pass("stubnets") { }
+ virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ {
+ // variables to mirror information from passed options
+ bool report_bits = 0;
+
+ log_header("Executing STUBNETS pass (find stub nets).\n");
+
+ // parse options
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++) {
+ std::string arg = args[argidx];
+ if (arg == "-report_bits") {
+ report_bits = true;
+ continue;
+ }
+ break;
+ }
+
+ // handle extra options (e.g. selection)
+ extra_args(args, argidx, design);
+
+ // call find_stub_nets() for each module that is either
+ // selected as a whole or contains selected objects.
+ for (auto &it : design->modules)
+ if (design->selected_module(it.first))
+ find_stub_nets(design, it.second, report_bits);
+ }
+} StubnetsPass;
+
--- /dev/null
+module uut(in1, in2, in3, out1, out2);
+
+input [8:0] in1, in2, in3;
+output [8:0] out1, out2;
+
+assign out1 = in1 + in2 + (in3 >> 4);
+
+endmodule
\begin{figure}[t!]
\begin{minipage}{7.7cm}
- \lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/always01_pub.v}
+ \lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/always01_pub.v}
\end{minipage}
\hfill
\begin{minipage}{7.7cm}
- \lstinputlisting[frame=single,language=Verilog]{FILES_StateOfTheArt/always02_pub.v}
+ \lstinputlisting[frame=single,language=Verilog]{CHAPTER_StateOfTheArt/always02_pub.v}
\end{minipage}
\caption{1st and 2nd Verilog always examples}
\label{fig:StateOfTheArt_always12}
\end{figure}
\begin{figure}[!]
- \lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/always03.v}
+ \lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/always03.v}
\caption{3rd Verilog always example}
\label{fig:StateOfTheArt_always3}
\end{figure}
tools under test were able to successfully synthesize this design.
\begin{figure}[b!]
- \lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/arrays01.v}
+ \lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/arrays01.v}
\caption{Verilog array example}
\label{fig:StateOfTheArt_arrays}
\end{figure}
arrays are not supported.
\begin{figure}[t!]
- \lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/forgen01.v}
+ \lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/forgen01.v}
\caption{Verilog for loop example}
\label{fig:StateOfTheArt_for}
\end{figure}
memories, correct handling of write collisions, and so forth.
\begin{figure}[t!]
- \lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/forgen02.v}
+ \lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/forgen02.v}
\caption{Verilog generate example}
\label{fig:StateOfTheArt_gen}
\end{figure}
--- /dev/null
+module uut_always01(clock, reset, c3, c2, c1, c0);
+
+input clock, reset;
+output c3, c2, c1, c0;
+reg [3:0] count;
+
+assign {c3, c2, c1, c0} = count;
+
+always @(posedge clock)
+ count <= reset ? 0 : count + 1;
+
+endmodule
--- /dev/null
+module uut_always01(clock,
+ reset, count);
+
+input clock, reset;
+output [3:0] count;
+reg [3:0] count;
+
+always @(posedge clock)
+ count <= reset ?
+ 0 : count + 1;
+
+
+
+endmodule
--- /dev/null
+module uut_always02(clock, reset, c3, c2, c1, c0);
+
+input clock, reset;
+output c3, c2, c1, c0;
+reg [3:0] count;
+
+assign {c3, c2, c1, c0} = count;
+
+always @(posedge clock) begin
+ count <= count + 1;
+ if (reset)
+ count <= 0;
+end
+
+endmodule
--- /dev/null
+module uut_always02(clock,
+ reset, count);
+
+input clock, reset;
+output [3:0] count;
+reg [3:0] count;
+
+always @(posedge clock) begin
+ count <= count + 1;
+ if (reset)
+ count <= 0;
+end
+
+endmodule
--- /dev/null
+module uut_always03(clock, in1, in2, in3, in4, in5, in6, in7,
+ out1, out2, out3);
+
+input clock, in1, in2, in3, in4, in5, in6, in7;
+output out1, out2, out3;
+reg out1, out2, out3;
+
+always @(posedge clock) begin
+ out1 = in1;
+ if (in2)
+ out1 = !out1;
+ out2 <= out1;
+ if (in3)
+ out2 <= out2;
+ if (in4)
+ if (in5)
+ out3 <= in6;
+ else
+ out3 <= in7;
+ out1 = out1 ^ out2;
+end
+
+endmodule
--- /dev/null
+module uut_arrays01(clock, we, addr, wr_data, rd_data);
+
+input clock, we;
+input [3:0] addr, wr_data;
+output [3:0] rd_data;
+reg [3:0] rd_data;
+
+reg [3:0] memory [15:0];
+
+always @(posedge clock) begin
+ if (we)
+ memory[addr] <= wr_data;
+ rd_data <= memory[addr];
+end
+
+endmodule
--- /dev/null
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <string.h>
+
+int line = 0;
+char buffer1[1024];
+char buffer2[1024];
+
+void check(bool ok)
+{
+ if (ok)
+ return;
+ // fprintf(stderr, "Error in testbench output compare (line=%d):\n-%s\n+%s\n", line, buffer1, buffer2);
+ exit(1);
+}
+
+int main(int argc, char **argv)
+{
+ FILE *f1, *f2;
+ bool eof1, eof2;
+ int i;
+
+ check(argc == 3);
+
+ f1 = fopen(argv[1], "r");
+ f2 = fopen(argv[2], "r");
+
+ check(f1 && f2);
+
+ while (!feof(f1) && !feof(f2))
+ {
+ line++;
+ buffer1[0] = 0;
+ buffer2[0] = 0;
+
+ eof1 = fgets(buffer1, 1024, f1) == NULL;
+ eof2 = fgets(buffer2, 1024, f2) == NULL;
+
+ if (*buffer1 && buffer1[strlen(buffer1)-1] == '\n')
+ buffer1[strlen(buffer1)-1] = 0;
+
+ if (*buffer2 && buffer2[strlen(buffer2)-1] == '\n')
+ buffer2[strlen(buffer2)-1] = 0;
+
+ check(eof1 == eof2);
+
+ for (i = 0; buffer1[i] || buffer2[i]; i++)
+ {
+ check(buffer1[i] != 0 && buffer2[i] != 0);
+
+ // first argument is the reference. An 'z' or 'x'
+ // here means we don't care about the result.
+ if (buffer1[i] == 'z' || buffer1[i] == 'x')
+ continue;
+
+ check(buffer1[i] == buffer2[i]);
+ }
+ }
+
+ check(feof(f1) && feof(f2));
+
+ fclose(f1);
+ fclose(f2);
+ return 0;
+}
+
--- /dev/null
+module uut_forgen01(a, y);
+
+input [4:0] a;
+output y;
+
+integer i, j;
+reg [31:0] lut;
+
+initial begin
+ for (i = 0; i < 32; i = i+1) begin
+ lut[i] = i > 1;
+ for (j = 2; j*j <= i; j = j+1)
+ if (i % j == 0)
+ lut[i] = 0;
+ end
+end
+
+assign y = lut[a];
+
+endmodule
--- /dev/null
+module uut_forgen02(a, b, cin, y, cout);
+
+parameter WIDTH = 8;
+
+input [WIDTH-1:0] a, b;
+input cin;
+
+output [WIDTH-1:0] y;
+output cout;
+
+genvar i;
+wire [WIDTH-1:0] carry;
+
+generate
+ for (i = 0; i < WIDTH; i=i+1) begin:adder
+ wire [2:0] D;
+ assign D[1:0] = { a[i], b[i] };
+ if (i == 0) begin:chain
+ assign D[2] = cin;
+ end else begin:chain
+ assign D[2] = carry[i-1];
+ end
+ assign y[i] = ^D;
+ assign carry[i] = &D[1:0] | (^D[1:0] & D[2]);
+ end
+endgenerate
+
+assign cout = carry[WIDTH-1];
+
+endmodule
--- /dev/null
+--- ./elab_net.cc.orig 2012-10-27 22:11:05.345688820 +0200
++++ ./elab_net.cc 2012-10-27 22:12:23.398075860 +0200
+@@ -29,6 +29,7 @@
+
+ # include <iostream>
+ # include <cstring>
++# include <memory>
+
+ /*
+ * This is a state flag that determines whether an elaborate_net must
+--- ./syn-rules.y.orig 2012-10-27 22:25:38.890020489 +0200
++++ ./syn-rules.y 2012-10-27 22:25:49.146071350 +0200
+@@ -25,6 +25,7 @@
+ # include "config.h"
+
+ # include <iostream>
++# include <stdio.h>
+
+ /*
+ * This file implements synthesis based on matching threads and
--- /dev/null
+--- ./helpers/config.sub.orig 2012-10-27 22:09:04.429089223 +0200
++++ ./helpers/config.sub 2012-10-27 22:09:11.501124295 +0200
+@@ -158,6 +158,7 @@
+ | sparc | sparclet | sparclite | sparc64)
+ basic_machine=$basic_machine-unknown
+ ;;
++ x86_64-pc) ;;
+ # We use `pc' rather than `unknown'
+ # because (1) that's what they normally are, and
+ # (2) the word "unknown" tends to confuse beginning users.
+--- ./src/base/ntki/ntkiFrames.c.orig 2012-10-27 22:09:26.961200963 +0200
++++ ./src/base/ntki/ntkiFrames.c 2012-10-27 22:09:32.901230409 +0200
+@@ -23,7 +23,7 @@
+ ////////////////////////////////////////////////////////////////////////
+
+ static void Ntk_NetworkAddFrame( Ntk_Network_t * pNetNew, Ntk_Network_t * pNet, int iFrame );
+-static void Ntk_NetworkReorderCiCo( Ntk_Network_t * pNet );
++// static void Ntk_NetworkReorderCiCo( Ntk_Network_t * pNet );
+
+ extern int Ntk_NetworkVerifyVariables( Ntk_Network_t * pNet1, Ntk_Network_t * pNet2, int fVerbose );
+
+--- ./src/graph/wn/wnStrashBin.c.orig 2012-10-27 22:27:29.966571294 +0200
++++ ./src/graph/wn/wnStrashBin.c 2012-10-27 22:27:55.898699881 +0200
+@@ -76,8 +76,10 @@
+ // assert( RetValue );
+
+ // clean the data of the nodes in the window
+- Ntk_NetworkForEachNodeSpecial( pWnd->pNet, pNode )
+- pNode->pCopy = (Ntk_Node_t *)pNode->pData = NULL;
++ Ntk_NetworkForEachNodeSpecial( pWnd->pNet, pNode ) {
++ pNode->pData = NULL;
++ pNode->pCopy = NULL;
++ }
+
+ // set the leaves
+ pgInputs = Sh_ManagerReadVars( pMan );
--- /dev/null
+/*
+Copyright (C) 2009-2010 Parvez Ahmad
+Written by Parvez Ahmad <parvez_ahmad@yahoo.co.uk>.
+
+This program is free software: you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+
+module BUF (input in, output out);
+
+assign out = in;
+
+endmodule
+
+module TRIBUF(input in, enable, output out);
+
+assign out = enable ? in : 1'bz;
+
+endmodule
+
+module INV(input in, output out);
+
+assign out = ~in;
+
+endmodule
+
+module AND2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);
+
+assign out = ∈
+
+endmodule
+
+module AND3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
+
+assign out = ∈
+
+endmodule
+
+module AND4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
+
+assign out = ∈
+
+endmodule
+
+module OR2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);
+
+assign out = |in;
+
+endmodule
+
+module OR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
+
+assign out = |in;
+
+endmodule
+
+module OR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
+
+assign out = |in;
+
+endmodule
+
+
+module NAND2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);
+
+assign out = ~∈
+
+endmodule
+
+module NAND3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
+
+assign out = ~∈
+
+endmodule
+
+module NAND4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
+
+assign out = ~∈
+
+endmodule
+
+module NOR2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);
+
+assign out = ~|in;
+
+endmodule
+
+module NOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
+
+assign out = ~|in;
+
+endmodule
+
+module NOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
+
+assign out = ~|in;
+
+endmodule
+
+
+module XOR2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);
+
+assign out = ^in;
+
+endmodule
+
+module XOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
+
+assign out = ^in;
+
+endmodule
+
+module XOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
+
+assign out = ^in;
+
+endmodule
+
+
+module XNOR2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);
+
+assign out = ~^in;
+
+endmodule
+
+module XNOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
+
+assign out = ~^in;
+
+endmodule
+
+module XNOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
+
+assign out = ~^in;
+
+endmodule
+
+module DEC1 (input in, enable, output reg [1:0] out);
+
+always @(in or enable)
+ if(!enable)
+ out = 2'b00;
+ else begin
+ case (in)
+ 1'b0 : out = 2'b01;
+ 1'b1 : out = 2'b10;
+ endcase
+ end
+endmodule
+
+module DEC2 (input [1:0] in, input enable, output reg [3:0] out);
+
+always @(in or enable)
+ if(!enable)
+ out = 4'b0000;
+ else begin
+ case (in)
+ 2'b00 : out = 4'b0001;
+ 2'b01 : out = 4'b0010;
+ 2'b10 : out = 4'b0100;
+ 2'b11 : out = 4'b1000;
+ endcase
+ end
+endmodule
+
+module DEC3 (input [2:0] in, input enable, output reg [7:0] out);
+
+always @(in or enable)
+ if(!enable)
+ out = 8'b00000000;
+ else begin
+ case (in)
+ 3'b000 : out = 8'b00000001;
+ 3'b001 : out = 8'b00000010;
+ 3'b010 : out = 8'b00000100;
+ 3'b011 : out = 8'b00001000;
+ 3'b100 : out = 8'b00010000;
+ 3'b101 : out = 8'b00100000;
+ 3'b110 : out = 8'b01000000;
+ 3'b111 : out = 8'b10000000;
+ endcase
+ end
+endmodule
+
+module DEC4 (input [3:0] in, input enable, output reg [15:0] out);
+
+always @(in or enable)
+ if(!enable)
+ out = 16'b0000000000000000;
+ else begin
+ case (in)
+ 4'b0000 : out = 16'b0000000000000001;
+ 4'b0001 : out = 16'b0000000000000010;
+ 4'b0010 : out = 16'b0000000000000100;
+ 4'b0011 : out = 16'b0000000000001000;
+ 4'b0100 : out = 16'b0000000000010000;
+ 4'b0101 : out = 16'b0000000000100000;
+ 4'b0110 : out = 16'b0000000001000000;
+ 4'b0111 : out = 16'b0000000010000000;
+ 4'b1000 : out = 16'b0000000100000000;
+ 4'b1001 : out = 16'b0000001000000000;
+ 4'b1010 : out = 16'b0000010000000000;
+ 4'b1011 : out = 16'b0000100000000000;
+ 4'b1100 : out = 16'b0001000000000000;
+ 4'b1101 : out = 16'b0010000000000000;
+ 4'b1110 : out = 16'b0100000000000000;
+ 4'b1111 : out = 16'b1000000000000000;
+ endcase
+ end
+endmodule
+module DEC5 (input [4:0] in, input enable, output reg [31:0] out);
+
+always @(in or enable)
+ if(!enable)
+ out = 32'b00000000000000000000000000000000;
+ else begin
+ case (in)
+ 5'b00000 : out = 32'b00000000000000000000000000000001;
+ 5'b00001 : out = 32'b00000000000000000000000000000010;
+ 5'b00010 : out = 32'b00000000000000000000000000000100;
+ 5'b00011 : out = 32'b00000000000000000000000000001000;
+ 5'b00100 : out = 32'b00000000000000000000000000010000;
+ 5'b00101 : out = 32'b00000000000000000000000000100000;
+ 5'b00110 : out = 32'b00000000000000000000000001000000;
+ 5'b00111 : out = 32'b00000000000000000000000010000000;
+ 5'b01000 : out = 32'b00000000000000000000000100000000;
+ 5'b01001 : out = 32'b00000000000000000000001000000000;
+ 5'b01010 : out = 32'b00000000000000000000010000000000;
+ 5'b01011 : out = 32'b00000000000000000000100000000000;
+ 5'b01100 : out = 32'b00000000000000000001000000000000;
+ 5'b01101 : out = 32'b00000000000000000010000000000000;
+ 5'b01110 : out = 32'b00000000000000000100000000000000;
+ 5'b01111 : out = 32'b00000000000000001000000000000000;
+ 5'b10000 : out = 32'b00000000000000010000000000000000;
+ 5'b10001 : out = 32'b00000000000000100000000000000000;
+ 5'b10010 : out = 32'b00000000000001000000000000000000;
+ 5'b10011 : out = 32'b00000000000010000000000000000000;
+ 5'b10100 : out = 32'b00000000000100000000000000000000;
+ 5'b10101 : out = 32'b00000000001000000000000000000000;
+ 5'b10110 : out = 32'b00000000010000000000000000000000;
+ 5'b10111 : out = 32'b00000000100000000000000000000000;
+ 5'b11000 : out = 32'b00000001000000000000000000000000;
+ 5'b11001 : out = 32'b00000010000000000000000000000000;
+ 5'b11010 : out = 32'b00000100000000000000000000000000;
+ 5'b11011 : out = 32'b00001000000000000000000000000000;
+ 5'b11100 : out = 32'b00010000000000000000000000000000;
+ 5'b11101 : out = 32'b00100000000000000000000000000000;
+ 5'b11110 : out = 32'b01000000000000000000000000000000;
+ 5'b11111 : out = 32'b10000000000000000000000000000000;
+ endcase
+ end
+endmodule
+
+module DEC6 (input [5:0] in, input enable, output reg [63:0] out);
+
+always @(in or enable)
+ if(!enable)
+ out = 64'b0000000000000000000000000000000000000000000000000000000000000000;
+ else begin
+ case (in)
+ 6'b000000 : out = 64'b0000000000000000000000000000000000000000000000000000000000000001;
+ 6'b000001 : out = 64'b0000000000000000000000000000000000000000000000000000000000000010;
+ 6'b000010 : out = 64'b0000000000000000000000000000000000000000000000000000000000000100;
+ 6'b000011 : out = 64'b0000000000000000000000000000000000000000000000000000000000001000;
+ 6'b000100 : out = 64'b0000000000000000000000000000000000000000000000000000000000010000;
+ 6'b000101 : out = 64'b0000000000000000000000000000000000000000000000000000000000100000;
+ 6'b000110 : out = 64'b0000000000000000000000000000000000000000000000000000000001000000;
+ 6'b000111 : out = 64'b0000000000000000000000000000000000000000000000000000000010000000;
+ 6'b001000 : out = 64'b0000000000000000000000000000000000000000000000000000000100000000;
+ 6'b001001 : out = 64'b0000000000000000000000000000000000000000000000000000001000000000;
+ 6'b001010 : out = 64'b0000000000000000000000000000000000000000000000000000010000000000;
+ 6'b001011 : out = 64'b0000000000000000000000000000000000000000000000000000100000000000;
+ 6'b001100 : out = 64'b0000000000000000000000000000000000000000000000000001000000000000;
+ 6'b001101 : out = 64'b0000000000000000000000000000000000000000000000000010000000000000;
+ 6'b001110 : out = 64'b0000000000000000000000000000000000000000000000000100000000000000;
+ 6'b001111 : out = 64'b0000000000000000000000000000000000000000000000001000000000000000;
+ 6'b010000 : out = 64'b0000000000000000000000000000000000000000000000010000000000000000;
+ 6'b010001 : out = 64'b0000000000000000000000000000000000000000000000100000000000000000;
+ 6'b010010 : out = 64'b0000000000000000000000000000000000000000000001000000000000000000;
+ 6'b010011 : out = 64'b0000000000000000000000000000000000000000000010000000000000000000;
+ 6'b010100 : out = 64'b0000000000000000000000000000000000000000000100000000000000000000;
+ 6'b010101 : out = 64'b0000000000000000000000000000000000000000001000000000000000000000;
+ 6'b010110 : out = 64'b0000000000000000000000000000000000000000010000000000000000000000;
+ 6'b010111 : out = 64'b0000000000000000000000000000000000000000100000000000000000000000;
+ 6'b011000 : out = 64'b0000000000000000000000000000000000000001000000000000000000000000;
+ 6'b011001 : out = 64'b0000000000000000000000000000000000000010000000000000000000000000;
+ 6'b011010 : out = 64'b0000000000000000000000000000000000000100000000000000000000000000;
+ 6'b011011 : out = 64'b0000000000000000000000000000000000001000000000000000000000000000;
+ 6'b011100 : out = 64'b0000000000000000000000000000000000010000000000000000000000000000;
+ 6'b011101 : out = 64'b0000000000000000000000000000000000100000000000000000000000000000;
+ 6'b011110 : out = 64'b0000000000000000000000000000000001000000000000000000000000000000;
+ 6'b011111 : out = 64'b0000000000000000000000000000000010000000000000000000000000000000;
+
+ 6'b100000 : out = 64'b0000000000000000000000000000000100000000000000000000000000000000;
+ 6'b100001 : out = 64'b0000000000000000000000000000001000000000000000000000000000000000;
+ 6'b100010 : out = 64'b0000000000000000000000000000010000000000000000000000000000000000;
+ 6'b100011 : out = 64'b0000000000000000000000000000100000000000000000000000000000000000;
+ 6'b100100 : out = 64'b0000000000000000000000000001000000000000000000000000000000000000;
+ 6'b100101 : out = 64'b0000000000000000000000000010000000000000000000000000000000000000;
+ 6'b100110 : out = 64'b0000000000000000000000000100000000000000000000000000000000000000;
+ 6'b100111 : out = 64'b0000000000000000000000001000000000000000000000000000000000000000;
+ 6'b101000 : out = 64'b0000000000000000000000010000000000000000000000000000000000000000;
+ 6'b101001 : out = 64'b0000000000000000000000100000000000000000000000000000000000000000;
+ 6'b101010 : out = 64'b0000000000000000000001000000000000000000000000000000000000000000;
+ 6'b101011 : out = 64'b0000000000000000000010000000000000000000000000000000000000000000;
+ 6'b101100 : out = 64'b0000000000000000000100000000000000000000000000000000000000000000;
+ 6'b101101 : out = 64'b0000000000000000001000000000000000000000000000000000000000000000;
+ 6'b101110 : out = 64'b0000000000000000010000000000000000000000000000000000000000000000;
+ 6'b101111 : out = 64'b0000000000000000100000000000000000000000000000000000000000000000;
+ 6'b110000 : out = 64'b0000000000000001000000000000000000000000000000000000000000000000;
+ 6'b110001 : out = 64'b0000000000000010000000000000000000000000000000000000000000000000;
+ 6'b110010 : out = 64'b0000000000000100000000000000000000000000000000000000000000000000;
+ 6'b110011 : out = 64'b0000000000001000000000000000000000000000000000000000000000000000;
+ 6'b110100 : out = 64'b0000000000010000000000000000000000000000000000000000000000000000;
+ 6'b110101 : out = 64'b0000000000100000000000000000000000000000000000000000000000000000;
+ 6'b110110 : out = 64'b0000000001000000000000000000000000000000000000000000000000000000;
+ 6'b110111 : out = 64'b0000000010000000000000000000000000000000000000000000000000000000;
+ 6'b111000 : out = 64'b0000000100000000000000000000000000000000000000000000000000000000;
+ 6'b111001 : out = 64'b0000001000000000000000000000000000000000000000000000000000000000;
+ 6'b111010 : out = 64'b0000010000000000000000000000000000000000000000000000000000000000;
+ 6'b111011 : out = 64'b0000100000000000000000000000000000000000000000000000000000000000;
+ 6'b111100 : out = 64'b0001000000000000000000000000000000000000000000000000000000000000;
+ 6'b111101 : out = 64'b0010000000000000000000000000000000000000000000000000000000000000;
+ 6'b111110 : out = 64'b0100000000000000000000000000000000000000000000000000000000000000;
+ 6'b111111 : out = 64'b1000000000000000000000000000000000000000000000000000000000000000;
+ endcase
+ end
+endmodule
+
+
+module MUX2(input [1:0] in, input select, output reg out);
+
+always @( in or select)
+ case (select)
+ 0: out = in[0];
+ 1: out = in[1];
+ endcase
+endmodule
+
+
+module MUX4(input [3:0] in, input [1:0] select, output reg out);
+
+always @( in or select)
+ case (select)
+ 0: out = in[0];
+ 1: out = in[1];
+ 2: out = in[2];
+ 3: out = in[3];
+ endcase
+endmodule
+
+
+module MUX8(input [7:0] in, input [2:0] select, output reg out);
+
+always @( in or select)
+ case (select)
+ 0: out = in[0];
+ 1: out = in[1];
+ 2: out = in[2];
+ 3: out = in[3];
+ 4: out = in[4];
+ 5: out = in[5];
+ 6: out = in[6];
+ 7: out = in[7];
+ endcase
+endmodule
+
+module MUX16(input [15:0] in, input [3:0] select, output reg out);
+
+always @( in or select)
+ case (select)
+ 0: out = in[0];
+ 1: out = in[1];
+ 2: out = in[2];
+ 3: out = in[3];
+ 4: out = in[4];
+ 5: out = in[5];
+ 6: out = in[6];
+ 7: out = in[7];
+ 8: out = in[8];
+ 9: out = in[9];
+ 10: out = in[10];
+ 11: out = in[11];
+ 12: out = in[12];
+ 13: out = in[13];
+ 14: out = in[14];
+ 15: out = in[15];
+ endcase
+endmodule
+
+module MUX32(input [31:0] in, input [4:0] select, output reg out);
+
+always @( in or select)
+ case (select)
+ 0: out = in[0];
+ 1: out = in[1];
+ 2: out = in[2];
+ 3: out = in[3];
+ 4: out = in[4];
+ 5: out = in[5];
+ 6: out = in[6];
+ 7: out = in[7];
+ 8: out = in[8];
+ 9: out = in[9];
+ 10: out = in[10];
+ 11: out = in[11];
+ 12: out = in[12];
+ 13: out = in[13];
+ 14: out = in[14];
+ 15: out = in[15];
+ 16: out = in[16];
+ 17: out = in[17];
+ 18: out = in[18];
+ 19: out = in[19];
+ 20: out = in[20];
+ 21: out = in[21];
+ 22: out = in[22];
+ 23: out = in[23];
+ 24: out = in[24];
+ 25: out = in[25];
+ 26: out = in[26];
+ 27: out = in[27];
+ 28: out = in[28];
+ 29: out = in[29];
+ 30: out = in[30];
+ 31: out = in[31];
+ endcase
+endmodule
+
+module MUX64(input [63:0] in, input [5:0] select, output reg out);
+
+always @( in or select)
+ case (select)
+ 0: out = in[0];
+ 1: out = in[1];
+ 2: out = in[2];
+ 3: out = in[3];
+ 4: out = in[4];
+ 5: out = in[5];
+ 6: out = in[6];
+ 7: out = in[7];
+ 8: out = in[8];
+ 9: out = in[9];
+ 10: out = in[10];
+ 11: out = in[11];
+ 12: out = in[12];
+ 13: out = in[13];
+ 14: out = in[14];
+ 15: out = in[15];
+ 16: out = in[16];
+ 17: out = in[17];
+ 18: out = in[18];
+ 19: out = in[19];
+ 20: out = in[20];
+ 21: out = in[21];
+ 22: out = in[22];
+ 23: out = in[23];
+ 24: out = in[24];
+ 25: out = in[25];
+ 26: out = in[26];
+ 27: out = in[27];
+ 28: out = in[28];
+ 29: out = in[29];
+ 30: out = in[30];
+ 31: out = in[31];
+ 32: out = in[32];
+ 33: out = in[33];
+ 34: out = in[34];
+ 35: out = in[35];
+ 36: out = in[36];
+ 37: out = in[37];
+ 38: out = in[38];
+ 39: out = in[39];
+ 40: out = in[40];
+ 41: out = in[41];
+ 42: out = in[42];
+ 43: out = in[43];
+ 44: out = in[44];
+ 45: out = in[45];
+ 46: out = in[46];
+ 47: out = in[47];
+ 48: out = in[48];
+ 49: out = in[49];
+ 50: out = in[50];
+ 51: out = in[51];
+ 52: out = in[52];
+ 53: out = in[53];
+ 54: out = in[54];
+ 55: out = in[55];
+ 56: out = in[56];
+ 57: out = in[57];
+ 58: out = in[58];
+ 59: out = in[59];
+ 60: out = in[60];
+ 61: out = in[61];
+ 62: out = in[62];
+ 63: out = in[63];
+ endcase
+endmodule
+
+module ADD1(input in1, in2, cin, output out, cout);
+
+assign {cout, out} = in1 + in2 + cin;
+
+endmodule
+
+module ADD2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2,
+ input cin, output [SIZE-1:0] out, output cout);
+
+assign {cout, out} = in1 + in2 + cin;
+
+endmodule
+
+module ADD4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2,
+ input cin, output [SIZE-1:0] out, output cout);
+
+assign {cout, out} = in1 + in2 + cin;
+
+endmodule
+
+module ADD8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2,
+ input cin, output [SIZE-1:0] out, output cout);
+
+assign {cout, out} = in1 + in2 + cin;
+
+endmodule
+
+module ADD16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2,
+ input cin, output [SIZE-1:0] out, output cout);
+
+assign {cout, out} = in1 + in2 + cin;
+
+endmodule
+
+module ADD32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2,
+ input cin, output [SIZE-1:0] out, output cout);
+
+assign {cout, out} = in1 + in2 + cin;
+
+endmodule
+module ADD64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2,
+ input cin, output [SIZE-1:0] out, output cout);
+
+assign {cout, out} = in1 + in2 + cin;
+
+endmodule
+
+module SUB1(input in1, in2, cin, output out, cout);
+
+assign {cout, out} = in1 - in2 - cin;
+
+endmodule
+
+module SUB2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2,
+ input cin, output [SIZE-1:0] out, output cout);
+
+assign {cout, out} = in1 - in2 - cin;
+
+endmodule
+
+module SUB4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2,
+ input cin, output [SIZE-1:0] out, output cout);
+
+assign {cout, out} = in1 - in2 - cin;
+
+endmodule
+
+module SUB8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2,
+ input cin, output [SIZE-1:0] out, output cout);
+
+assign {cout, out} = in1 - in2 - cin;
+
+endmodule
+
+module SUB16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2,
+ input cin, output [SIZE-1:0] out, output cout);
+
+assign {cout, out} = in1 - in2 - cin;
+
+endmodule
+
+module SUB32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2,
+ input cin, output [SIZE-1:0] out, output cout);
+
+assign {cout, out} = in1 - in2 - cin;
+
+endmodule
+module SUB64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2,
+ input cin, output [SIZE-1:0] out, output cout);
+
+assign {cout, out} = in1 - in2 - cin;
+
+endmodule
+
+module MUL1 #(parameter SIZE = 1)(input in1, in2, output [2*SIZE-1:0] out);
+
+assign out = in1*in2;
+
+endmodule
+
+module MUL2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);
+
+assign out = in1*in2;
+
+endmodule
+
+module MUL4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);
+
+assign out = in1*in2;
+
+endmodule
+
+module MUL8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);
+
+assign out = in1*in2;
+
+endmodule
+
+module MUL16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);
+
+assign out = in1*in2;
+
+endmodule
+
+module MUL32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);
+
+assign out = in1*in2;
+
+endmodule
+
+module MUL64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);
+
+assign out = in1*in2;
+
+endmodule
+
+module DIV1 #(parameter SIZE = 1)(input in1, in2, output out, rem);
+
+assign out = in1/in2;
+assign rem = in1%in2;
+
+endmodule
+
+module DIV2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2,
+ output [SIZE-1:0] out, rem);
+
+assign out = in1/in2;
+assign rem = in1%in2;
+
+endmodule
+
+module DIV4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2,
+ output [SIZE-1:0] out, rem);
+
+assign out = in1/in2;
+assign rem = in1%in2;
+
+endmodule
+
+module DIV8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2,
+ output [SIZE-1:0] out, rem);
+
+assign out = in1/in2;
+assign rem = in1%in2;
+
+endmodule
+
+module DIV16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2,
+ output [SIZE-1:0] out, rem);
+
+assign out = in1/in2;
+assign rem = in1%in2;
+
+endmodule
+
+module DIV32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2,
+ output [SIZE-1:0] out, rem);
+
+assign out = in1/in2;
+assign rem = in1%in2;
+
+endmodule
+
+module DIV64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2,
+ output [SIZE-1:0] out, rem);
+
+assign out = in1/in2;
+assign rem = in1%in2;
+
+endmodule
+
+module FF (input d, clk, output reg q);
+always @( posedge clk)
+ q <= d;
+endmodule
+
+
+module RFF(input d, clk, reset, output reg q);
+always @(posedge clk or posedge reset)
+ if(reset)
+ q <= 0;
+ else
+ q <= d;
+endmodule
+
+module SFF(input d, clk, set, output reg q);
+always @(posedge clk or posedge set)
+ if(set)
+ q <= 1;
+ else
+ q <= d;
+endmodule
+
+module RSFF(input d, clk, set, reset, output reg q);
+always @(posedge clk or posedge reset or posedge set)
+ if(reset)
+ q <= 0;
+ else if(set)
+ q <= 1;
+ else
+ q <= d;
+endmodule
+
+module SRFF(input d, clk, set, reset, output reg q);
+always @(posedge clk or posedge set or posedge reset)
+ if(set)
+ q <= 1;
+ else if(reset)
+ q <= 0;
+ else
+ q <= d;
+endmodule
+
+module LATCH(input d, enable, output reg q);
+always @( d or enable)
+ if(enable)
+ q <= d;
+endmodule
+
+module RLATCH(input d, reset, enable, output reg q);
+always @( d or enable or reset)
+ if(enable)
+ if(reset)
+ q <= 0;
+ else
+ q <= d;
+endmodule
+
+module LSHIFT1 #(parameter SIZE = 1)(input in, shift, val, output reg out);
+
+always @ (in, shift, val) begin
+ if(shift)
+ out = val;
+ else
+ out = in;
+end
+
+endmodule
+
+
+module LSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in,
+ input [SIZE-1:0] shift, input val,
+ output reg [SIZE-1:0] out);
+
+always @(in or shift or val) begin
+ out = in << shift;
+ if(val)
+ out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
+end
+endmodule
+
+module LSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in,
+ input [2:0] shift, input val, output reg [SIZE-1:0] out);
+
+always @(in or shift or val) begin
+ out = in << shift;
+ if(val)
+ out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
+end
+endmodule
+
+
+module LSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in,
+ input [3:0] shift, input val, output reg [SIZE-1:0] out);
+
+always @(in or shift or val) begin
+ out = in << shift;
+ if(val)
+ out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
+end
+endmodule
+
+module LSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in,
+ input [4:0] shift, input val, output reg [SIZE-1:0] out);
+
+always @(in or shift or val) begin
+ out = in << shift;
+ if(val)
+ out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
+end
+endmodule
+
+module LSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in,
+ input [5:0] shift, input val, output reg [SIZE-1:0] out);
+
+always @(in or shift or val) begin
+ out = in << shift;
+ if(val)
+ out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
+end
+endmodule
+
+module LSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in,
+ input [6:0] shift, input val, output reg [SIZE-1:0] out);
+
+always @(in or shift or val) begin
+ out = in << shift;
+ if(val)
+ out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
+end
+endmodule
+
+module RSHIFT1 #(parameter SIZE = 1)(input in, shift, val, output reg out);
+
+always @ (in, shift, val) begin
+ if(shift)
+ out = val;
+ else
+ out = in;
+end
+
+endmodule
+
+module RSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in,
+ input [SIZE-1:0] shift, input val,
+ output reg [SIZE-1:0] out);
+
+always @(in or shift or val) begin
+ out = in >> shift;
+ if(val)
+ out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
+end
+
+endmodule
+
+
+module RSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in,
+ input [2:0] shift, input val,
+ output reg [SIZE-1:0] out);
+
+always @(in or shift or val) begin
+ out = in >> shift;
+ if(val)
+ out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
+end
+endmodule
+
+module RSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in,
+ input [3:0] shift, input val,
+ output reg [SIZE-1:0] out);
+
+always @(in or shift or val) begin
+ out = in >> shift;
+ if(val)
+ out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
+end
+
+endmodule
+
+module RSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in,
+ input [4:0] shift, input val,
+ output reg [SIZE-1:0] out);
+
+always @(in or shift or val) begin
+ out = in >> shift;
+ if(val)
+ out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
+end
+endmodule
+
+
+module RSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in,
+ input [5:0] shift, input val,
+ output reg [SIZE-1:0] out);
+
+always @(in or shift or val) begin
+ out = in >> shift;
+ if(val)
+ out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
+end
+endmodule
+
+module RSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in,
+ input [6:0] shift, input val,
+ output reg [SIZE-1:0] out);
+
+always @(in or shift or val) begin
+ out = in >> shift;
+ if(val)
+ out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
+end
+endmodule
+
+module CMP1 #(parameter SIZE = 1) (input in1, in2,
+ output reg equal, unequal, greater, lesser);
+
+always @ (in1 or in2) begin
+ if(in1 == in2) begin
+ equal = 1;
+ unequal = 0;
+ greater = 0;
+ lesser = 0;
+ end
+ else begin
+ equal = 0;
+ unequal = 1;
+
+ if(in1 < in2) begin
+ greater = 0;
+ lesser = 1;
+ end
+ else begin
+ greater = 1;
+ lesser = 0;
+ end
+ end
+end
+endmodule
+
+
+module CMP2 #(parameter SIZE = 2) (input [SIZE-1:0] in1, in2,
+ output reg equal, unequal, greater, lesser);
+
+always @ (in1 or in2) begin
+ if(in1 == in2) begin
+ equal = 1;
+ unequal = 0;
+ greater = 0;
+ lesser = 0;
+ end
+ else begin
+ equal = 0;
+ unequal = 1;
+
+ if(in1 < in2) begin
+ greater = 0;
+ lesser = 1;
+ end
+ else begin
+ greater = 1;
+ lesser = 0;
+ end
+ end
+end
+endmodule
+
+module CMP4 #(parameter SIZE = 4) (input [SIZE-1:0] in1, in2,
+ output reg equal, unequal, greater, lesser);
+
+always @ (in1 or in2) begin
+ if(in1 == in2) begin
+ equal = 1;
+ unequal = 0;
+ greater = 0;
+ lesser = 0;
+ end
+ else begin
+ equal = 0;
+ unequal = 1;
+
+ if(in1 < in2) begin
+ greater = 0;
+ lesser = 1;
+ end
+ else begin
+ greater = 1;
+ lesser = 0;
+ end
+ end
+end
+endmodule
+
+module CMP8 #(parameter SIZE = 8) (input [SIZE-1:0] in1, in2,
+ output reg equal, unequal, greater, lesser);
+
+always @ (in1 or in2) begin
+ if(in1 == in2) begin
+ equal = 1;
+ unequal = 0;
+ greater = 0;
+ lesser = 0;
+ end
+ else begin
+ equal = 0;
+ unequal = 1;
+
+ if(in1 < in2) begin
+ greater = 0;
+ lesser = 1;
+ end
+ else begin
+ greater = 1;
+ lesser = 0;
+ end
+ end
+end
+endmodule
+
+module CMP16 #(parameter SIZE = 16) (input [SIZE-1:0] in1, in2,
+ output reg equal, unequal, greater, lesser);
+
+always @ (in1 or in2) begin
+ if(in1 == in2) begin
+ equal = 1;
+ unequal = 0;
+ greater = 0;
+ lesser = 0;
+ end
+ else begin
+ equal = 0;
+ unequal = 1;
+
+ if(in1 < in2) begin
+ greater = 0;
+ lesser = 1;
+ end
+ else begin
+ greater = 1;
+ lesser = 0;
+ end
+ end
+end
+endmodule
+
+module CMP32 #(parameter SIZE = 32) (input [SIZE-1:0] in1, in2,
+ output reg equal, unequal, greater, lesser);
+
+always @ (in1 or in2) begin
+ if(in1 == in2) begin
+ equal = 1;
+ unequal = 0;
+ greater = 0;
+ lesser = 0;
+ end
+ else begin
+ equal = 0;
+ unequal = 1;
+
+ if(in1 < in2) begin
+ greater = 0;
+ lesser = 1;
+ end
+ else begin
+ greater = 1;
+ lesser = 0;
+ end
+ end
+end
+endmodule
+
+module CMP64 #(parameter SIZE = 64) (input [SIZE-1:0] in1, in2,
+ output reg equal, unequal, greater, lesser);
+
+always @ (in1 or in2) begin
+ if(in1 == in2) begin
+ equal = 1;
+ unequal = 0;
+ greater = 0;
+ lesser = 0;
+ end
+ else begin
+ equal = 0;
+ unequal = 1;
+
+ if(in1 < in2) begin
+ greater = 0;
+ lesser = 1;
+ end
+ else begin
+ greater = 1;
+ lesser = 0;
+ end
+ end
+end
+endmodule
+
+module VCC (output supply1 out);
+endmodule
+
+module GND (output supply0 out);
+endmodule
+
+
+module INC1 #(parameter SIZE = 1) (input in, output [SIZE:0] out);
+
+assign out = in + 1;
+
+endmodule
+
+module INC2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output [SIZE:0] out);
+
+assign out = in + 1;
+
+endmodule
+
+module INC4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output [SIZE:0] out);
+assign out = in + 1;
+
+endmodule
+
+module INC8 #(parameter SIZE = 8) (input [SIZE-1:0] in, output [SIZE:0] out);
+assign out = in + 1;
+
+endmodule
+
+module INC16 #(parameter SIZE = 16) (input [SIZE-1:0] in, output [SIZE:0] out);
+assign out = in + 1;
+
+endmodule
+
+module INC32 #(parameter SIZE = 32) (input [SIZE-1:0] in, output [SIZE:0] out);
+assign out = in + 1;
+
+endmodule
+module INC64 #(parameter SIZE = 64) (input [SIZE-1:0] in, output [SIZE:0] out);
+assign out = in + 1;
+
+endmodule
+
--- /dev/null
+
+module cell0(Result0);
+output Result0;
+assign Result0 = 0;
+endmodule
+
+module cell1(Result0);
+output Result0;
+assign Result0 = 1;
+endmodule
+
+module ADD4(
+ DataA0, DataA1, DataA2, DataA3,
+ DataB0, DataB1, DataB2, DataB3,
+ Result0, Result1, Result2, Result3, Cout
+);
+input DataA0, DataA1, DataA2, DataA3;
+input DataB0, DataB1, DataB2, DataB3;
+output Result0, Result1, Result2, Result3, Cout;
+assign {Cout, Result3, Result2, Result1, Result0} = {DataA3, DataA2, DataA1, DataA0} + {DataB3, DataB2, DataB1, DataB0};
+endmodule
+
+module BUF(DATA, RESULT);
+input DATA;
+output RESULT;
+assign RESULT = DATA;
+endmodule
+
+module INV(DATA, RESULT);
+input DATA;
+output RESULT;
+assign RESULT = ~DATA;
+endmodule
+
+module fd4(
+ Clock,
+ Data0, Data1, Data2, Data3,
+ Q0, Q1, Q2, Q3
+);
+input Clock;
+input Data0, Data1, Data2, Data3;
+output reg Q0, Q1, Q2, Q3;
+always @(posedge Clock)
+ {Q0, Q1, Q2, Q3} <= {Data0, Data1, Data2, Data3};
+endmodule
+
+module fdce1(
+ Clock, Enable,
+ Data0,
+ Q0
+);
+input Clock, Enable;
+input Data0;
+output reg Q0;
+always @(posedge Clock)
+ if (Enable)
+ Q0 <= Data0;
+endmodule
+
+module fdce4(
+ Clock, Enable,
+ Data0, Data1, Data2, Data3,
+ Q0, Q1, Q2, Q3
+);
+input Clock, Enable;
+input Data0, Data1, Data2, Data3;
+output reg Q0, Q1, Q2, Q3;
+always @(posedge Clock)
+ if (Enable)
+ {Q0, Q1, Q2, Q3} <= {Data0, Data1, Data2, Data3};
+endmodule
+
+module mux4_1_2(
+ Sel0,
+ Data0x0, Data0x1, Data0x2, Data0x3,
+ Data1x0, Data1x1, Data1x2, Data1x3,
+ Result0, Result1, Result2, Result3
+);
+input Sel0;
+input Data0x0, Data0x1, Data0x2, Data0x3;
+input Data1x0, Data1x1, Data1x2, Data1x3;
+output Result0, Result1, Result2, Result3;
+assign {Result0, Result1, Result2, Result3} = Sel0 ? {Data1x0, Data1x1, Data1x2, Data1x3} : {Data0x0, Data0x1, Data0x2, Data0x3};
+endmodule
+
+module mux1_1_2(
+ Sel0,
+ Data0x0,
+ Data1x0,
+ Result0
+);
+input Sel0;
+input Data0x0;
+input Data1x0;
+output Result0;
+assign Result0 = Sel0 ? Data1x0 : Data0x0;
+endmodule
+
+module xor2(
+ DATA0X0,
+ DATA1X0,
+ RESULT0
+);
+input DATA0X0;
+input DATA1X0;
+output RESULT0;
+assign RESULT0 = DATA1X0 ^ DATA0X0;
+endmodule
+
+module fdce64(
+ Clock, Enable,
+ Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8, Data9, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, Data32, Data33, Data34, Data35, Data36, Data37, Data38, Data39, Data40, Data41, Data42, Data43, Data44, Data45, Data46, Data47, Data48, Data49, Data50, Data51, Data52, Data53, Data54, Data55, Data56, Data57, Data58, Data59, Data60, Data61, Data62, Data63,
+ Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q39, Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q49, Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q59, Q60, Q61, Q62, Q63
+);
+input Clock, Enable;
+input Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8, Data9, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, Data32, Data33, Data34, Data35, Data36, Data37, Data38, Data39, Data40, Data41, Data42, Data43, Data44, Data45, Data46, Data47, Data48, Data49, Data50, Data51, Data52, Data53, Data54, Data55, Data56, Data57, Data58, Data59, Data60, Data61, Data62, Data63;
+output reg Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q39, Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q49, Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q59, Q60, Q61, Q62, Q63;
+always @(posedge Clock)
+ if (Enable)
+ { Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q39, Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q49, Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q59, Q60, Q61, Q62, Q63 } <= { Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8, Data9, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, Data32, Data33, Data34, Data35, Data36, Data37, Data38, Data39, Data40, Data41, Data42, Data43, Data44, Data45, Data46, Data47, Data48, Data49, Data50, Data51, Data52, Data53, Data54, Data55, Data56, Data57, Data58, Data59, Data60, Data61, Data62, Data63 };
+endmodule
+
+module mux4_4_16(
+ Sel0, Sel1, Sel2, Sel3,
+ Result0, Result1, Result2, Result3,
+ Data0x0, Data0x1, Data0x2, Data0x3,
+ Data1x0, Data1x1, Data1x2, Data1x3,
+ Data2x0, Data2x1, Data2x2, Data2x3,
+ Data3x0, Data3x1, Data3x2, Data3x3,
+ Data4x0, Data4x1, Data4x2, Data4x3,
+ Data5x0, Data5x1, Data5x2, Data5x3,
+ Data6x0, Data6x1, Data6x2, Data6x3,
+ Data7x0, Data7x1, Data7x2, Data7x3,
+ Data8x0, Data8x1, Data8x2, Data8x3,
+ Data9x0, Data9x1, Data9x2, Data9x3,
+ Data10x0, Data10x1, Data10x2, Data10x3,
+ Data11x0, Data11x1, Data11x2, Data11x3,
+ Data12x0, Data12x1, Data12x2, Data12x3,
+ Data13x0, Data13x1, Data13x2, Data13x3,
+ Data14x0, Data14x1, Data14x2, Data14x3,
+ Data15x0, Data15x1, Data15x2, Data15x3
+);
+input Sel0, Sel1, Sel2, Sel3;
+output Result0, Result1, Result2, Result3;
+input Data0x0, Data0x1, Data0x2, Data0x3;
+input Data1x0, Data1x1, Data1x2, Data1x3;
+input Data2x0, Data2x1, Data2x2, Data2x3;
+input Data3x0, Data3x1, Data3x2, Data3x3;
+input Data4x0, Data4x1, Data4x2, Data4x3;
+input Data5x0, Data5x1, Data5x2, Data5x3;
+input Data6x0, Data6x1, Data6x2, Data6x3;
+input Data7x0, Data7x1, Data7x2, Data7x3;
+input Data8x0, Data8x1, Data8x2, Data8x3;
+input Data9x0, Data9x1, Data9x2, Data9x3;
+input Data10x0, Data10x1, Data10x2, Data10x3;
+input Data11x0, Data11x1, Data11x2, Data11x3;
+input Data12x0, Data12x1, Data12x2, Data12x3;
+input Data13x0, Data13x1, Data13x2, Data13x3;
+input Data14x0, Data14x1, Data14x2, Data14x3;
+input Data15x0, Data15x1, Data15x2, Data15x3;
+assign {Result0, Result1, Result2, Result3} =
+ {Sel3, Sel2, Sel1, Sel0} == 0 ? { Data0x0, Data0x1, Data0x2, Data0x3 } :
+ {Sel3, Sel2, Sel1, Sel0} == 1 ? { Data1x0, Data1x1, Data1x2, Data1x3 } :
+ {Sel3, Sel2, Sel1, Sel0} == 2 ? { Data2x0, Data2x1, Data2x2, Data2x3 } :
+ {Sel3, Sel2, Sel1, Sel0} == 3 ? { Data3x0, Data3x1, Data3x2, Data3x3 } :
+ {Sel3, Sel2, Sel1, Sel0} == 4 ? { Data4x0, Data4x1, Data4x2, Data4x3 } :
+ {Sel3, Sel2, Sel1, Sel0} == 5 ? { Data5x0, Data5x1, Data5x2, Data5x3 } :
+ {Sel3, Sel2, Sel1, Sel0} == 6 ? { Data6x0, Data6x1, Data6x2, Data6x3 } :
+ {Sel3, Sel2, Sel1, Sel0} == 7 ? { Data7x0, Data7x1, Data7x2, Data7x3 } :
+ {Sel3, Sel2, Sel1, Sel0} == 8 ? { Data8x0, Data8x1, Data8x2, Data8x3 } :
+ {Sel3, Sel2, Sel1, Sel0} == 9 ? { Data9x0, Data9x1, Data9x2, Data9x3 } :
+ {Sel3, Sel2, Sel1, Sel0} == 10 ? { Data10x0, Data10x1, Data10x2, Data10x3 } :
+ {Sel3, Sel2, Sel1, Sel0} == 11 ? { Data11x0, Data11x1, Data11x2, Data11x3 } :
+ {Sel3, Sel2, Sel1, Sel0} == 12 ? { Data12x0, Data12x1, Data12x2, Data12x3 } :
+ {Sel3, Sel2, Sel1, Sel0} == 13 ? { Data13x0, Data13x1, Data13x2, Data13x3 } :
+ {Sel3, Sel2, Sel1, Sel0} == 14 ? { Data14x0, Data14x1, Data14x2, Data14x3 } :
+ {Sel3, Sel2, Sel1, Sel0} == 15 ? { Data15x0, Data15x1, Data15x2, Data15x3 } : 'bx;
+endmodule
+
+module mux1_5_32(
+ Sel0, Sel1, Sel2, Sel3, Sel4,
+ Data0x0, Data1x0, Data2x0, Data3x0, Data4x0, Data5x0, Data6x0, Data7x0, Data8x0, Data9x0, Data10x0, Data11x0, Data12x0, Data13x0, Data14x0, Data15x0,
+ Data16x0, Data17x0, Data18x0, Data19x0, Data20x0, Data21x0, Data22x0, Data23x0, Data24x0, Data25x0, Data26x0, Data27x0, Data28x0, Data29x0, Data30x0, Data31x0,
+ Result0
+);
+input Sel0, Sel1, Sel2, Sel3, Sel4;
+input Data0x0, Data1x0, Data2x0, Data3x0, Data4x0, Data5x0, Data6x0, Data7x0, Data8x0, Data9x0, Data10x0, Data11x0, Data12x0, Data13x0, Data14x0, Data15x0;
+input Data16x0, Data17x0, Data18x0, Data19x0, Data20x0, Data21x0, Data22x0, Data23x0, Data24x0, Data25x0, Data26x0, Data27x0, Data28x0, Data29x0, Data30x0, Data31x0;
+output Result0;
+assign Result0 =
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 0 ? Data0x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 1 ? Data1x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 2 ? Data2x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 3 ? Data3x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 4 ? Data4x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 5 ? Data5x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 6 ? Data6x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 7 ? Data7x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 8 ? Data8x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 9 ? Data9x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 10 ? Data10x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 11 ? Data11x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 12 ? Data12x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 13 ? Data13x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 14 ? Data14x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 15 ? Data15x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 16 ? Data16x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 17 ? Data17x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 18 ? Data18x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 19 ? Data19x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 20 ? Data20x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 21 ? Data21x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 22 ? Data22x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 23 ? Data23x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 24 ? Data24x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 25 ? Data25x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 26 ? Data26x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 27 ? Data27x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 28 ? Data28x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 29 ? Data29x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 30 ? Data30x0 :
+ {Sel4, Sel3, Sel2, Sel1, Sel0} == 31 ? Data31x0 : 'bx;
+endmodule
+
--- /dev/null
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * ---
+ *
+ * The internal logic cell simulation library.
+ *
+ * This verilog library contains simple simulation models for the internal
+ * logic cells (_INV_, _AND_, ...) that are generated by the default technology
+ * mapper (see "stdcells.v" in this directory) and expected by the "abc" pass.
+ *
+ */
+
+module _INV_(A, Y);
+input A;
+output Y;
+assign Y = ~A;
+endmodule
+
+module _AND_(A, B, Y);
+input A, B;
+output Y;
+assign Y = A & B;
+endmodule
+
+module _OR_(A, B, Y);
+input A, B;
+output Y;
+assign Y = A | B;
+endmodule
+
+module _XOR_(A, B, Y);
+input A, B;
+output Y;
+assign Y = A ^ B;
+endmodule
+
+module _MUX_(A, B, S, Y);
+input A, B, S;
+output reg Y;
+always @* begin
+ if (S)
+ Y = B;
+ else
+ Y = A;
+end
+endmodule
+
+module _DFF_N_(D, Q, C);
+input D, C;
+output reg Q;
+always @(negedge C) begin
+ Q <= D;
+end
+endmodule
+
+module _DFF_P_(D, Q, C);
+input D, C;
+output reg Q;
+always @(posedge C) begin
+ Q <= D;
+end
+endmodule
+
+module _DFF_NN0_(D, Q, C, R);
+input D, C, R;
+output reg Q;
+always @(negedge C or negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else
+ Q <= D;
+end
+endmodule
+
+module _DFF_NN1_(D, Q, C, R);
+input D, C, R;
+output reg Q;
+always @(negedge C or negedge R) begin
+ if (R == 0)
+ Q <= 1;
+ else
+ Q <= D;
+end
+endmodule
+
+module _DFF_NP0_(D, Q, C, R);
+input D, C, R;
+output reg Q;
+always @(negedge C or posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else
+ Q <= D;
+end
+endmodule
+
+module _DFF_NP1_(D, Q, C, R);
+input D, C, R;
+output reg Q;
+always @(negedge C or posedge R) begin
+ if (R == 1)
+ Q <= 1;
+ else
+ Q <= D;
+end
+endmodule
+
+module _DFF_PN0_(D, Q, C, R);
+input D, C, R;
+output reg Q;
+always @(posedge C or negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else
+ Q <= D;
+end
+endmodule
+
+module _DFF_PN1_(D, Q, C, R);
+input D, C, R;
+output reg Q;
+always @(posedge C or negedge R) begin
+ if (R == 0)
+ Q <= 1;
+ else
+ Q <= D;
+end
+endmodule
+
+module _DFF_PP0_(D, Q, C, R);
+input D, C, R;
+output reg Q;
+always @(posedge C or posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else
+ Q <= D;
+end
+endmodule
+
+module _DFF_PP1_(D, Q, C, R);
+input D, C, R;
+output reg Q;
+always @(posedge C or posedge R) begin
+ if (R == 1)
+ Q <= 1;
+ else
+ Q <= D;
+end
+endmodule
+
--- /dev/null
+Some minor build fixes for sis-1.3.6 as it can be downloaded from
+http://www-cad.eecs.berkeley.edu/~pchong/sis.html or
+http://embedded.eecs.berkeley.edu/Alumni/pchong/sis.html
+
+diff --git a/sis/io/read_kiss.c b/sis/io/read_kiss.c
+index 814e526..c862892 100644
+--- a/sis/io/read_kiss.c
++++ b/sis/io/read_kiss.c
+@@ -10,7 +10,6 @@
+ #ifdef SIS
+ #include "sis.h"
+
+-extern void read_error();
+ extern int read_lineno;
+ extern char *read_filename;
+
+diff --git a/sis/pld/act_bdd.c b/sis/pld/act_bdd.c
+index 4fb4415..a5cd74c 100644
+--- a/sis/pld/act_bdd.c
++++ b/sis/pld/act_bdd.c
+@@ -141,6 +141,8 @@ char *name;
+ return p_vertex;
+ }
+
++static int compare();
++
+ /* Or 2 ACT's*/
+ act_t *
+ my_or_act_F(array_b,cover, array)
+@@ -148,7 +150,6 @@ array_t *array_b;
+ array_t *array;
+ sm_row *cover;
+ {
+- static int compare();
+ int i;
+ act_t *up_vertex, *down_vertex, *vertex;
+ sm_element *p;
+diff --git a/sis/pld/act_ite.c b/sis/pld/act_ite.c
+index a35f2fb..7b824df 100644
+--- a/sis/pld/act_ite.c
++++ b/sis/pld/act_ite.c
+@@ -125,6 +125,8 @@ node_t *fanin;
+ and the minimum column cover variables in cover, generates an ite for the
+ original function. */
+
++static int compare();
++
+ ite_vertex *
+ my_or_ite_F(array_b, cover, array, network)
+ array_t *array_b;
+@@ -132,7 +134,6 @@ array_t *array;
+ sm_row *cover;
+ network_t *network;
+ {
+- static int compare();
+ int i;
+ ite_vertex *vertex;
+ sm_element *p;
+diff --git a/sis/pld/xln_merge.c b/sis/pld/xln_merge.c
+index 075e6c5..16f4d61 100644
+--- a/sis/pld/xln_merge.c
++++ b/sis/pld/xln_merge.c
+@@ -284,6 +284,7 @@ array_t *match1_array, *match2_array;
+
+ }
+
++static sm_row *xln_merge_find_neighbor_of_row1_with_minimum_neighbors();
+ \f
+ /*----------------------------------------------------------------------------------------------------
+ An alternate to lindo option. Uses greedy merging. A node with minimum mergeable nodes is picked
+@@ -296,7 +297,6 @@ xln_merge_nodes_without_lindo(coeff, cand_node_array, match1_array, match2_array
+ {
+ node_t *n1, *n2;
+ sm_row *row1, *row2;
+- static sm_row *xln_merge_find_neighbor_of_row1_with_minimum_neighbors();
+
+ while (TRUE) {
+ row1 = sm_shortest_row(coeff);
+diff --git a/sis/pld/xln_part_dec.c b/sis/pld/xln_part_dec.c
+index 1c856bd..b78828a 100644
+--- a/sis/pld/xln_part_dec.c
++++ b/sis/pld/xln_part_dec.c
+@@ -49,13 +49,14 @@ int size;
+
+ \f
+
++static int kernel_value();
++
+ int
+ split_node(network, node, size)
+ network_t *network;
+ node_t *node;
+ int size;
+ {
+- static int kernel_value();
+ int i, value = 1;
+ kern_node *sorted;
+ divisor_t *div, *best_div;
+diff --git a/xsis/Makefile.am b/xsis/Makefile.am
+index 196d98b..686fdf4 100644
+--- a/xsis/Makefile.am
++++ b/xsis/Makefile.am
+@@ -1,8 +1,8 @@
+ xsis_SOURCES_local = NetPlot.c NetPlot.h NetPlotP.h main.c xastg.c \
+ xblif.c xcmd.c xhelp.c xsis.c xsis.h xutil.c \
+ blif50.px ghost.px help50.px sis50.px
+-AM_CPPFLAGS = -I../sis/include -I@SIS_X_INCLUDES@
+-AM_LDFLAGS = -L@SIS_X_LIBRARIES@
++AM_CPPFLAGS = -I../sis/include
++AM_LDFLAGS =
+ LDADD = ../sis/libsis.a -lXaw -lXmu -lXt -lXext -lX11 -lm
+
+ if SIS_COND_X
--- /dev/null
+#!/bin/bash
+
+yosys_bin="/usr/local/synthesis/src/yosys/yosys"
+hana_bin="/usr/local/synthesis/src/hana/bin/hana"
+vl2mv_bin="/usr/local/synthesis/bin/vl2mv"
+vis_bin="/usr/local/synthesis/bin/vis"
+iverilog_bin="/usr/local/synthesis/bin/iverilog-0.8"
+odin_bin="/usr/local/synthesis/src/vtr_release/ODIN_II/odin_II.exe"
+abc_bin="/usr/local/synthesis/src/alanmi-abc-b5750272659f/abc"
+edif2ngd="/opt/Xilinx/14.3/ISE_DS/ISE/bin/lin64/edif2ngd"
+netgen="/opt/Xilinx/14.3/ISE_DS/ISE/bin/lin64/netgen"
+
+all_modes="yosys hana vis icarus odin"
+all_sources="always01 always02 always03 arrays01 forgen01 forgen02"
+
+if [ "$*" == "ALL" ]; then
+ for mode in $all_modes; do
+ for src in $all_sources; do
+ echo "synth.sh $mode $src.v ${src}_${mode}.v"
+ ( set -x; bash synth.sh $mode $src.v ${src}_${mode}.v || rm -f ${src}_${mode}.v; ) > ${src}_${mode}.log 2>&1
+ done
+ done
+ exit
+fi
+
+mode="$1"
+source="$2"
+output="$3"
+prefix="${output%.v}"
+
+help() {
+ echo "$0 ALL" >&2
+ echo "$0 {yosys|hana|vis|icarus|odin} <source-file> <output-file>" >&2
+ exit 1
+}
+
+if [ "$#" != 3 -o ! -f "$source" ]; then
+ help
+fi
+
+set -ex
+
+case "$mode" in
+ yosys)
+ $yosys_bin -o $output -b "verilog -noattr" -p proc -p opt -p memory -p opt -p techmap -p opt $source ;;
+ hana)
+ $hana_bin -s $output $source ;;
+ vis)
+ $vl2mv_bin -o $prefix.mv $source
+ { echo "read_blif_mv $prefix.mv"; echo "write_verilog $output"; } | $abc_bin ;;
+ icarus)
+ rm -f $prefix.ngo $prefix.v
+ $iverilog_bin -t fpga -o $prefix.edif $source
+ $edif2ngd $prefix.edif $prefix.ngo
+ $netgen -ofmt verilog $prefix.ngo $prefix.v
+ sed -re '/timescale/ s,^,//,;' -i $prefix.v ;;
+ odin)
+ $odin_bin -o $prefix.blif -V $source
+ sed -re 's,top\^,,g; s,clock,_clock,g;' -i $prefix.blif
+ { echo "read_blif $prefix.blif"; echo "write_verilog $output"; } | $abc_bin ;;
+ *)
+ help
+esac
+
--- /dev/null
+#!/bin/bash
+
+set -ex
+
+yosys_bin="/usr/local/synthesis/src/yosys/yosys"
+iverilog_bin="iverilog"
+
+all_modes="yosys hana vis icarus odin"
+all_sources="always01 always02 always03 arrays01 forgen01 forgen02"
+
+gcc -o cmp_tbdata cmp_tbdata.c
+
+for src in $all_sources; do
+ echo; echo
+ $yosys_bin -o ${src}_tb.v -b autotest ${src}.v
+ $iverilog_bin -o ${src}_tb ${src}_tb.v ${src}.v
+ ./${src}_tb > ${src}_tb.out
+ for mode in $all_modes; do
+ simlib=""
+ [ -f ${src}_${mode}.v ] || continue
+ [ -f simlib_${mode}.v ] && simlib="simlib_${mode}.v"
+ if $iverilog_bin -o ${src}_${mode}_tb -s testbench ${src}_tb.v ${src}_${mode}.v $simlib; then
+ ./${src}_${mode}_tb > ${src}_${mode}_tb.out
+ else
+ rm -f ${src}_${mode}_tb.out
+ fi
+ done
+done
+
+set +x
+echo; echo; echo
+
+{
+ for mode in $all_modes; do
+ echo -en "\t$mode"
+ done; echo
+
+ for src in $all_sources; do
+ echo -n "$src"
+ for mode in $all_modes; do
+ if [ -f ${src}_${mode}.v ]; then
+ if [ ! -s ${src}_${mode}_tb.out ]; then
+ echo -en "\tmissing"
+ elif ./cmp_tbdata ${src}_tb.out ${src}_${mode}_tb.out; then
+ echo -en "\tok"
+ else
+ echo -en "\tfailed"
+ fi
+ else
+ echo -en "\terror"
+ fi
+ done; echo
+ done
+} | expand -t12
+
+++ /dev/null
-#!/bin/bash
-
-openmsp430_mods="
-omsp_alu
-omsp_clock_module
-omsp_dbg
-omsp_dbg_uart
-omsp_execution_unit
-omsp_frontend
-omsp_mem_backbone
-omsp_multiplier
-omsp_register_file
-omsp_sfr
-omsp_sync_cell
-omsp_sync_reset
-omsp_watchdog
-openMSP430"
-
-or1200_mods="
-or1200_alu
-or1200_amultp2_32x32
-or1200_cfgr
-or1200_ctrl
-or1200_dc_top
-or1200_dmmu_tlb
-or1200_dmmu_top
-or1200_du
-or1200_except
-or1200_fpu
-or1200_freeze
-or1200_ic_fsm
-or1200_ic_ram
-or1200_ic_tag
-or1200_ic_top
-or1200_if
-or1200_immu_tlb
-or1200_lsu
-or1200_mem2reg
-or1200_mult_mac
-or1200_operandmuxes
-or1200_pic
-or1200_pm
-or1200_qmem_top
-or1200_reg2mem
-or1200_rf
-or1200_sb
-or1200_sprs
-or1200_top
-or1200_tt
-or1200_wbmux"
-
-grep_regs() {
- x=$(grep '^ Number of Slice Registers:' $1.syr | sed 's/.*: *//;' | cut -f1 -d' ')
- echo $x | sed 's,^ *$,-1,'
-}
-
-grep_luts() {
- x=$(grep '^ Number of Slice LUTs:' $1.syr | sed 's/.*: *//;' | cut -f1 -d' ')
- echo $x | sed 's,^ *$,-1,'
-}
-
-grep_freq() {
- x=$(grep 'Minimum period.*Maximum Frequency' $1.syr | sed 's/\.[0-9]*MHz.*//;' | cut -f3 -d:)
- echo $x | sed 's,^ *$,-1,'
-}
-
-for mod in $openmsp430_mods $or1200_mods; do
- printf '%-30s s,$, \\& %6d \\& %6d \\& %4d MHz \\& %6d \\& %6d \\& %4d MHz \\\\\\\\,;\n' "/${mod//_/\\\\_}}/" \
- $(grep_regs ${mod}) $(grep_luts ${mod}) $(grep_freq ${mod}) \
- $(grep_regs ${mod}_ys) $(grep_luts ${mod}_ys) $(grep_freq ${mod}_ys)
-done
-
-# for mod in $openmsp430_mods $or1200_mods; do
-# [ $mod = "or1200_top" -o $mod = "or1200_dmmu_top" -o $mod = or1200_dmmu_tlb -o $mod = or1200_immu_tlb ] && continue
-# regs=$(grep_regs ${mod}) regs_ys=$(grep_regs ${mod}_ys)
-# luts=$(grep_luts ${mod}) luts_ys=$(grep_luts ${mod}_ys)
-# freq=$(grep_freq ${mod}) freq_ys=$(grep_freq ${mod}_ys)
-# if [ $regs -gt 0 -a $regs_ys -gt 0 ]; then regs_p=$(( 100*regs_ys / regs )); else regs_p=NaN; fi
-# if [ $luts -gt 0 -a $luts_ys -gt 0 ]; then luts_p=$(( 100*luts_ys / luts )); else luts_p=NaN; fi
-# if [ $freq -gt 0 -a $freq_ys -gt 0 ]; then freq_p=$(( 100*freq_ys / freq )); else freq_p=NaN; fi
-# printf '%-30s %3s %3s %3s\n' $mod $regs_p $luts_p $freq_p
-#
-# done
-
+++ /dev/null
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sync_cell.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sync_reset.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_register_file.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_dbg_uart.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_alu.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_watchdog.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sfr.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_multiplier.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_mem_backbone.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_frontend.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_execution_unit.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_dbg.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_clock_module.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/openMSP430.v"
+++ /dev/null
-verilog work "openmsp430_ys.v"
+++ /dev/null
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_spram.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_reg2mem.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_mem2reg.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_dpram.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_amultp2_32x32.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_wbmux.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_sprs.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_rf.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_operandmuxes.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_mult_mac.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_lsu.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_immu_tlb.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_if.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ic_tag.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ic_ram.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ic_fsm.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_genpc.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_freeze.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_fpu.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_except.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_dmmu_tlb.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ctrl.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_cfgr.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_alu.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_wb_biu.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_tt.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_sb.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_qmem_top.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_pm.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_pic.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_immu_top.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_ic_top.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_du.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_dmmu_top.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_dc_top.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_cpu.v"
-verilog work "../../../../../Work/yosys-tests/or1200/rtl/or1200_top.v"
+++ /dev/null
-verilog work "or1200_ys.v"
+++ /dev/null
-#!/bin/bash
-
-openmsp430_mods="
-omsp_alu
-omsp_clock_module
-omsp_dbg
-omsp_dbg_uart
-omsp_execution_unit
-omsp_frontend
-omsp_mem_backbone
-omsp_multiplier
-omsp_register_file
-omsp_sfr
-omsp_sync_cell
-omsp_sync_reset
-omsp_watchdog
-openMSP430"
-
-or1200_mods="
-or1200_alu
-or1200_amultp2_32x32
-or1200_cfgr
-or1200_ctrl
-or1200_dc_top
-or1200_dmmu_tlb
-or1200_dmmu_top
-or1200_du
-or1200_except
-or1200_fpu
-or1200_freeze
-or1200_ic_fsm
-or1200_ic_ram
-or1200_ic_tag
-or1200_ic_top
-or1200_if
-or1200_immu_tlb
-or1200_lsu
-or1200_mem2reg
-or1200_mult_mac
-or1200_operandmuxes
-or1200_pic
-or1200_pm
-or1200_qmem_top
-or1200_reg2mem
-or1200_rf
-or1200_sb
-or1200_sprs
-or1200_top
-or1200_tt
-or1200_wbmux"
-
-yosys_cmds="hierarchy -check; proc; opt; fsm; opt; memory; opt; techmap; opt; abc; opt"
-
-yosys -p "$yosys_cmds" -o openmsp430_ys.v $( cut -f2 -d'"' openmsp430.prj )
-yosys -p "$yosys_cmds" -o or1200_ys.v $( cut -f2 -d'"' or1200.prj )
-
-. /opt/Xilinx/14.5/ISE_DS/settings64.sh
-
-run_single() {
- prj_file=$1 top_module=$2 out_file=$3
- sed "s/@prj_file@/$prj_file/g; s/@out_file@/$out_file/g; s/@top_module@/$top_module/g;" < settings.xst > ${out_file}.xst
- xst -ifn ${out_file}.xst -ofn ${out_file}.syr
-}
-
-for mod in $openmsp430_mods; do
- run_single openmsp430.prj ${mod} ${mod}
- run_single openmsp430_ys.prj ${mod} ${mod}_ys
-done
-
-for mod in $or1200_mods; do
- run_single or1200.prj ${mod} ${mod}
- run_single or1200_ys.prj ${mod} ${mod}_ys
-done
-
+++ /dev/null
-run -ifn @prj_file@ -ofn @out_file@ -ofmt NGC -top @top_module@ -p artix7
--use_dsp48 NO -iobuf NO -ram_extract NO -rom_extract NO -fsm_extract YES -fsm_encoding Auto
+++ /dev/null
-test: stubnets.so
- yosys -ql test1.log -m ./stubnets.so test.v -p "stubnets"
- yosys -ql test2.log -m ./stubnets.so test.v -p "opt; stubnets"
- yosys -ql test3.log -m ./stubnets.so test.v -p "techmap; opt; stubnets -report_bits"
- tail test1.log test2.log test3.log
-
-stubnets.so: stubnets.cc
- yosys-config --exec --cxx --cxxflags --ldflags -o $@ -shared $^ --ldlibs
-
-clean:
- rm -f test1.log test2.log test3.log
- rm -f stubnets.so stubnets.d
+++ /dev/null
-// This is free and unencumbered software released into the public domain.
-//
-// Anyone is free to copy, modify, publish, use, compile, sell, or
-// distribute this software, either in source code form or as a compiled
-// binary, for any purpose, commercial or non-commercial, and by any
-// means.
-
-#include "kernel/rtlil.h"
-#include "kernel/register.h"
-#include "kernel/sigtools.h"
-#include "kernel/log.h"
-
-#include <string>
-#include <map>
-#include <set>
-
-// this function is called for each module in the design
-static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool report_bits)
-{
- // use a SigMap to convert nets to a unique representation
- SigMap sigmap(module);
-
- // count how many times a single-bit signal is used
- std::map<RTLIL::SigSpec, int> bit_usage_count;
-
- // count ouput lines for this module (needed only for summary output at the end)
- int line_count = 0;
-
- log("Looking for stub wires in module %s:\n", RTLIL::id2cstr(module->name));
-
- // For all ports on all cells
- for (auto &cell_iter : module->cells)
- for (auto &conn : cell_iter.second->connections)
- {
- // Get the signals on the port
- // (use sigmap to get a uniqe signal name)
- RTLIL::SigSpec sig = sigmap(conn.second);
-
- // split the signal up into single-bit chunks
- sig.expand();
-
- // add each chunk to bit_usage_count, unless it is a constant
- for (auto &c : sig.chunks)
- if (c.wire != NULL)
- bit_usage_count[c]++;
- }
-
- // for each wire in the module
- for (auto &wire_iter : module->wires)
- {
- RTLIL::Wire *wire = wire_iter.second;
-
- // .. but only selected wires
- if (!design->selected(module, wire))
- continue;
-
- // add +1 usage if this wire actually is a port
- int usage_offset = wire->port_id > 0 ? 1 : 0;
-
- // we will record which bits of the (possibly multi-bit) wire are stub signals
- std::set<int> stub_bits;
-
- // get a signal description for this wire and split it into seperate bits
- RTLIL::SigSpec sig = sigmap(wire);
- sig.expand();
-
- // for each bit (unless it is a constant):
- // check if it is used at least two times and add to stub_bits otherwise
- for (size_t i = 0; i < sig.chunks.size(); i++)
- if (sig.chunks[i].wire != NULL && (bit_usage_count[sig.chunks[i]] +
- usage_offset) < 2)
- stub_bits.insert(i);
-
- // continue if no stub bits found
- if (stub_bits.size() == 0)
- continue;
-
- // report stub bits and/or stub wires, don't report single bits
- // if called with report_bits set to false.
- if (int(stub_bits.size()) == sig.width) {
- log(" found stub wire: %s\n", RTLIL::id2cstr(wire->name));
- } else {
- if (!report_bits)
- continue;
- log(" found wire with stub bits: %s [", RTLIL::id2cstr(wire->name));
- for (int bit : stub_bits)
- log("%s%d", bit == *stub_bits.begin() ? "" : ", ", bit);
- log("]\n");
- }
-
- // we have outputted a line, increment summary counter
- line_count++;
- }
-
- // report summary
- if (report_bits)
- log(" found %d stub wires or wires with stub bits.\n", line_count);
- else
- log(" found %d stub wires.\n", line_count);
-}
-
-// each pass contains a singleton object that is derived from Pass
-struct StubnetsPass : public Pass {
- StubnetsPass() : Pass("stubnets") { }
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
- {
- // variables to mirror information from passed options
- bool report_bits = 0;
-
- log_header("Executing STUBNETS pass (find stub nets).\n");
-
- // parse options
- size_t argidx;
- for (argidx = 1; argidx < args.size(); argidx++) {
- std::string arg = args[argidx];
- if (arg == "-report_bits") {
- report_bits = true;
- continue;
- }
- break;
- }
-
- // handle extra options (e.g. selection)
- extra_args(args, argidx, design);
-
- // call find_stub_nets() for each module that is either
- // selected as a whole or contains selected objects.
- for (auto &it : design->modules)
- if (design->selected_module(it.first))
- find_stub_nets(design, it.second, report_bits);
- }
-} StubnetsPass;
-
+++ /dev/null
-module uut(in1, in2, in3, out1, out2);
-
-input [8:0] in1, in2, in3;
-output [8:0] out1, out2;
-
-assign out1 = in1 + in2 + (in3 >> 4);
-
-endmodule
+++ /dev/null
-module uut_always01(clock, reset, c3, c2, c1, c0);
-
-input clock, reset;
-output c3, c2, c1, c0;
-reg [3:0] count;
-
-assign {c3, c2, c1, c0} = count;
-
-always @(posedge clock)
- count <= reset ? 0 : count + 1;
-
-endmodule
+++ /dev/null
-module uut_always01(clock,
- reset, count);
-
-input clock, reset;
-output [3:0] count;
-reg [3:0] count;
-
-always @(posedge clock)
- count <= reset ?
- 0 : count + 1;
-
-
-
-endmodule
+++ /dev/null
-module uut_always02(clock, reset, c3, c2, c1, c0);
-
-input clock, reset;
-output c3, c2, c1, c0;
-reg [3:0] count;
-
-assign {c3, c2, c1, c0} = count;
-
-always @(posedge clock) begin
- count <= count + 1;
- if (reset)
- count <= 0;
-end
-
-endmodule
+++ /dev/null
-module uut_always02(clock,
- reset, count);
-
-input clock, reset;
-output [3:0] count;
-reg [3:0] count;
-
-always @(posedge clock) begin
- count <= count + 1;
- if (reset)
- count <= 0;
-end
-
-endmodule
+++ /dev/null
-module uut_always03(clock, in1, in2, in3, in4, in5, in6, in7,
- out1, out2, out3);
-
-input clock, in1, in2, in3, in4, in5, in6, in7;
-output out1, out2, out3;
-reg out1, out2, out3;
-
-always @(posedge clock) begin
- out1 = in1;
- if (in2)
- out1 = !out1;
- out2 <= out1;
- if (in3)
- out2 <= out2;
- if (in4)
- if (in5)
- out3 <= in6;
- else
- out3 <= in7;
- out1 = out1 ^ out2;
-end
-
-endmodule
+++ /dev/null
-module uut_arrays01(clock, we, addr, wr_data, rd_data);
-
-input clock, we;
-input [3:0] addr, wr_data;
-output [3:0] rd_data;
-reg [3:0] rd_data;
-
-reg [3:0] memory [15:0];
-
-always @(posedge clock) begin
- if (we)
- memory[addr] <= wr_data;
- rd_data <= memory[addr];
-end
-
-endmodule
+++ /dev/null
-#include <stdio.h>
-#include <stdlib.h>
-#include <stdbool.h>
-#include <string.h>
-
-int line = 0;
-char buffer1[1024];
-char buffer2[1024];
-
-void check(bool ok)
-{
- if (ok)
- return;
- // fprintf(stderr, "Error in testbench output compare (line=%d):\n-%s\n+%s\n", line, buffer1, buffer2);
- exit(1);
-}
-
-int main(int argc, char **argv)
-{
- FILE *f1, *f2;
- bool eof1, eof2;
- int i;
-
- check(argc == 3);
-
- f1 = fopen(argv[1], "r");
- f2 = fopen(argv[2], "r");
-
- check(f1 && f2);
-
- while (!feof(f1) && !feof(f2))
- {
- line++;
- buffer1[0] = 0;
- buffer2[0] = 0;
-
- eof1 = fgets(buffer1, 1024, f1) == NULL;
- eof2 = fgets(buffer2, 1024, f2) == NULL;
-
- if (*buffer1 && buffer1[strlen(buffer1)-1] == '\n')
- buffer1[strlen(buffer1)-1] = 0;
-
- if (*buffer2 && buffer2[strlen(buffer2)-1] == '\n')
- buffer2[strlen(buffer2)-1] = 0;
-
- check(eof1 == eof2);
-
- for (i = 0; buffer1[i] || buffer2[i]; i++)
- {
- check(buffer1[i] != 0 && buffer2[i] != 0);
-
- // first argument is the reference. An 'z' or 'x'
- // here means we don't care about the result.
- if (buffer1[i] == 'z' || buffer1[i] == 'x')
- continue;
-
- check(buffer1[i] == buffer2[i]);
- }
- }
-
- check(feof(f1) && feof(f2));
-
- fclose(f1);
- fclose(f2);
- return 0;
-}
-
+++ /dev/null
-module uut_forgen01(a, y);
-
-input [4:0] a;
-output y;
-
-integer i, j;
-reg [31:0] lut;
-
-initial begin
- for (i = 0; i < 32; i = i+1) begin
- lut[i] = i > 1;
- for (j = 2; j*j <= i; j = j+1)
- if (i % j == 0)
- lut[i] = 0;
- end
-end
-
-assign y = lut[a];
-
-endmodule
+++ /dev/null
-module uut_forgen02(a, b, cin, y, cout);
-
-parameter WIDTH = 8;
-
-input [WIDTH-1:0] a, b;
-input cin;
-
-output [WIDTH-1:0] y;
-output cout;
-
-genvar i;
-wire [WIDTH-1:0] carry;
-
-generate
- for (i = 0; i < WIDTH; i=i+1) begin:adder
- wire [2:0] D;
- assign D[1:0] = { a[i], b[i] };
- if (i == 0) begin:chain
- assign D[2] = cin;
- end else begin:chain
- assign D[2] = carry[i-1];
- end
- assign y[i] = ^D;
- assign carry[i] = &D[1:0] | (^D[1:0] & D[2]);
- end
-endgenerate
-
-assign cout = carry[WIDTH-1];
-
-endmodule
+++ /dev/null
---- ./elab_net.cc.orig 2012-10-27 22:11:05.345688820 +0200
-+++ ./elab_net.cc 2012-10-27 22:12:23.398075860 +0200
-@@ -29,6 +29,7 @@
-
- # include <iostream>
- # include <cstring>
-+# include <memory>
-
- /*
- * This is a state flag that determines whether an elaborate_net must
---- ./syn-rules.y.orig 2012-10-27 22:25:38.890020489 +0200
-+++ ./syn-rules.y 2012-10-27 22:25:49.146071350 +0200
-@@ -25,6 +25,7 @@
- # include "config.h"
-
- # include <iostream>
-+# include <stdio.h>
-
- /*
- * This file implements synthesis based on matching threads and
+++ /dev/null
---- ./helpers/config.sub.orig 2012-10-27 22:09:04.429089223 +0200
-+++ ./helpers/config.sub 2012-10-27 22:09:11.501124295 +0200
-@@ -158,6 +158,7 @@
- | sparc | sparclet | sparclite | sparc64)
- basic_machine=$basic_machine-unknown
- ;;
-+ x86_64-pc) ;;
- # We use `pc' rather than `unknown'
- # because (1) that's what they normally are, and
- # (2) the word "unknown" tends to confuse beginning users.
---- ./src/base/ntki/ntkiFrames.c.orig 2012-10-27 22:09:26.961200963 +0200
-+++ ./src/base/ntki/ntkiFrames.c 2012-10-27 22:09:32.901230409 +0200
-@@ -23,7 +23,7 @@
- ////////////////////////////////////////////////////////////////////////
-
- static void Ntk_NetworkAddFrame( Ntk_Network_t * pNetNew, Ntk_Network_t * pNet, int iFrame );
--static void Ntk_NetworkReorderCiCo( Ntk_Network_t * pNet );
-+// static void Ntk_NetworkReorderCiCo( Ntk_Network_t * pNet );
-
- extern int Ntk_NetworkVerifyVariables( Ntk_Network_t * pNet1, Ntk_Network_t * pNet2, int fVerbose );
-
---- ./src/graph/wn/wnStrashBin.c.orig 2012-10-27 22:27:29.966571294 +0200
-+++ ./src/graph/wn/wnStrashBin.c 2012-10-27 22:27:55.898699881 +0200
-@@ -76,8 +76,10 @@
- // assert( RetValue );
-
- // clean the data of the nodes in the window
-- Ntk_NetworkForEachNodeSpecial( pWnd->pNet, pNode )
-- pNode->pCopy = (Ntk_Node_t *)pNode->pData = NULL;
-+ Ntk_NetworkForEachNodeSpecial( pWnd->pNet, pNode ) {
-+ pNode->pData = NULL;
-+ pNode->pCopy = NULL;
-+ }
-
- // set the leaves
- pgInputs = Sh_ManagerReadVars( pMan );
+++ /dev/null
-/*
-Copyright (C) 2009-2010 Parvez Ahmad
-Written by Parvez Ahmad <parvez_ahmad@yahoo.co.uk>.
-
-This program is free software: you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program. If not, see <http://www.gnu.org/licenses/>. */
-
-
-module BUF (input in, output out);
-
-assign out = in;
-
-endmodule
-
-module TRIBUF(input in, enable, output out);
-
-assign out = enable ? in : 1'bz;
-
-endmodule
-
-module INV(input in, output out);
-
-assign out = ~in;
-
-endmodule
-
-module AND2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);
-
-assign out = ∈
-
-endmodule
-
-module AND3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
-
-assign out = ∈
-
-endmodule
-
-module AND4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
-
-assign out = ∈
-
-endmodule
-
-module OR2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);
-
-assign out = |in;
-
-endmodule
-
-module OR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
-
-assign out = |in;
-
-endmodule
-
-module OR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
-
-assign out = |in;
-
-endmodule
-
-
-module NAND2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);
-
-assign out = ~∈
-
-endmodule
-
-module NAND3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
-
-assign out = ~∈
-
-endmodule
-
-module NAND4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
-
-assign out = ~∈
-
-endmodule
-
-module NOR2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);
-
-assign out = ~|in;
-
-endmodule
-
-module NOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
-
-assign out = ~|in;
-
-endmodule
-
-module NOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
-
-assign out = ~|in;
-
-endmodule
-
-
-module XOR2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);
-
-assign out = ^in;
-
-endmodule
-
-module XOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
-
-assign out = ^in;
-
-endmodule
-
-module XOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
-
-assign out = ^in;
-
-endmodule
-
-
-module XNOR2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output out);
-
-assign out = ~^in;
-
-endmodule
-
-module XNOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
-
-assign out = ~^in;
-
-endmodule
-
-module XNOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
-
-assign out = ~^in;
-
-endmodule
-
-module DEC1 (input in, enable, output reg [1:0] out);
-
-always @(in or enable)
- if(!enable)
- out = 2'b00;
- else begin
- case (in)
- 1'b0 : out = 2'b01;
- 1'b1 : out = 2'b10;
- endcase
- end
-endmodule
-
-module DEC2 (input [1:0] in, input enable, output reg [3:0] out);
-
-always @(in or enable)
- if(!enable)
- out = 4'b0000;
- else begin
- case (in)
- 2'b00 : out = 4'b0001;
- 2'b01 : out = 4'b0010;
- 2'b10 : out = 4'b0100;
- 2'b11 : out = 4'b1000;
- endcase
- end
-endmodule
-
-module DEC3 (input [2:0] in, input enable, output reg [7:0] out);
-
-always @(in or enable)
- if(!enable)
- out = 8'b00000000;
- else begin
- case (in)
- 3'b000 : out = 8'b00000001;
- 3'b001 : out = 8'b00000010;
- 3'b010 : out = 8'b00000100;
- 3'b011 : out = 8'b00001000;
- 3'b100 : out = 8'b00010000;
- 3'b101 : out = 8'b00100000;
- 3'b110 : out = 8'b01000000;
- 3'b111 : out = 8'b10000000;
- endcase
- end
-endmodule
-
-module DEC4 (input [3:0] in, input enable, output reg [15:0] out);
-
-always @(in or enable)
- if(!enable)
- out = 16'b0000000000000000;
- else begin
- case (in)
- 4'b0000 : out = 16'b0000000000000001;
- 4'b0001 : out = 16'b0000000000000010;
- 4'b0010 : out = 16'b0000000000000100;
- 4'b0011 : out = 16'b0000000000001000;
- 4'b0100 : out = 16'b0000000000010000;
- 4'b0101 : out = 16'b0000000000100000;
- 4'b0110 : out = 16'b0000000001000000;
- 4'b0111 : out = 16'b0000000010000000;
- 4'b1000 : out = 16'b0000000100000000;
- 4'b1001 : out = 16'b0000001000000000;
- 4'b1010 : out = 16'b0000010000000000;
- 4'b1011 : out = 16'b0000100000000000;
- 4'b1100 : out = 16'b0001000000000000;
- 4'b1101 : out = 16'b0010000000000000;
- 4'b1110 : out = 16'b0100000000000000;
- 4'b1111 : out = 16'b1000000000000000;
- endcase
- end
-endmodule
-module DEC5 (input [4:0] in, input enable, output reg [31:0] out);
-
-always @(in or enable)
- if(!enable)
- out = 32'b00000000000000000000000000000000;
- else begin
- case (in)
- 5'b00000 : out = 32'b00000000000000000000000000000001;
- 5'b00001 : out = 32'b00000000000000000000000000000010;
- 5'b00010 : out = 32'b00000000000000000000000000000100;
- 5'b00011 : out = 32'b00000000000000000000000000001000;
- 5'b00100 : out = 32'b00000000000000000000000000010000;
- 5'b00101 : out = 32'b00000000000000000000000000100000;
- 5'b00110 : out = 32'b00000000000000000000000001000000;
- 5'b00111 : out = 32'b00000000000000000000000010000000;
- 5'b01000 : out = 32'b00000000000000000000000100000000;
- 5'b01001 : out = 32'b00000000000000000000001000000000;
- 5'b01010 : out = 32'b00000000000000000000010000000000;
- 5'b01011 : out = 32'b00000000000000000000100000000000;
- 5'b01100 : out = 32'b00000000000000000001000000000000;
- 5'b01101 : out = 32'b00000000000000000010000000000000;
- 5'b01110 : out = 32'b00000000000000000100000000000000;
- 5'b01111 : out = 32'b00000000000000001000000000000000;
- 5'b10000 : out = 32'b00000000000000010000000000000000;
- 5'b10001 : out = 32'b00000000000000100000000000000000;
- 5'b10010 : out = 32'b00000000000001000000000000000000;
- 5'b10011 : out = 32'b00000000000010000000000000000000;
- 5'b10100 : out = 32'b00000000000100000000000000000000;
- 5'b10101 : out = 32'b00000000001000000000000000000000;
- 5'b10110 : out = 32'b00000000010000000000000000000000;
- 5'b10111 : out = 32'b00000000100000000000000000000000;
- 5'b11000 : out = 32'b00000001000000000000000000000000;
- 5'b11001 : out = 32'b00000010000000000000000000000000;
- 5'b11010 : out = 32'b00000100000000000000000000000000;
- 5'b11011 : out = 32'b00001000000000000000000000000000;
- 5'b11100 : out = 32'b00010000000000000000000000000000;
- 5'b11101 : out = 32'b00100000000000000000000000000000;
- 5'b11110 : out = 32'b01000000000000000000000000000000;
- 5'b11111 : out = 32'b10000000000000000000000000000000;
- endcase
- end
-endmodule
-
-module DEC6 (input [5:0] in, input enable, output reg [63:0] out);
-
-always @(in or enable)
- if(!enable)
- out = 64'b0000000000000000000000000000000000000000000000000000000000000000;
- else begin
- case (in)
- 6'b000000 : out = 64'b0000000000000000000000000000000000000000000000000000000000000001;
- 6'b000001 : out = 64'b0000000000000000000000000000000000000000000000000000000000000010;
- 6'b000010 : out = 64'b0000000000000000000000000000000000000000000000000000000000000100;
- 6'b000011 : out = 64'b0000000000000000000000000000000000000000000000000000000000001000;
- 6'b000100 : out = 64'b0000000000000000000000000000000000000000000000000000000000010000;
- 6'b000101 : out = 64'b0000000000000000000000000000000000000000000000000000000000100000;
- 6'b000110 : out = 64'b0000000000000000000000000000000000000000000000000000000001000000;
- 6'b000111 : out = 64'b0000000000000000000000000000000000000000000000000000000010000000;
- 6'b001000 : out = 64'b0000000000000000000000000000000000000000000000000000000100000000;
- 6'b001001 : out = 64'b0000000000000000000000000000000000000000000000000000001000000000;
- 6'b001010 : out = 64'b0000000000000000000000000000000000000000000000000000010000000000;
- 6'b001011 : out = 64'b0000000000000000000000000000000000000000000000000000100000000000;
- 6'b001100 : out = 64'b0000000000000000000000000000000000000000000000000001000000000000;
- 6'b001101 : out = 64'b0000000000000000000000000000000000000000000000000010000000000000;
- 6'b001110 : out = 64'b0000000000000000000000000000000000000000000000000100000000000000;
- 6'b001111 : out = 64'b0000000000000000000000000000000000000000000000001000000000000000;
- 6'b010000 : out = 64'b0000000000000000000000000000000000000000000000010000000000000000;
- 6'b010001 : out = 64'b0000000000000000000000000000000000000000000000100000000000000000;
- 6'b010010 : out = 64'b0000000000000000000000000000000000000000000001000000000000000000;
- 6'b010011 : out = 64'b0000000000000000000000000000000000000000000010000000000000000000;
- 6'b010100 : out = 64'b0000000000000000000000000000000000000000000100000000000000000000;
- 6'b010101 : out = 64'b0000000000000000000000000000000000000000001000000000000000000000;
- 6'b010110 : out = 64'b0000000000000000000000000000000000000000010000000000000000000000;
- 6'b010111 : out = 64'b0000000000000000000000000000000000000000100000000000000000000000;
- 6'b011000 : out = 64'b0000000000000000000000000000000000000001000000000000000000000000;
- 6'b011001 : out = 64'b0000000000000000000000000000000000000010000000000000000000000000;
- 6'b011010 : out = 64'b0000000000000000000000000000000000000100000000000000000000000000;
- 6'b011011 : out = 64'b0000000000000000000000000000000000001000000000000000000000000000;
- 6'b011100 : out = 64'b0000000000000000000000000000000000010000000000000000000000000000;
- 6'b011101 : out = 64'b0000000000000000000000000000000000100000000000000000000000000000;
- 6'b011110 : out = 64'b0000000000000000000000000000000001000000000000000000000000000000;
- 6'b011111 : out = 64'b0000000000000000000000000000000010000000000000000000000000000000;
-
- 6'b100000 : out = 64'b0000000000000000000000000000000100000000000000000000000000000000;
- 6'b100001 : out = 64'b0000000000000000000000000000001000000000000000000000000000000000;
- 6'b100010 : out = 64'b0000000000000000000000000000010000000000000000000000000000000000;
- 6'b100011 : out = 64'b0000000000000000000000000000100000000000000000000000000000000000;
- 6'b100100 : out = 64'b0000000000000000000000000001000000000000000000000000000000000000;
- 6'b100101 : out = 64'b0000000000000000000000000010000000000000000000000000000000000000;
- 6'b100110 : out = 64'b0000000000000000000000000100000000000000000000000000000000000000;
- 6'b100111 : out = 64'b0000000000000000000000001000000000000000000000000000000000000000;
- 6'b101000 : out = 64'b0000000000000000000000010000000000000000000000000000000000000000;
- 6'b101001 : out = 64'b0000000000000000000000100000000000000000000000000000000000000000;
- 6'b101010 : out = 64'b0000000000000000000001000000000000000000000000000000000000000000;
- 6'b101011 : out = 64'b0000000000000000000010000000000000000000000000000000000000000000;
- 6'b101100 : out = 64'b0000000000000000000100000000000000000000000000000000000000000000;
- 6'b101101 : out = 64'b0000000000000000001000000000000000000000000000000000000000000000;
- 6'b101110 : out = 64'b0000000000000000010000000000000000000000000000000000000000000000;
- 6'b101111 : out = 64'b0000000000000000100000000000000000000000000000000000000000000000;
- 6'b110000 : out = 64'b0000000000000001000000000000000000000000000000000000000000000000;
- 6'b110001 : out = 64'b0000000000000010000000000000000000000000000000000000000000000000;
- 6'b110010 : out = 64'b0000000000000100000000000000000000000000000000000000000000000000;
- 6'b110011 : out = 64'b0000000000001000000000000000000000000000000000000000000000000000;
- 6'b110100 : out = 64'b0000000000010000000000000000000000000000000000000000000000000000;
- 6'b110101 : out = 64'b0000000000100000000000000000000000000000000000000000000000000000;
- 6'b110110 : out = 64'b0000000001000000000000000000000000000000000000000000000000000000;
- 6'b110111 : out = 64'b0000000010000000000000000000000000000000000000000000000000000000;
- 6'b111000 : out = 64'b0000000100000000000000000000000000000000000000000000000000000000;
- 6'b111001 : out = 64'b0000001000000000000000000000000000000000000000000000000000000000;
- 6'b111010 : out = 64'b0000010000000000000000000000000000000000000000000000000000000000;
- 6'b111011 : out = 64'b0000100000000000000000000000000000000000000000000000000000000000;
- 6'b111100 : out = 64'b0001000000000000000000000000000000000000000000000000000000000000;
- 6'b111101 : out = 64'b0010000000000000000000000000000000000000000000000000000000000000;
- 6'b111110 : out = 64'b0100000000000000000000000000000000000000000000000000000000000000;
- 6'b111111 : out = 64'b1000000000000000000000000000000000000000000000000000000000000000;
- endcase
- end
-endmodule
-
-
-module MUX2(input [1:0] in, input select, output reg out);
-
-always @( in or select)
- case (select)
- 0: out = in[0];
- 1: out = in[1];
- endcase
-endmodule
-
-
-module MUX4(input [3:0] in, input [1:0] select, output reg out);
-
-always @( in or select)
- case (select)
- 0: out = in[0];
- 1: out = in[1];
- 2: out = in[2];
- 3: out = in[3];
- endcase
-endmodule
-
-
-module MUX8(input [7:0] in, input [2:0] select, output reg out);
-
-always @( in or select)
- case (select)
- 0: out = in[0];
- 1: out = in[1];
- 2: out = in[2];
- 3: out = in[3];
- 4: out = in[4];
- 5: out = in[5];
- 6: out = in[6];
- 7: out = in[7];
- endcase
-endmodule
-
-module MUX16(input [15:0] in, input [3:0] select, output reg out);
-
-always @( in or select)
- case (select)
- 0: out = in[0];
- 1: out = in[1];
- 2: out = in[2];
- 3: out = in[3];
- 4: out = in[4];
- 5: out = in[5];
- 6: out = in[6];
- 7: out = in[7];
- 8: out = in[8];
- 9: out = in[9];
- 10: out = in[10];
- 11: out = in[11];
- 12: out = in[12];
- 13: out = in[13];
- 14: out = in[14];
- 15: out = in[15];
- endcase
-endmodule
-
-module MUX32(input [31:0] in, input [4:0] select, output reg out);
-
-always @( in or select)
- case (select)
- 0: out = in[0];
- 1: out = in[1];
- 2: out = in[2];
- 3: out = in[3];
- 4: out = in[4];
- 5: out = in[5];
- 6: out = in[6];
- 7: out = in[7];
- 8: out = in[8];
- 9: out = in[9];
- 10: out = in[10];
- 11: out = in[11];
- 12: out = in[12];
- 13: out = in[13];
- 14: out = in[14];
- 15: out = in[15];
- 16: out = in[16];
- 17: out = in[17];
- 18: out = in[18];
- 19: out = in[19];
- 20: out = in[20];
- 21: out = in[21];
- 22: out = in[22];
- 23: out = in[23];
- 24: out = in[24];
- 25: out = in[25];
- 26: out = in[26];
- 27: out = in[27];
- 28: out = in[28];
- 29: out = in[29];
- 30: out = in[30];
- 31: out = in[31];
- endcase
-endmodule
-
-module MUX64(input [63:0] in, input [5:0] select, output reg out);
-
-always @( in or select)
- case (select)
- 0: out = in[0];
- 1: out = in[1];
- 2: out = in[2];
- 3: out = in[3];
- 4: out = in[4];
- 5: out = in[5];
- 6: out = in[6];
- 7: out = in[7];
- 8: out = in[8];
- 9: out = in[9];
- 10: out = in[10];
- 11: out = in[11];
- 12: out = in[12];
- 13: out = in[13];
- 14: out = in[14];
- 15: out = in[15];
- 16: out = in[16];
- 17: out = in[17];
- 18: out = in[18];
- 19: out = in[19];
- 20: out = in[20];
- 21: out = in[21];
- 22: out = in[22];
- 23: out = in[23];
- 24: out = in[24];
- 25: out = in[25];
- 26: out = in[26];
- 27: out = in[27];
- 28: out = in[28];
- 29: out = in[29];
- 30: out = in[30];
- 31: out = in[31];
- 32: out = in[32];
- 33: out = in[33];
- 34: out = in[34];
- 35: out = in[35];
- 36: out = in[36];
- 37: out = in[37];
- 38: out = in[38];
- 39: out = in[39];
- 40: out = in[40];
- 41: out = in[41];
- 42: out = in[42];
- 43: out = in[43];
- 44: out = in[44];
- 45: out = in[45];
- 46: out = in[46];
- 47: out = in[47];
- 48: out = in[48];
- 49: out = in[49];
- 50: out = in[50];
- 51: out = in[51];
- 52: out = in[52];
- 53: out = in[53];
- 54: out = in[54];
- 55: out = in[55];
- 56: out = in[56];
- 57: out = in[57];
- 58: out = in[58];
- 59: out = in[59];
- 60: out = in[60];
- 61: out = in[61];
- 62: out = in[62];
- 63: out = in[63];
- endcase
-endmodule
-
-module ADD1(input in1, in2, cin, output out, cout);
-
-assign {cout, out} = in1 + in2 + cin;
-
-endmodule
-
-module ADD2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2,
- input cin, output [SIZE-1:0] out, output cout);
-
-assign {cout, out} = in1 + in2 + cin;
-
-endmodule
-
-module ADD4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2,
- input cin, output [SIZE-1:0] out, output cout);
-
-assign {cout, out} = in1 + in2 + cin;
-
-endmodule
-
-module ADD8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2,
- input cin, output [SIZE-1:0] out, output cout);
-
-assign {cout, out} = in1 + in2 + cin;
-
-endmodule
-
-module ADD16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2,
- input cin, output [SIZE-1:0] out, output cout);
-
-assign {cout, out} = in1 + in2 + cin;
-
-endmodule
-
-module ADD32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2,
- input cin, output [SIZE-1:0] out, output cout);
-
-assign {cout, out} = in1 + in2 + cin;
-
-endmodule
-module ADD64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2,
- input cin, output [SIZE-1:0] out, output cout);
-
-assign {cout, out} = in1 + in2 + cin;
-
-endmodule
-
-module SUB1(input in1, in2, cin, output out, cout);
-
-assign {cout, out} = in1 - in2 - cin;
-
-endmodule
-
-module SUB2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2,
- input cin, output [SIZE-1:0] out, output cout);
-
-assign {cout, out} = in1 - in2 - cin;
-
-endmodule
-
-module SUB4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2,
- input cin, output [SIZE-1:0] out, output cout);
-
-assign {cout, out} = in1 - in2 - cin;
-
-endmodule
-
-module SUB8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2,
- input cin, output [SIZE-1:0] out, output cout);
-
-assign {cout, out} = in1 - in2 - cin;
-
-endmodule
-
-module SUB16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2,
- input cin, output [SIZE-1:0] out, output cout);
-
-assign {cout, out} = in1 - in2 - cin;
-
-endmodule
-
-module SUB32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2,
- input cin, output [SIZE-1:0] out, output cout);
-
-assign {cout, out} = in1 - in2 - cin;
-
-endmodule
-module SUB64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2,
- input cin, output [SIZE-1:0] out, output cout);
-
-assign {cout, out} = in1 - in2 - cin;
-
-endmodule
-
-module MUL1 #(parameter SIZE = 1)(input in1, in2, output [2*SIZE-1:0] out);
-
-assign out = in1*in2;
-
-endmodule
-
-module MUL2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);
-
-assign out = in1*in2;
-
-endmodule
-
-module MUL4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);
-
-assign out = in1*in2;
-
-endmodule
-
-module MUL8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);
-
-assign out = in1*in2;
-
-endmodule
-
-module MUL16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);
-
-assign out = in1*in2;
-
-endmodule
-
-module MUL32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);
-
-assign out = in1*in2;
-
-endmodule
-
-module MUL64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, output [2*SIZE-1:0] out);
-
-assign out = in1*in2;
-
-endmodule
-
-module DIV1 #(parameter SIZE = 1)(input in1, in2, output out, rem);
-
-assign out = in1/in2;
-assign rem = in1%in2;
-
-endmodule
-
-module DIV2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2,
- output [SIZE-1:0] out, rem);
-
-assign out = in1/in2;
-assign rem = in1%in2;
-
-endmodule
-
-module DIV4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2,
- output [SIZE-1:0] out, rem);
-
-assign out = in1/in2;
-assign rem = in1%in2;
-
-endmodule
-
-module DIV8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2,
- output [SIZE-1:0] out, rem);
-
-assign out = in1/in2;
-assign rem = in1%in2;
-
-endmodule
-
-module DIV16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2,
- output [SIZE-1:0] out, rem);
-
-assign out = in1/in2;
-assign rem = in1%in2;
-
-endmodule
-
-module DIV32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2,
- output [SIZE-1:0] out, rem);
-
-assign out = in1/in2;
-assign rem = in1%in2;
-
-endmodule
-
-module DIV64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2,
- output [SIZE-1:0] out, rem);
-
-assign out = in1/in2;
-assign rem = in1%in2;
-
-endmodule
-
-module FF (input d, clk, output reg q);
-always @( posedge clk)
- q <= d;
-endmodule
-
-
-module RFF(input d, clk, reset, output reg q);
-always @(posedge clk or posedge reset)
- if(reset)
- q <= 0;
- else
- q <= d;
-endmodule
-
-module SFF(input d, clk, set, output reg q);
-always @(posedge clk or posedge set)
- if(set)
- q <= 1;
- else
- q <= d;
-endmodule
-
-module RSFF(input d, clk, set, reset, output reg q);
-always @(posedge clk or posedge reset or posedge set)
- if(reset)
- q <= 0;
- else if(set)
- q <= 1;
- else
- q <= d;
-endmodule
-
-module SRFF(input d, clk, set, reset, output reg q);
-always @(posedge clk or posedge set or posedge reset)
- if(set)
- q <= 1;
- else if(reset)
- q <= 0;
- else
- q <= d;
-endmodule
-
-module LATCH(input d, enable, output reg q);
-always @( d or enable)
- if(enable)
- q <= d;
-endmodule
-
-module RLATCH(input d, reset, enable, output reg q);
-always @( d or enable or reset)
- if(enable)
- if(reset)
- q <= 0;
- else
- q <= d;
-endmodule
-
-module LSHIFT1 #(parameter SIZE = 1)(input in, shift, val, output reg out);
-
-always @ (in, shift, val) begin
- if(shift)
- out = val;
- else
- out = in;
-end
-
-endmodule
-
-
-module LSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in,
- input [SIZE-1:0] shift, input val,
- output reg [SIZE-1:0] out);
-
-always @(in or shift or val) begin
- out = in << shift;
- if(val)
- out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
-end
-endmodule
-
-module LSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in,
- input [2:0] shift, input val, output reg [SIZE-1:0] out);
-
-always @(in or shift or val) begin
- out = in << shift;
- if(val)
- out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
-end
-endmodule
-
-
-module LSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in,
- input [3:0] shift, input val, output reg [SIZE-1:0] out);
-
-always @(in or shift or val) begin
- out = in << shift;
- if(val)
- out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
-end
-endmodule
-
-module LSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in,
- input [4:0] shift, input val, output reg [SIZE-1:0] out);
-
-always @(in or shift or val) begin
- out = in << shift;
- if(val)
- out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
-end
-endmodule
-
-module LSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in,
- input [5:0] shift, input val, output reg [SIZE-1:0] out);
-
-always @(in or shift or val) begin
- out = in << shift;
- if(val)
- out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
-end
-endmodule
-
-module LSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in,
- input [6:0] shift, input val, output reg [SIZE-1:0] out);
-
-always @(in or shift or val) begin
- out = in << shift;
- if(val)
- out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
-end
-endmodule
-
-module RSHIFT1 #(parameter SIZE = 1)(input in, shift, val, output reg out);
-
-always @ (in, shift, val) begin
- if(shift)
- out = val;
- else
- out = in;
-end
-
-endmodule
-
-module RSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in,
- input [SIZE-1:0] shift, input val,
- output reg [SIZE-1:0] out);
-
-always @(in or shift or val) begin
- out = in >> shift;
- if(val)
- out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
-end
-
-endmodule
-
-
-module RSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in,
- input [2:0] shift, input val,
- output reg [SIZE-1:0] out);
-
-always @(in or shift or val) begin
- out = in >> shift;
- if(val)
- out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
-end
-endmodule
-
-module RSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in,
- input [3:0] shift, input val,
- output reg [SIZE-1:0] out);
-
-always @(in or shift or val) begin
- out = in >> shift;
- if(val)
- out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
-end
-
-endmodule
-
-module RSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in,
- input [4:0] shift, input val,
- output reg [SIZE-1:0] out);
-
-always @(in or shift or val) begin
- out = in >> shift;
- if(val)
- out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
-end
-endmodule
-
-
-module RSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in,
- input [5:0] shift, input val,
- output reg [SIZE-1:0] out);
-
-always @(in or shift or val) begin
- out = in >> shift;
- if(val)
- out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
-end
-endmodule
-
-module RSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in,
- input [6:0] shift, input val,
- output reg [SIZE-1:0] out);
-
-always @(in or shift or val) begin
- out = in >> shift;
- if(val)
- out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
-end
-endmodule
-
-module CMP1 #(parameter SIZE = 1) (input in1, in2,
- output reg equal, unequal, greater, lesser);
-
-always @ (in1 or in2) begin
- if(in1 == in2) begin
- equal = 1;
- unequal = 0;
- greater = 0;
- lesser = 0;
- end
- else begin
- equal = 0;
- unequal = 1;
-
- if(in1 < in2) begin
- greater = 0;
- lesser = 1;
- end
- else begin
- greater = 1;
- lesser = 0;
- end
- end
-end
-endmodule
-
-
-module CMP2 #(parameter SIZE = 2) (input [SIZE-1:0] in1, in2,
- output reg equal, unequal, greater, lesser);
-
-always @ (in1 or in2) begin
- if(in1 == in2) begin
- equal = 1;
- unequal = 0;
- greater = 0;
- lesser = 0;
- end
- else begin
- equal = 0;
- unequal = 1;
-
- if(in1 < in2) begin
- greater = 0;
- lesser = 1;
- end
- else begin
- greater = 1;
- lesser = 0;
- end
- end
-end
-endmodule
-
-module CMP4 #(parameter SIZE = 4) (input [SIZE-1:0] in1, in2,
- output reg equal, unequal, greater, lesser);
-
-always @ (in1 or in2) begin
- if(in1 == in2) begin
- equal = 1;
- unequal = 0;
- greater = 0;
- lesser = 0;
- end
- else begin
- equal = 0;
- unequal = 1;
-
- if(in1 < in2) begin
- greater = 0;
- lesser = 1;
- end
- else begin
- greater = 1;
- lesser = 0;
- end
- end
-end
-endmodule
-
-module CMP8 #(parameter SIZE = 8) (input [SIZE-1:0] in1, in2,
- output reg equal, unequal, greater, lesser);
-
-always @ (in1 or in2) begin
- if(in1 == in2) begin
- equal = 1;
- unequal = 0;
- greater = 0;
- lesser = 0;
- end
- else begin
- equal = 0;
- unequal = 1;
-
- if(in1 < in2) begin
- greater = 0;
- lesser = 1;
- end
- else begin
- greater = 1;
- lesser = 0;
- end
- end
-end
-endmodule
-
-module CMP16 #(parameter SIZE = 16) (input [SIZE-1:0] in1, in2,
- output reg equal, unequal, greater, lesser);
-
-always @ (in1 or in2) begin
- if(in1 == in2) begin
- equal = 1;
- unequal = 0;
- greater = 0;
- lesser = 0;
- end
- else begin
- equal = 0;
- unequal = 1;
-
- if(in1 < in2) begin
- greater = 0;
- lesser = 1;
- end
- else begin
- greater = 1;
- lesser = 0;
- end
- end
-end
-endmodule
-
-module CMP32 #(parameter SIZE = 32) (input [SIZE-1:0] in1, in2,
- output reg equal, unequal, greater, lesser);
-
-always @ (in1 or in2) begin
- if(in1 == in2) begin
- equal = 1;
- unequal = 0;
- greater = 0;
- lesser = 0;
- end
- else begin
- equal = 0;
- unequal = 1;
-
- if(in1 < in2) begin
- greater = 0;
- lesser = 1;
- end
- else begin
- greater = 1;
- lesser = 0;
- end
- end
-end
-endmodule
-
-module CMP64 #(parameter SIZE = 64) (input [SIZE-1:0] in1, in2,
- output reg equal, unequal, greater, lesser);
-
-always @ (in1 or in2) begin
- if(in1 == in2) begin
- equal = 1;
- unequal = 0;
- greater = 0;
- lesser = 0;
- end
- else begin
- equal = 0;
- unequal = 1;
-
- if(in1 < in2) begin
- greater = 0;
- lesser = 1;
- end
- else begin
- greater = 1;
- lesser = 0;
- end
- end
-end
-endmodule
-
-module VCC (output supply1 out);
-endmodule
-
-module GND (output supply0 out);
-endmodule
-
-
-module INC1 #(parameter SIZE = 1) (input in, output [SIZE:0] out);
-
-assign out = in + 1;
-
-endmodule
-
-module INC2 #(parameter SIZE = 2) (input [SIZE-1:0] in, output [SIZE:0] out);
-
-assign out = in + 1;
-
-endmodule
-
-module INC4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output [SIZE:0] out);
-assign out = in + 1;
-
-endmodule
-
-module INC8 #(parameter SIZE = 8) (input [SIZE-1:0] in, output [SIZE:0] out);
-assign out = in + 1;
-
-endmodule
-
-module INC16 #(parameter SIZE = 16) (input [SIZE-1:0] in, output [SIZE:0] out);
-assign out = in + 1;
-
-endmodule
-
-module INC32 #(parameter SIZE = 32) (input [SIZE-1:0] in, output [SIZE:0] out);
-assign out = in + 1;
-
-endmodule
-module INC64 #(parameter SIZE = 64) (input [SIZE-1:0] in, output [SIZE:0] out);
-assign out = in + 1;
-
-endmodule
-
+++ /dev/null
-
-module cell0(Result0);
-output Result0;
-assign Result0 = 0;
-endmodule
-
-module cell1(Result0);
-output Result0;
-assign Result0 = 1;
-endmodule
-
-module ADD4(
- DataA0, DataA1, DataA2, DataA3,
- DataB0, DataB1, DataB2, DataB3,
- Result0, Result1, Result2, Result3, Cout
-);
-input DataA0, DataA1, DataA2, DataA3;
-input DataB0, DataB1, DataB2, DataB3;
-output Result0, Result1, Result2, Result3, Cout;
-assign {Cout, Result3, Result2, Result1, Result0} = {DataA3, DataA2, DataA1, DataA0} + {DataB3, DataB2, DataB1, DataB0};
-endmodule
-
-module BUF(DATA, RESULT);
-input DATA;
-output RESULT;
-assign RESULT = DATA;
-endmodule
-
-module INV(DATA, RESULT);
-input DATA;
-output RESULT;
-assign RESULT = ~DATA;
-endmodule
-
-module fd4(
- Clock,
- Data0, Data1, Data2, Data3,
- Q0, Q1, Q2, Q3
-);
-input Clock;
-input Data0, Data1, Data2, Data3;
-output reg Q0, Q1, Q2, Q3;
-always @(posedge Clock)
- {Q0, Q1, Q2, Q3} <= {Data0, Data1, Data2, Data3};
-endmodule
-
-module fdce1(
- Clock, Enable,
- Data0,
- Q0
-);
-input Clock, Enable;
-input Data0;
-output reg Q0;
-always @(posedge Clock)
- if (Enable)
- Q0 <= Data0;
-endmodule
-
-module fdce4(
- Clock, Enable,
- Data0, Data1, Data2, Data3,
- Q0, Q1, Q2, Q3
-);
-input Clock, Enable;
-input Data0, Data1, Data2, Data3;
-output reg Q0, Q1, Q2, Q3;
-always @(posedge Clock)
- if (Enable)
- {Q0, Q1, Q2, Q3} <= {Data0, Data1, Data2, Data3};
-endmodule
-
-module mux4_1_2(
- Sel0,
- Data0x0, Data0x1, Data0x2, Data0x3,
- Data1x0, Data1x1, Data1x2, Data1x3,
- Result0, Result1, Result2, Result3
-);
-input Sel0;
-input Data0x0, Data0x1, Data0x2, Data0x3;
-input Data1x0, Data1x1, Data1x2, Data1x3;
-output Result0, Result1, Result2, Result3;
-assign {Result0, Result1, Result2, Result3} = Sel0 ? {Data1x0, Data1x1, Data1x2, Data1x3} : {Data0x0, Data0x1, Data0x2, Data0x3};
-endmodule
-
-module mux1_1_2(
- Sel0,
- Data0x0,
- Data1x0,
- Result0
-);
-input Sel0;
-input Data0x0;
-input Data1x0;
-output Result0;
-assign Result0 = Sel0 ? Data1x0 : Data0x0;
-endmodule
-
-module xor2(
- DATA0X0,
- DATA1X0,
- RESULT0
-);
-input DATA0X0;
-input DATA1X0;
-output RESULT0;
-assign RESULT0 = DATA1X0 ^ DATA0X0;
-endmodule
-
-module fdce64(
- Clock, Enable,
- Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8, Data9, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, Data32, Data33, Data34, Data35, Data36, Data37, Data38, Data39, Data40, Data41, Data42, Data43, Data44, Data45, Data46, Data47, Data48, Data49, Data50, Data51, Data52, Data53, Data54, Data55, Data56, Data57, Data58, Data59, Data60, Data61, Data62, Data63,
- Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q39, Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q49, Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q59, Q60, Q61, Q62, Q63
-);
-input Clock, Enable;
-input Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8, Data9, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, Data32, Data33, Data34, Data35, Data36, Data37, Data38, Data39, Data40, Data41, Data42, Data43, Data44, Data45, Data46, Data47, Data48, Data49, Data50, Data51, Data52, Data53, Data54, Data55, Data56, Data57, Data58, Data59, Data60, Data61, Data62, Data63;
-output reg Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q39, Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q49, Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q59, Q60, Q61, Q62, Q63;
-always @(posedge Clock)
- if (Enable)
- { Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q39, Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q49, Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q59, Q60, Q61, Q62, Q63 } <= { Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8, Data9, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, Data32, Data33, Data34, Data35, Data36, Data37, Data38, Data39, Data40, Data41, Data42, Data43, Data44, Data45, Data46, Data47, Data48, Data49, Data50, Data51, Data52, Data53, Data54, Data55, Data56, Data57, Data58, Data59, Data60, Data61, Data62, Data63 };
-endmodule
-
-module mux4_4_16(
- Sel0, Sel1, Sel2, Sel3,
- Result0, Result1, Result2, Result3,
- Data0x0, Data0x1, Data0x2, Data0x3,
- Data1x0, Data1x1, Data1x2, Data1x3,
- Data2x0, Data2x1, Data2x2, Data2x3,
- Data3x0, Data3x1, Data3x2, Data3x3,
- Data4x0, Data4x1, Data4x2, Data4x3,
- Data5x0, Data5x1, Data5x2, Data5x3,
- Data6x0, Data6x1, Data6x2, Data6x3,
- Data7x0, Data7x1, Data7x2, Data7x3,
- Data8x0, Data8x1, Data8x2, Data8x3,
- Data9x0, Data9x1, Data9x2, Data9x3,
- Data10x0, Data10x1, Data10x2, Data10x3,
- Data11x0, Data11x1, Data11x2, Data11x3,
- Data12x0, Data12x1, Data12x2, Data12x3,
- Data13x0, Data13x1, Data13x2, Data13x3,
- Data14x0, Data14x1, Data14x2, Data14x3,
- Data15x0, Data15x1, Data15x2, Data15x3
-);
-input Sel0, Sel1, Sel2, Sel3;
-output Result0, Result1, Result2, Result3;
-input Data0x0, Data0x1, Data0x2, Data0x3;
-input Data1x0, Data1x1, Data1x2, Data1x3;
-input Data2x0, Data2x1, Data2x2, Data2x3;
-input Data3x0, Data3x1, Data3x2, Data3x3;
-input Data4x0, Data4x1, Data4x2, Data4x3;
-input Data5x0, Data5x1, Data5x2, Data5x3;
-input Data6x0, Data6x1, Data6x2, Data6x3;
-input Data7x0, Data7x1, Data7x2, Data7x3;
-input Data8x0, Data8x1, Data8x2, Data8x3;
-input Data9x0, Data9x1, Data9x2, Data9x3;
-input Data10x0, Data10x1, Data10x2, Data10x3;
-input Data11x0, Data11x1, Data11x2, Data11x3;
-input Data12x0, Data12x1, Data12x2, Data12x3;
-input Data13x0, Data13x1, Data13x2, Data13x3;
-input Data14x0, Data14x1, Data14x2, Data14x3;
-input Data15x0, Data15x1, Data15x2, Data15x3;
-assign {Result0, Result1, Result2, Result3} =
- {Sel3, Sel2, Sel1, Sel0} == 0 ? { Data0x0, Data0x1, Data0x2, Data0x3 } :
- {Sel3, Sel2, Sel1, Sel0} == 1 ? { Data1x0, Data1x1, Data1x2, Data1x3 } :
- {Sel3, Sel2, Sel1, Sel0} == 2 ? { Data2x0, Data2x1, Data2x2, Data2x3 } :
- {Sel3, Sel2, Sel1, Sel0} == 3 ? { Data3x0, Data3x1, Data3x2, Data3x3 } :
- {Sel3, Sel2, Sel1, Sel0} == 4 ? { Data4x0, Data4x1, Data4x2, Data4x3 } :
- {Sel3, Sel2, Sel1, Sel0} == 5 ? { Data5x0, Data5x1, Data5x2, Data5x3 } :
- {Sel3, Sel2, Sel1, Sel0} == 6 ? { Data6x0, Data6x1, Data6x2, Data6x3 } :
- {Sel3, Sel2, Sel1, Sel0} == 7 ? { Data7x0, Data7x1, Data7x2, Data7x3 } :
- {Sel3, Sel2, Sel1, Sel0} == 8 ? { Data8x0, Data8x1, Data8x2, Data8x3 } :
- {Sel3, Sel2, Sel1, Sel0} == 9 ? { Data9x0, Data9x1, Data9x2, Data9x3 } :
- {Sel3, Sel2, Sel1, Sel0} == 10 ? { Data10x0, Data10x1, Data10x2, Data10x3 } :
- {Sel3, Sel2, Sel1, Sel0} == 11 ? { Data11x0, Data11x1, Data11x2, Data11x3 } :
- {Sel3, Sel2, Sel1, Sel0} == 12 ? { Data12x0, Data12x1, Data12x2, Data12x3 } :
- {Sel3, Sel2, Sel1, Sel0} == 13 ? { Data13x0, Data13x1, Data13x2, Data13x3 } :
- {Sel3, Sel2, Sel1, Sel0} == 14 ? { Data14x0, Data14x1, Data14x2, Data14x3 } :
- {Sel3, Sel2, Sel1, Sel0} == 15 ? { Data15x0, Data15x1, Data15x2, Data15x3 } : 'bx;
-endmodule
-
-module mux1_5_32(
- Sel0, Sel1, Sel2, Sel3, Sel4,
- Data0x0, Data1x0, Data2x0, Data3x0, Data4x0, Data5x0, Data6x0, Data7x0, Data8x0, Data9x0, Data10x0, Data11x0, Data12x0, Data13x0, Data14x0, Data15x0,
- Data16x0, Data17x0, Data18x0, Data19x0, Data20x0, Data21x0, Data22x0, Data23x0, Data24x0, Data25x0, Data26x0, Data27x0, Data28x0, Data29x0, Data30x0, Data31x0,
- Result0
-);
-input Sel0, Sel1, Sel2, Sel3, Sel4;
-input Data0x0, Data1x0, Data2x0, Data3x0, Data4x0, Data5x0, Data6x0, Data7x0, Data8x0, Data9x0, Data10x0, Data11x0, Data12x0, Data13x0, Data14x0, Data15x0;
-input Data16x0, Data17x0, Data18x0, Data19x0, Data20x0, Data21x0, Data22x0, Data23x0, Data24x0, Data25x0, Data26x0, Data27x0, Data28x0, Data29x0, Data30x0, Data31x0;
-output Result0;
-assign Result0 =
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 0 ? Data0x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 1 ? Data1x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 2 ? Data2x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 3 ? Data3x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 4 ? Data4x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 5 ? Data5x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 6 ? Data6x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 7 ? Data7x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 8 ? Data8x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 9 ? Data9x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 10 ? Data10x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 11 ? Data11x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 12 ? Data12x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 13 ? Data13x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 14 ? Data14x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 15 ? Data15x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 16 ? Data16x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 17 ? Data17x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 18 ? Data18x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 19 ? Data19x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 20 ? Data20x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 21 ? Data21x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 22 ? Data22x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 23 ? Data23x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 24 ? Data24x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 25 ? Data25x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 26 ? Data26x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 27 ? Data27x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 28 ? Data28x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 29 ? Data29x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 30 ? Data30x0 :
- {Sel4, Sel3, Sel2, Sel1, Sel0} == 31 ? Data31x0 : 'bx;
-endmodule
-
+++ /dev/null
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- * ---
- *
- * The internal logic cell simulation library.
- *
- * This verilog library contains simple simulation models for the internal
- * logic cells (_INV_, _AND_, ...) that are generated by the default technology
- * mapper (see "stdcells.v" in this directory) and expected by the "abc" pass.
- *
- */
-
-module _INV_(A, Y);
-input A;
-output Y;
-assign Y = ~A;
-endmodule
-
-module _AND_(A, B, Y);
-input A, B;
-output Y;
-assign Y = A & B;
-endmodule
-
-module _OR_(A, B, Y);
-input A, B;
-output Y;
-assign Y = A | B;
-endmodule
-
-module _XOR_(A, B, Y);
-input A, B;
-output Y;
-assign Y = A ^ B;
-endmodule
-
-module _MUX_(A, B, S, Y);
-input A, B, S;
-output reg Y;
-always @* begin
- if (S)
- Y = B;
- else
- Y = A;
-end
-endmodule
-
-module _DFF_N_(D, Q, C);
-input D, C;
-output reg Q;
-always @(negedge C) begin
- Q <= D;
-end
-endmodule
-
-module _DFF_P_(D, Q, C);
-input D, C;
-output reg Q;
-always @(posedge C) begin
- Q <= D;
-end
-endmodule
-
-module _DFF_NN0_(D, Q, C, R);
-input D, C, R;
-output reg Q;
-always @(negedge C or negedge R) begin
- if (R == 0)
- Q <= 0;
- else
- Q <= D;
-end
-endmodule
-
-module _DFF_NN1_(D, Q, C, R);
-input D, C, R;
-output reg Q;
-always @(negedge C or negedge R) begin
- if (R == 0)
- Q <= 1;
- else
- Q <= D;
-end
-endmodule
-
-module _DFF_NP0_(D, Q, C, R);
-input D, C, R;
-output reg Q;
-always @(negedge C or posedge R) begin
- if (R == 1)
- Q <= 0;
- else
- Q <= D;
-end
-endmodule
-
-module _DFF_NP1_(D, Q, C, R);
-input D, C, R;
-output reg Q;
-always @(negedge C or posedge R) begin
- if (R == 1)
- Q <= 1;
- else
- Q <= D;
-end
-endmodule
-
-module _DFF_PN0_(D, Q, C, R);
-input D, C, R;
-output reg Q;
-always @(posedge C or negedge R) begin
- if (R == 0)
- Q <= 0;
- else
- Q <= D;
-end
-endmodule
-
-module _DFF_PN1_(D, Q, C, R);
-input D, C, R;
-output reg Q;
-always @(posedge C or negedge R) begin
- if (R == 0)
- Q <= 1;
- else
- Q <= D;
-end
-endmodule
-
-module _DFF_PP0_(D, Q, C, R);
-input D, C, R;
-output reg Q;
-always @(posedge C or posedge R) begin
- if (R == 1)
- Q <= 0;
- else
- Q <= D;
-end
-endmodule
-
-module _DFF_PP1_(D, Q, C, R);
-input D, C, R;
-output reg Q;
-always @(posedge C or posedge R) begin
- if (R == 1)
- Q <= 1;
- else
- Q <= D;
-end
-endmodule
-
+++ /dev/null
-Some minor build fixes for sis-1.3.6 as it can be downloaded from
-http://www-cad.eecs.berkeley.edu/~pchong/sis.html or
-http://embedded.eecs.berkeley.edu/Alumni/pchong/sis.html
-
-diff --git a/sis/io/read_kiss.c b/sis/io/read_kiss.c
-index 814e526..c862892 100644
---- a/sis/io/read_kiss.c
-+++ b/sis/io/read_kiss.c
-@@ -10,7 +10,6 @@
- #ifdef SIS
- #include "sis.h"
-
--extern void read_error();
- extern int read_lineno;
- extern char *read_filename;
-
-diff --git a/sis/pld/act_bdd.c b/sis/pld/act_bdd.c
-index 4fb4415..a5cd74c 100644
---- a/sis/pld/act_bdd.c
-+++ b/sis/pld/act_bdd.c
-@@ -141,6 +141,8 @@ char *name;
- return p_vertex;
- }
-
-+static int compare();
-+
- /* Or 2 ACT's*/
- act_t *
- my_or_act_F(array_b,cover, array)
-@@ -148,7 +150,6 @@ array_t *array_b;
- array_t *array;
- sm_row *cover;
- {
-- static int compare();
- int i;
- act_t *up_vertex, *down_vertex, *vertex;
- sm_element *p;
-diff --git a/sis/pld/act_ite.c b/sis/pld/act_ite.c
-index a35f2fb..7b824df 100644
---- a/sis/pld/act_ite.c
-+++ b/sis/pld/act_ite.c
-@@ -125,6 +125,8 @@ node_t *fanin;
- and the minimum column cover variables in cover, generates an ite for the
- original function. */
-
-+static int compare();
-+
- ite_vertex *
- my_or_ite_F(array_b, cover, array, network)
- array_t *array_b;
-@@ -132,7 +134,6 @@ array_t *array;
- sm_row *cover;
- network_t *network;
- {
-- static int compare();
- int i;
- ite_vertex *vertex;
- sm_element *p;
-diff --git a/sis/pld/xln_merge.c b/sis/pld/xln_merge.c
-index 075e6c5..16f4d61 100644
---- a/sis/pld/xln_merge.c
-+++ b/sis/pld/xln_merge.c
-@@ -284,6 +284,7 @@ array_t *match1_array, *match2_array;
-
- }
-
-+static sm_row *xln_merge_find_neighbor_of_row1_with_minimum_neighbors();
- \f
- /*----------------------------------------------------------------------------------------------------
- An alternate to lindo option. Uses greedy merging. A node with minimum mergeable nodes is picked
-@@ -296,7 +297,6 @@ xln_merge_nodes_without_lindo(coeff, cand_node_array, match1_array, match2_array
- {
- node_t *n1, *n2;
- sm_row *row1, *row2;
-- static sm_row *xln_merge_find_neighbor_of_row1_with_minimum_neighbors();
-
- while (TRUE) {
- row1 = sm_shortest_row(coeff);
-diff --git a/sis/pld/xln_part_dec.c b/sis/pld/xln_part_dec.c
-index 1c856bd..b78828a 100644
---- a/sis/pld/xln_part_dec.c
-+++ b/sis/pld/xln_part_dec.c
-@@ -49,13 +49,14 @@ int size;
-
- \f
-
-+static int kernel_value();
-+
- int
- split_node(network, node, size)
- network_t *network;
- node_t *node;
- int size;
- {
-- static int kernel_value();
- int i, value = 1;
- kern_node *sorted;
- divisor_t *div, *best_div;
-diff --git a/xsis/Makefile.am b/xsis/Makefile.am
-index 196d98b..686fdf4 100644
---- a/xsis/Makefile.am
-+++ b/xsis/Makefile.am
-@@ -1,8 +1,8 @@
- xsis_SOURCES_local = NetPlot.c NetPlot.h NetPlotP.h main.c xastg.c \
- xblif.c xcmd.c xhelp.c xsis.c xsis.h xutil.c \
- blif50.px ghost.px help50.px sis50.px
--AM_CPPFLAGS = -I../sis/include -I@SIS_X_INCLUDES@
--AM_LDFLAGS = -L@SIS_X_LIBRARIES@
-+AM_CPPFLAGS = -I../sis/include
-+AM_LDFLAGS =
- LDADD = ../sis/libsis.a -lXaw -lXmu -lXt -lXext -lX11 -lm
-
- if SIS_COND_X
+++ /dev/null
-#!/bin/bash
-
-yosys_bin="/usr/local/synthesis/src/yosys/yosys"
-hana_bin="/usr/local/synthesis/src/hana/bin/hana"
-vl2mv_bin="/usr/local/synthesis/bin/vl2mv"
-vis_bin="/usr/local/synthesis/bin/vis"
-iverilog_bin="/usr/local/synthesis/bin/iverilog-0.8"
-odin_bin="/usr/local/synthesis/src/vtr_release/ODIN_II/odin_II.exe"
-abc_bin="/usr/local/synthesis/src/alanmi-abc-b5750272659f/abc"
-edif2ngd="/opt/Xilinx/14.3/ISE_DS/ISE/bin/lin64/edif2ngd"
-netgen="/opt/Xilinx/14.3/ISE_DS/ISE/bin/lin64/netgen"
-
-all_modes="yosys hana vis icarus odin"
-all_sources="always01 always02 always03 arrays01 forgen01 forgen02"
-
-if [ "$*" == "ALL" ]; then
- for mode in $all_modes; do
- for src in $all_sources; do
- echo "synth.sh $mode $src.v ${src}_${mode}.v"
- ( set -x; bash synth.sh $mode $src.v ${src}_${mode}.v || rm -f ${src}_${mode}.v; ) > ${src}_${mode}.log 2>&1
- done
- done
- exit
-fi
-
-mode="$1"
-source="$2"
-output="$3"
-prefix="${output%.v}"
-
-help() {
- echo "$0 ALL" >&2
- echo "$0 {yosys|hana|vis|icarus|odin} <source-file> <output-file>" >&2
- exit 1
-}
-
-if [ "$#" != 3 -o ! -f "$source" ]; then
- help
-fi
-
-set -ex
-
-case "$mode" in
- yosys)
- $yosys_bin -o $output -b "verilog -noattr" -p proc -p opt -p memory -p opt -p techmap -p opt $source ;;
- hana)
- $hana_bin -s $output $source ;;
- vis)
- $vl2mv_bin -o $prefix.mv $source
- { echo "read_blif_mv $prefix.mv"; echo "write_verilog $output"; } | $abc_bin ;;
- icarus)
- rm -f $prefix.ngo $prefix.v
- $iverilog_bin -t fpga -o $prefix.edif $source
- $edif2ngd $prefix.edif $prefix.ngo
- $netgen -ofmt verilog $prefix.ngo $prefix.v
- sed -re '/timescale/ s,^,//,;' -i $prefix.v ;;
- odin)
- $odin_bin -o $prefix.blif -V $source
- sed -re 's,top\^,,g; s,clock,_clock,g;' -i $prefix.blif
- { echo "read_blif $prefix.blif"; echo "write_verilog $output"; } | $abc_bin ;;
- *)
- help
-esac
-
+++ /dev/null
-#!/bin/bash
-
-set -ex
-
-yosys_bin="/usr/local/synthesis/src/yosys/yosys"
-iverilog_bin="iverilog"
-
-all_modes="yosys hana vis icarus odin"
-all_sources="always01 always02 always03 arrays01 forgen01 forgen02"
-
-gcc -o cmp_tbdata cmp_tbdata.c
-
-for src in $all_sources; do
- echo; echo
- $yosys_bin -o ${src}_tb.v -b autotest ${src}.v
- $iverilog_bin -o ${src}_tb ${src}_tb.v ${src}.v
- ./${src}_tb > ${src}_tb.out
- for mode in $all_modes; do
- simlib=""
- [ -f ${src}_${mode}.v ] || continue
- [ -f simlib_${mode}.v ] && simlib="simlib_${mode}.v"
- if $iverilog_bin -o ${src}_${mode}_tb -s testbench ${src}_tb.v ${src}_${mode}.v $simlib; then
- ./${src}_${mode}_tb > ${src}_${mode}_tb.out
- else
- rm -f ${src}_${mode}_tb.out
- fi
- done
-done
-
-set +x
-echo; echo; echo
-
-{
- for mode in $all_modes; do
- echo -en "\t$mode"
- done; echo
-
- for src in $all_sources; do
- echo -n "$src"
- for mode in $all_modes; do
- if [ -f ${src}_${mode}.v ]; then
- if [ ! -s ${src}_${mode}_tb.out ]; then
- echo -en "\tmissing"
- elif ./cmp_tbdata ${src}_tb.out ${src}_${mode}_tb.out; then
- echo -en "\tok"
- else
- echo -en "\tfailed"
- fi
- else
- echo -en "\terror"
- fi
- done; echo
- done
-} | expand -t12
-
projects / yosys.git / commitdiff