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diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn
index 80f3d08fe92c21ab85b9b1ba8d7c4c1785e046f8..9e747abc022d6db001d15cf18bf4436f6ce306a7 100644 (file)
--- a/openpower/sv/mv.swizzle.mdwn
+++ b/openpower/sv/mv.swizzle.mdwn
@@ -118,8 +118,15 @@ of storing four 64-bit in-flight elements may be considered
 too high. If this is the
 case it is acceptable to throw an Illegal Instruction Trap, and emulate
 the instruction in software. Performance will obviously be adversely affected.
-See [[sv/compliancy_levels]]*: all aspects of
-Swizzle are entirely optional in hardware at the Embedded Level.
+See [[sv/compliancy_levels]]: all aspects of
+Swizzle are entirely optional in hardware at the Embedded Level.*
+
+Implementors must consider `SUBVL` to have been implicitly set by
+the Swizzle instructions. Hardware may statically calculate `SUBVL`
+from the immediate.  "W.0Z" is SUBVL=4, where "X0Z." is SUBVL=3,
+and ".W.." sets SUBVL=2.  Setting `SUBVL` has a different meaning
+in Swizzle Move instructions,
+as explained below.
 
 # RM Mode Concept:
 
@@ -132,6 +139,7 @@ MVRM-2P-2S1D:
 | src_SUBVL    | `14:15`  | SUBVL for Source              |
 | MASK_SRC     | `16:18`  | Execution Mask for Source     |
 
-The inclusion of a separate src SUBVL would allow either
-`sv.mv.swiz RT.vecN RA.vecN` to mean contiguous sequential copy
-or it could mean zip/unzip (pack/unpack).
+The inclusion of a separate src SUBVL allows
+`sv.mv.swiz RT.vecN RA.vecN` to mean zip/unzip (pack/unpack).
+This is conceptually achieved by having both source and
+destination SUBVL be "outer" loops instead of inner loops.