Fix ignoring of simulation timings so that invalid module parameters cause syntax...

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 885332b762d38d443f877e48c797e6d417aa2631..07d85bed8fbe8cc2df34f363aff6e79924d064d4 100644 (file)
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -389,10 +389,6 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
 \\[\r\n]               /* ignore continuation sequence */
 "//"[^\r\n]*           /* ignore one-line comments */
 
-"#"\ *[0-9][0-9_]*                     /* ignore simulation timings */
-"#"\ *[0-9][0-9_]*\.[0-9][0-9_]*       /* ignore simulation timings */
-"#"\ *[$a-zA-Z_\.][$a-zA-Z_0-9\.]*     /* ignore simulation timings */
-
 . { return *yytext; }
 
 %%

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index c5ff3d402ecc3b42031fdca966b3249d845df658..9fa2a1a2f7a57c2ee38afcac9d2fdb4236d4ce9d 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -355,6 +355,8 @@ package_body_stmt:
        localparam_decl;
 
 non_opt_delay:
+       '#' TOK_ID { delete $2; } |
+       '#' TOK_CONSTVAL { delete $2; } |
        '#' '(' expr ')' { delete $3; } |
        '#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };