\frame{\frametitle{Credits and Acknowledgements}
\begin{itemize}
- \item The Designers of RISC-V\vspace{15pt}
- \item The Shakti Group\vspace{15pt}
- \item Prof. G S Madhusudan\vspace{15pt}
- \item Neel Gala\vspace{15pt}
- \item Rishabh Jain\vspace{15pt}
+ \item The Designers of RISC-V\vspace{8pt}
+ \item The RISC-V Foundation\vspace{8pt}
+ \item The Shakti Group, and IIT Madras RISE Group\vspace{8pt}
+ \item Prof. G S Madhusudan\vspace{8pt}
+ \item Neel Gala\vspace{8pt}
+ \item Rishabh Jain\vspace{8pt}
+ \item Members of the RISC-V Open Groups (SW/HW/ISA)\vspace{8pt}
+ \item Libre and Open Software and Hardware Communities
\end{itemize}
}
\begin{itemize}
\item DDR3/4 PHYs are analog and very high speed.
Impedance training. Extreme timing tolerances on parallel buses.\\
- No surprise they cost USD \$1m and above.
+ No surprise proprietary cost is USD \$1m and above.
\item Symbiotic EDA will do (Libre) PHY layout for USD \$300k,
time to completion for chosen geometry: 8-12 months.
\end{itemize}