Fix PR63190

From-SVN: r215004

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e32812cf522ff2e802eb5457e5e29a7efd363e31..6a8aec7bdd834eb053efa2dfba8223b311c43929 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2014-09-07 Venkataramanan Kumar <venkataramanan.kumar@linaro.org>
+
+       PR target/63190
+       * config/aarch64/aarch64.md (stack_protect_test_<mode>) Add register
+       constraint for operand0 and remove write only modifier from operand3.
+
 2014-09-07  Richard Sandiford  <rdsandiford@googlemail.com>
 
        PR rtl-optimization/62208

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 6e63881f1f024d8001076e77594098c9c0b79921..c60038a9015d614f40f6d9e3fd228ad3e2b247a8 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -4027,11 +4027,11 @@
 })
 
 (define_insn "stack_protect_test_<mode>"
-  [(set (match_operand:PTR 0 "register_operand")
+  [(set (match_operand:PTR 0 "register_operand" "=r")
        (unspec:PTR [(match_operand:PTR 1 "memory_operand" "m")
                     (match_operand:PTR 2 "memory_operand" "m")]
         UNSPEC_SP_TEST))
-   (clobber (match_scratch:PTR 3 "=&r"))]
+   (clobber (match_scratch:PTR 3 "&r"))]
   ""
   "ldr\t%<w>3, %x1\;ldr\t%<w>0, %x2\;eor\t%<w>0, %<w>3, %<w>0"
   [(set_attr "length" "12")