_numVecElemDestRegs = 0;
_numIntDestRegs = 0;
_numCCDestRegs = 0;
- _destRegIdx[_numDestRegs++] = RegId(IntRegClass, dest);
+ setDestRegIdx(_numDestRegs++, RegId(IntRegClass, dest));
_numIntDestRegs++;
flags[IsHtmStart] = true;
flags[IsInteger] = true;
_numVecElemDestRegs = 0;
_numIntDestRegs = 0;
_numCCDestRegs = 0;
- _destRegIdx[_numDestRegs++] = RegId(IntRegClass, dest);
+ setDestRegIdx(_numDestRegs++, RegId(IntRegClass, dest));
_numIntDestRegs++;
flags[IsInteger] = true;
flags[IsMicroop] = true;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
flags[IsCondControl] = true;
} else {
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
flags[IsCondControl] = true;
} else {
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
flags[IsCondControl] = true;
} else {
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
if (!(condCode == COND_AL || condCode == COND_UC)) {
flags[IsCondControl] = true;
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
} else {
flags[IsUncondControl] = true;
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
#if %(use_uops)d
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
#if %(use_uops)d
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
#if %(use_uops)d
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
#if %(use_uops)d
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
#if %(use_uops)d
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
#if %(use_uops)d
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
#if %(use_uops)d
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
#if %(use_uops)d
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
#if %(use_uops)d
if (!(condCode == COND_AL || condCode == COND_UC)) {
conditional = true;
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
#if %(use_uops)d
if (!(condCode == COND_AL || condCode == COND_UC)) {
conditional = true;
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
#if %(use_uops)d
uint32_t r2 = RegId(IntRegClass, result).index() + 1 ;
d2_src = _numSrcRegs ;
- _srcRegIdx[_numSrcRegs++] = RegId(IntRegClass, d2);
+ setSrcRegIdx(_numSrcRegs++, RegId(IntRegClass, d2));
r2_src = _numSrcRegs ;
- _srcRegIdx[_numSrcRegs++] = RegId(IntRegClass, r2);
+ setSrcRegIdx(_numSrcRegs++, RegId(IntRegClass, r2));
r2_dst = _numDestRegs ;
- _destRegIdx[_numDestRegs++] = RegId(IntRegClass, r2);
+ setDestRegIdx(_numDestRegs++, RegId(IntRegClass, r2));
flags[IsStore] = false;
flags[IsLoad] = false;
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
// The first micro-op is responsible for pinning the
// destination and the fault status registers
assert(_numDestRegs == 2);
- _destRegIdx[0].setNumPinnedWrites(numElems - 1);
- _destRegIdx[1].setNumPinnedWrites(numElems - 1);
+ for (int i = 0; i < _numDestRegs; i++) {
+ auto dr = destRegIdx(i);
+ dr.setNumPinnedWrites(numElems - 1);
+ setDestRegIdx(i, dr);
+ }
}
}
// The first micro-op is responsible for pinning the
// destination and the fault status registers
assert(_numDestRegs == 2);
- _destRegIdx[0].setNumPinnedWrites(numElems - 1);
- _destRegIdx[1].setNumPinnedWrites(numElems - 1);
+ for (int i = 0; i < _numDestRegs; i++) {
+ auto dr = destRegIdx(i);
+ dr.setNumPinnedWrites(numElems - 1);
+ setDestRegIdx(i, dr);
+ }
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
}
}
}
derived classes encapsulates the traits of a particular operand
type (e.g., "32-bit integer register").'''
- src_reg_constructor = '\n\t_srcRegIdx[_numSrcRegs++] = RegId(%s, %s);'
- dst_reg_constructor = '\n\t_destRegIdx[_numDestRegs++] = RegId(%s, %s);'
+ src_reg_constructor = '\n\tsetSrcRegIdx(_numSrcRegs++, RegId(%s, %s));'
+ dst_reg_constructor = '\n\tsetDestRegIdx(_numDestRegs++, RegId(%s, %s));'
def buildReadCode(self, func = None):
subst_dict = {"name": self.base_name,
numAccessNeeded = 1
if self.is_src:
- c_src = ('\n\t_srcRegIdx[_numSrcRegs++] = RegId(%s, %s, %s);' %
+ c_src = ('\n\tsetSrcRegIdx(_numSrcRegs++, RegId(%s, %s, %s));' %
(self.reg_class, self.reg_spec, self.elem_spec))
if self.is_dest:
- c_dest = ('\n\t_destRegIdx[_numDestRegs++] = RegId(%s, %s, %s);' %
+ c_dest = ('\n\tsetDestRegIdx(_numDestRegs++, RegId(%s, %s, %s));' %
(self.reg_class, self.reg_spec, self.elem_spec))
c_dest += '\n\t_numVecElemDestRegs++;'
return c_src + c_dest
// class?
if (strcmp(mnemonic, "syscall") != 0) {
if(_numDestRegs > 0){
- printReg(ss, _destRegIdx[0]);
+ printReg(ss, destRegIdx(0));
}
if(_numSrcRegs > 0) {
ss << ", ";
- printReg(ss, _srcRegIdx[0]);
+ printReg(ss, srcRegIdx(0));
}
if(_numSrcRegs > 1) {
ss << ", ";
- printReg(ss, _srcRegIdx[1]);
+ printReg(ss, srcRegIdx(1));
}
}
// branches) or a destination (the link reg for
// unconditional branches)
if (_numSrcRegs == 1) {
- printReg(ss, _srcRegIdx[0]);
+ printReg(ss, srcRegIdx(0));
ss << ", ";
} else if(_numSrcRegs == 2) {
- printReg(ss, _srcRegIdx[0]);
+ printReg(ss, srcRegIdx(0));
ss << ", ";
- printReg(ss, _srcRegIdx[1]);
+ printReg(ss, srcRegIdx(1));
ss << ", ";
}
else
ccprintf(ss, "0x%x", disp);
} else if (_numSrcRegs == 1) {
- printReg(ss, _srcRegIdx[0]);
+ printReg(ss, srcRegIdx(0));
} else if(_numSrcRegs == 2) {
- printReg(ss, _srcRegIdx[0]);
+ printReg(ss, srcRegIdx(0));
ss << ", ";
- printReg(ss, _srcRegIdx[1]);
+ printReg(ss, srcRegIdx(1));
}
return ss.str();
if (_numSrcRegs > 0) {
ss << ", ";
- printReg(ss, _srcRegIdx[0]);
+ printReg(ss, srcRegIdx(0));
}
if (_numSrcRegs > 1) {
ss << ", ";
- printReg(ss, _srcRegIdx[1]);
+ printReg(ss, srcRegIdx(1));
}
return ss.str();
// just print the first dest... if there's a second one,
// it's generally implicit
if (_numDestRegs > 0) {
- printReg(ss, _destRegIdx[0]);
+ printReg(ss, destRegIdx(0));
ss << ", ";
}
// a third one, it's a read-modify-write dest (Rc),
// e.g. for CMOVxx
if (_numSrcRegs > 0) {
- printReg(ss, _srcRegIdx[0]);
+ printReg(ss, srcRegIdx(0));
}
if (_numSrcRegs > 1) {
ss << ", ";
- printReg(ss, _srcRegIdx[1]);
+ printReg(ss, srcRegIdx(1));
}
return ss.str();
// Destination Registers are implicit for HI/LO ops
if (_numSrcRegs > 0) {
- printReg(ss, _srcRegIdx[0]);
+ printReg(ss, srcRegIdx(0));
}
if (_numSrcRegs > 1) {
ss << ", ";
- printReg(ss, _srcRegIdx[1]);
+ printReg(ss, srcRegIdx(1));
}
return ss.str();
ccprintf(ss, "%-10s ", mnemonic);
- if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
- printReg(ss, _destRegIdx[0]);
- } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
- printReg(ss, _srcRegIdx[0]);
+ if (_numDestRegs > 0 && destRegIdx(0).index() < 32) {
+ printReg(ss, destRegIdx(0));
+ } else if (_numSrcRegs > 0 && srcRegIdx(0).index() < 32) {
+ printReg(ss, srcRegIdx(0));
}
return ss.str();
ccprintf(ss, "%-10s ", mnemonic);
- if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
- printReg(ss, _destRegIdx[0]);
- } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
- printReg(ss, _srcRegIdx[0]);
+ if (_numDestRegs > 0 && destRegIdx(0).index() < 32) {
+ printReg(ss, destRegIdx(0));
+ } else if (_numSrcRegs > 0 && srcRegIdx(0).index() < 32) {
+ printReg(ss, srcRegIdx(0));
}
return ss.str();
ccprintf(ss, "%-10s ", mnemonic);
- if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) {
- printReg(ss, _destRegIdx[0]);
- } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) {
- printReg(ss, _srcRegIdx[0]);
+ if (_numDestRegs > 0 && destRegIdx(0).index() < 32) {
+ printReg(ss, destRegIdx(0));
+ } else if (_numSrcRegs > 0 && srcRegIdx(0).index() < 32) {
+ printReg(ss, srcRegIdx(0));
}
return ss.str();
ccprintf(ss, "%-10s ", mnemonic);
if (_numDestRegs > 0) {
- printReg(ss, _destRegIdx[0]);
+ printReg(ss, destRegIdx(0));
}
ss << ", ";
if (_numSrcRegs > 0) {
- printReg(ss, _srcRegIdx[0]);
+ printReg(ss, srcRegIdx(0));
ss << ", ";
}
PowerISA::PCState
BranchRegCond::branchTarget(ThreadContext *tc) const
{
- uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1].index());
+ uint32_t regVal = tc->readIntReg(srcRegIdx(_numSrcRegs - 1).index());
return regVal & 0xfffffffc;
}
// Print the first destination only
if (_numDestRegs > 0) {
- printReg(ss, _destRegIdx[0]);
+ printReg(ss, destRegIdx(0));
}
// Print the (possibly) two source registers
if (_numDestRegs > 0) {
ss << ", ";
}
- printReg(ss, _srcRegIdx[0]);
+ printReg(ss, srcRegIdx(0));
if (_numSrcRegs > 1) {
ss << ", ";
- printReg(ss, _srcRegIdx[1]);
+ printReg(ss, srcRegIdx(1));
}
}
string myMnemonic(mnemonic);
// Special cases
- if (!myMnemonic.compare("or") && _srcRegIdx[0] == _srcRegIdx[1]) {
+ if (!myMnemonic.compare("or") && srcRegIdx(0) == srcRegIdx(1)) {
myMnemonic = "mr";
printSecondSrc = false;
} else if (!myMnemonic.compare("mtlr") || !myMnemonic.compare("cmpi")) {
// Print the first destination only
if (_numDestRegs > 0 && printDest) {
- printReg(ss, _destRegIdx[0]);
+ printReg(ss, destRegIdx(0));
}
// Print the (possibly) two source registers
if (_numDestRegs > 0 && printDest) {
ss << ", ";
}
- printReg(ss, _srcRegIdx[0]);
+ printReg(ss, srcRegIdx(0));
if (_numSrcRegs > 1 && printSecondSrc) {
ss << ", ";
- printReg(ss, _srcRegIdx[1]);
+ printReg(ss, srcRegIdx(1));
}
}
// Print the first destination only
if (_numDestRegs > 0) {
- printReg(ss, _destRegIdx[0]);
+ printReg(ss, destRegIdx(0));
}
// Print the source register
if (_numDestRegs > 0) {
ss << ", ";
}
- printReg(ss, _srcRegIdx[0]);
+ printReg(ss, srcRegIdx(0));
}
// Print the immediate value last
// Print the first destination only
if (_numDestRegs > 0) {
- printReg(ss, _destRegIdx[0]);
+ printReg(ss, destRegIdx(0));
}
// Print the first source register
if (_numDestRegs > 0) {
ss << ", ";
}
- printReg(ss, _srcRegIdx[0]);
+ printReg(ss, srcRegIdx(0));
}
// Print the shift
// Print the first destination only
if (_numDestRegs > 0) {
- printReg(ss, _destRegIdx[0]);
+ printReg(ss, destRegIdx(0));
}
// Print the first source register
if (_numDestRegs > 0) {
ss << ", ";
}
- printReg(ss, _srcRegIdx[0]);
+ printReg(ss, srcRegIdx(0));
}
// Print the shift, mask begin and mask end
// If the instruction updates the source register with the
// EA, then this source register is placed in position 0,
// therefore we print the last destination register.
- printReg(ss, _destRegIdx[_numDestRegs-1]);
+ printReg(ss, destRegIdx(_numDestRegs-1));
}
}
// Print the data register for a store
else {
- printReg(ss, _srcRegIdx[1]);
+ printReg(ss, srcRegIdx(1));
}
// Print the displacement
// Print the address register
ss << "(";
- printReg(ss, _srcRegIdx[0]);
+ printReg(ss, srcRegIdx(0));
ss << ")";
return ss.str();
// Print the first destination only
if (_numDestRegs > 0) {
- printReg(ss, _destRegIdx[0]);
+ printReg(ss, destRegIdx(0));
}
// Print the (possibly) two source registers
if (_numDestRegs > 0) {
ss << ", ";
}
- printReg(ss, _srcRegIdx[0]);
+ printReg(ss, srcRegIdx(0));
if (_numSrcRegs > 1) {
ss << ", ";
- printReg(ss, _srcRegIdx[1]);
+ printReg(ss, srcRegIdx(1));
}
}
Addr pc, const Loader::SymbolTable *symtab) const
{
stringstream ss;
- ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ("
- << registerName(_srcRegIdx[0]) << ')';
+ ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", ("
+ << registerName(srcRegIdx(0)) << ')';
return ss.str();
}
Addr pc, const Loader::SymbolTable *symtab) const
{
stringstream ss;
- ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
- << registerName(_srcRegIdx[1]) << ", ("
- << registerName(_srcRegIdx[0]) << ')';
+ ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "
+ << registerName(srcRegIdx(1)) << ", ("
+ << registerName(srcRegIdx(0)) << ')';
return ss.str();
}
Addr pc, const Loader::SymbolTable *symtab) const
{
stringstream ss;
- ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
- << registerName(_srcRegIdx[1]) << ", ("
- << registerName(_srcRegIdx[0]) << ')';
+ ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "
+ << registerName(srcRegIdx(1)) << ", ("
+ << registerName(srcRegIdx(0)) << ')';
return ss.str();
}
Addr pc, const Loader::SymbolTable *symtab) const
{
std::stringstream ss;
- ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
- registerName(_srcRegIdx[0]);
+ ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
+ registerName(srcRegIdx(0));
return ss.str();
}
Load::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
{
stringstream ss;
- ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
- offset << '(' << registerName(_srcRegIdx[0]) << ')';
+ ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
+ offset << '(' << registerName(srcRegIdx(0)) << ')';
return ss.str();
}
Store::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
{
stringstream ss;
- ss << mnemonic << ' ' << registerName(_srcRegIdx[1]) << ", " <<
- offset << '(' << registerName(_srcRegIdx[0]) << ')';
+ ss << mnemonic << ' ' << registerName(srcRegIdx(1)) << ", " <<
+ offset << '(' << registerName(srcRegIdx(0)) << ')';
return ss.str();
}
RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
{
stringstream ss;
- ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
- registerName(_srcRegIdx[0]);
+ ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
+ registerName(srcRegIdx(0));
if (_numSrcRegs >= 2)
- ss << ", " << registerName(_srcRegIdx[1]);
+ ss << ", " << registerName(srcRegIdx(1));
if (_numSrcRegs >= 3)
- ss << ", " << registerName(_srcRegIdx[2]);
+ ss << ", " << registerName(srcRegIdx(2));
return ss.str();
}
CSROp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
{
stringstream ss;
- ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
+ ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", ";
auto data = CSRData.find(csr);
if (data != CSRData.end())
ss << data->second.name;
else
ss << "?? (" << hex << "0x" << csr << dec << ")";
if (_numSrcRegs > 0)
- ss << ", " << registerName(_srcRegIdx[0]);
+ ss << ", " << registerName(srcRegIdx(0));
else
ss << uimm;
return ss.str();
{
if (strcmp(mnemonic, "fence_vma") == 0) {
stringstream ss;
- ss << mnemonic << ' ' << registerName(_srcRegIdx[0]) << ", " <<
- registerName(_srcRegIdx[1]);
+ ss << mnemonic << ' ' << registerName(srcRegIdx(0)) << ", " <<
+ registerName(srcRegIdx(1));
return ss.str();
}
}};
def format CIAddi4spnOp(imm_code, code, imm_type='int64_t', *opt_flags) {{
- regs = ['_destRegIdx[0]', '_srcRegIdx[0]']
+ regs = ['destRegIdx(0)', 'srcRegIdx(0)']
iop = InstObjParams(name, Name, 'ImmOp<%s>' % imm_type,
{'code': code, 'imm_code': imm_code,
'regs': ','.join(regs)}, opt_flags)
def format CIOp(imm_code, code, imm_type='int64_t', *opt_flags) {{
iop = InstObjParams(name, Name, 'ImmOp<%s>' % imm_type,
{'code': code, 'imm_code': imm_code,
- 'regs': '_destRegIdx[0]'}, opt_flags)
+ 'regs': 'destRegIdx(0)'}, opt_flags)
header_output = ImmDeclare.subst(iop)
decoder_output = ImmConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
if (CIMM3<2:2> > 0)
imm |= ~((int64_t)0xFF);
"""
- regs = '_srcRegIdx[0]'
+ regs = 'srcRegIdx(0)'
iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
{'code': code, 'imm_code': imm_code,
- 'regs': '_srcRegIdx[0]'}, opt_flags)
+ 'regs': 'srcRegIdx(0)'}, opt_flags)
header_output = BranchDeclare.subst(iop)
decoder_output = ImmConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
}};
def format CompressedROp(code, *opt_flags) {{
- regs = ['_destRegIdx[0]','_srcRegIdx[1]']
+ regs = ['destRegIdx(0)','srcRegIdx(1)']
iop = InstObjParams(name, Name, 'RegOp',
{'code': code, 'regs': ','.join(regs)}, opt_flags)
header_output = CBasicDeclare.subst(iop)
%(class_name)s::branchTarget(ThreadContext *tc) const
{
PCState pc = tc->pcState();
- pc.set((tc->readIntReg(_srcRegIdx[0].index()) + imm)&~0x1);
+ pc.set((tc->readIntReg(srcRegIdx(0).index()) + imm)&~0x1);
return pc;
}
std::stringstream ss;
ss << mnemonic << ' ';
if (QUADRANT == 0x3)
- ss << registerName(_destRegIdx[0]) << ", "
- << imm << "(" << registerName(_srcRegIdx[0]) << ")";
+ ss << registerName(destRegIdx(0)) << ", "
+ << imm << "(" << registerName(srcRegIdx(0)) << ")";
else
- ss << registerName(_srcRegIdx[0]);
+ ss << registerName(srcRegIdx(0));
return ss.str();
}
}};
def format IOp(code, imm_type='int64_t', imm_code='imm = sext<12>(IMM12);',
*opt_flags) {{
- regs = ['_destRegIdx[0]','_srcRegIdx[0]']
+ regs = ['destRegIdx(0)','srcRegIdx(0)']
iop = InstObjParams(name, Name, 'ImmOp<%s>' % imm_type,
{'imm_code': imm_code, 'code': code,
'regs': ','.join(regs)}, opt_flags)
}};
def format FenceOp(code, imm_type='int64_t', *opt_flags) {{
- regs = ['_destRegIdx[0]','_srcRegIdx[0]']
+ regs = ['destRegIdx(0)','srcRegIdx(0)']
iop = InstObjParams(name, Name, 'ImmOp<%s>' % imm_type,
{'code': code, 'imm_code': 'imm = sext<12>(IMM12);',
'regs': ','.join(regs)}, opt_flags)
IMMSIGN << 12;
imm = sext<13>(imm);
"""
- regs = ['_srcRegIdx[0]','_srcRegIdx[1]']
+ regs = ['srcRegIdx(0)','srcRegIdx(1)']
iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
{'code': code, 'imm_code': imm_code,
'regs': ','.join(regs)}, opt_flags)
}};
def format Jump(code, *opt_flags) {{
- regs = ['_srcRegIdx[0]']
+ regs = ['srcRegIdx(0)']
iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
{'code': code, 'imm_code': 'imm = sext<12>(IMM12);',
'regs': ','.join(regs)}, opt_flags)
}};
def format UOp(code, *opt_flags) {{
- regs = ['_destRegIdx[0]']
+ regs = ['destRegIdx(0)']
iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
{'code': code, 'imm_code': 'imm = IMM20;',
'regs': ','.join(regs)}, opt_flags)
imm = sext<21>(imm);
"""
pc = 'pc.set(pc.pc() + imm);'
- regs = ['_destRegIdx[0]']
+ regs = ['destRegIdx(0)']
iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
{'code': code, 'imm_code': imm_code,
'regs': ','.join(regs)}, opt_flags)
printMnemonic(response, mnemonic);
if (save) {
- printReg(response, _srcRegIdx[0]);
+ printReg(response, srcRegIdx(0));
ccprintf(response, ", ");
}
ccprintf(response, "[ ");
- printReg(response, _srcRegIdx[!save ? 0 : 1]);
+ printReg(response, srcRegIdx(!save ? 0 : 1));
ccprintf(response, " + ");
- printReg(response, _srcRegIdx[!save ? 1 : 2]);
+ printReg(response, srcRegIdx(!save ? 1 : 2));
ccprintf(response, " ]");
if (load) {
ccprintf(response, ", ");
- printReg(response, _destRegIdx[0]);
+ printReg(response, destRegIdx(0));
}
return response.str();
printMnemonic(response, mnemonic);
if (save) {
- printReg(response, _srcRegIdx[1]);
+ printReg(response, srcRegIdx(1));
ccprintf(response, ", ");
}
ccprintf(response, "[ ");
- printReg(response, _srcRegIdx[0]);
+ printReg(response, srcRegIdx(0));
if (imm >= 0)
ccprintf(response, " + 0x%x ]", imm);
else
ccprintf(response, " + -0x%x ]", -imm);
if (load) {
ccprintf(response, ", ");
- printReg(response, _destRegIdx[0]);
+ printReg(response, destRegIdx(0));
}
return response.str();
std::stringstream response;
printMnemonic(response, mnemonic);
- printRegArray(response, _srcRegIdx, _numSrcRegs);
+ printRegArray(response, &srcRegIdx(0), _numSrcRegs);
if (_numDestRegs && _numSrcRegs)
response << ", ";
printDestReg(response, 0);
std::stringstream response;
printMnemonic(response, mnemonic);
- printRegArray(response, _srcRegIdx, _numSrcRegs);
+ printRegArray(response, &srcRegIdx(0), _numSrcRegs);
if (_numSrcRegs > 0)
response << ", ";
ccprintf(response, "0x%x", imm);
IntOp::printPseudoOps(std::ostream &os, Addr pc,
const Loader::SymbolTable *symbab) const
{
- if (!std::strcmp(mnemonic, "or") && _srcRegIdx[0].index() == 0) {
+ if (!std::strcmp(mnemonic, "or") && srcRegIdx(0).index() == 0) {
printMnemonic(os, "mov");
printSrcReg(os, 1);
ccprintf(os, ", ");
const Loader::SymbolTable *symbab) const
{
if (!std::strcmp(mnemonic, "or")) {
- if (_numSrcRegs > 0 && _srcRegIdx[0].index() == 0) {
+ if (_numSrcRegs > 0 && srcRegIdx(0).index() == 0) {
if (imm == 0) {
printMnemonic(os, "clr");
} else {
if (printPseudoOps(response, pc, symtab))
return response.str();
printMnemonic(response, mnemonic);
- printRegArray(response, _srcRegIdx, _numSrcRegs);
+ printRegArray(response, &srcRegIdx(0), _numSrcRegs);
if (_numDestRegs && _numSrcRegs)
response << ", ";
printDestReg(response, 0);
if (printPseudoOps(response, pc, symtab))
return response.str();
printMnemonic(response, mnemonic);
- printRegArray(response, _srcRegIdx, _numSrcRegs);
+ printRegArray(response, &srcRegIdx(0), _numSrcRegs);
if (_numSrcRegs > 0)
response << ", ";
ccprintf(response, "%#x", imm);
printMnemonic(response, mnemonic);
if (store) {
- printReg(response, _srcRegIdx[0]);
+ printReg(response, srcRegIdx(0));
ccprintf(response, ", ");
}
ccprintf(response, "[");
- if (_srcRegIdx[!store ? 0 : 1].index() != 0) {
+ if (srcRegIdx(!store ? 0 : 1).index() != 0) {
printSrcReg(response, !store ? 0 : 1);
ccprintf(response, " + ");
}
ccprintf(response, "]");
if (load) {
ccprintf(response, ", ");
- printReg(response, _destRegIdx[0]);
+ printReg(response, destRegIdx(0));
}
return response.str();
printMnemonic(response, mnemonic);
if (save) {
- printReg(response, _srcRegIdx[0]);
+ printReg(response, srcRegIdx(0));
ccprintf(response, ", ");
}
ccprintf(response, "[");
- if (_srcRegIdx[!save ? 0 : 1].index() != 0) {
- printReg(response, _srcRegIdx[!save ? 0 : 1]);
+ if (srcRegIdx(!save ? 0 : 1).index() != 0) {
+ printReg(response, srcRegIdx(!save ? 0 : 1));
ccprintf(response, " + ");
}
if (imm >= 0)
ccprintf(response, "-%#x]", -imm);
if (load) {
ccprintf(response, ", ");
- printReg(response, _destRegIdx[0]);
+ printReg(response, destRegIdx(0));
}
return response.str();
ccprintf(response, " ");
// If the first reg is %g0, don't print it.
// This improves readability
- if (_srcRegIdx[0].index() != 0) {
+ if (srcRegIdx(0).index() != 0) {
printSrcReg(response, 0);
ccprintf(response, ", ");
}
ccprintf(response, " ");
// If the first reg is %g0, don't print it.
// This improves readability
- if (_srcRegIdx[0].index() != 0) {
+ if (srcRegIdx(0).index() != 0) {
printSrcReg(response, 0);
ccprintf(response, ", ");
}
}
void
-SparcStaticInst::printRegArray(std::ostream &os, const RegId indexArray[],
+SparcStaticInst::printRegArray(std::ostream &os, const RegId *indexArray,
int num) const
{
if (num <= 0)
SparcStaticInst::printSrcReg(std::ostream &os, int reg) const
{
if (_numSrcRegs > reg)
- printReg(os, _srcRegIdx[reg]);
+ printReg(os, srcRegIdx(reg));
}
void
SparcStaticInst::printDestReg(std::ostream &os, int reg) const
{
if (_numDestRegs > reg)
- printReg(os, _destRegIdx[reg]);
+ printReg(os, destRegIdx(reg));
}
void
// a third one, it's a read-modify-write dest (Rc),
// e.g. for CMOVxx
if (_numSrcRegs > 0)
- printReg(ss, _srcRegIdx[0]);
+ printReg(ss, srcRegIdx(0));
if (_numSrcRegs > 1) {
ss << ",";
- printReg(ss, _srcRegIdx[1]);
+ printReg(ss, srcRegIdx(1));
}
// just print the first dest... if there's a second one,
if (_numDestRegs > 0) {
if (_numSrcRegs > 0)
ss << ",";
- printReg(ss, _destRegIdx[0]);
+ printReg(ss, destRegIdx(0));
}
return ss.str();
void printDestReg(std::ostream &os, int reg) const;
void printRegArray(std::ostream &os,
- const RegId indexArray[], int num) const;
+ const RegId *indexArray, int num) const;
void advancePC(PCState &pcState) const override;
printMnemonic(response, mnemonic);
ccprintf(response, " ");
- printReg(response, _srcRegIdx[0]);
+ printReg(response, srcRegIdx(0));
ccprintf(response, ", 0x%x", trapNum);
ccprintf(response, ", or ");
- printReg(response, _srcRegIdx[1]);
+ printReg(response, srcRegIdx(1));
return response.str();
}
X86StaticInst::printSrcReg(std::ostream &os, int reg, int size) const
{
if (_numSrcRegs > reg)
- printReg(os, _srcRegIdx[reg], size);
+ printReg(os, srcRegIdx(reg), size);
}
void
X86StaticInst::printDestReg(std::ostream &os, int reg, int size) const
{
if (_numDestRegs > reg)
- printReg(os, _destRegIdx[reg], size);
+ printReg(os, destRegIdx(reg), size);
}
void
inline uint64_t merge(uint64_t into, uint64_t val, int size) const
{
X86IntReg reg = into;
- if (_destRegIdx[0].index() & IntFoldBit)
+ if (destRegIdx(0).index() & IntFoldBit)
{
reg.H = val;
return reg;
{
X86IntReg reg = from;
DPRINTF(X86, "Picking with size %d\n", size);
- if (_srcRegIdx[idx].index() & IntFoldBit)
+ if (srcRegIdx(idx).index() & IntFoldBit)
return reg.H;
switch(size)
{
{
X86IntReg reg = from;
DPRINTF(X86, "Picking with size %d\n", size);
- if (_srcRegIdx[idx].index() & IntFoldBit)
+ if (srcRegIdx(idx).index() & IntFoldBit)
return reg.SH;
switch(size)
{
printMnemonic(response, mnemonic);
ccprintf(response, " ");
- printReg(response, _srcRegIdx[0], machInst.opSize);
+ printReg(response, srcRegIdx(0), machInst.opSize);
return response.str();
}
}};
printMnemonic(response, mnemonic);
ccprintf(response, " ");
- printReg(response, _srcRegIdx[0], machInst.opSize);
+ printReg(response, srcRegIdx(0), machInst.opSize);
return response.str();
}
}};
{
std::stringstream response;
- // Although mwait could take hints from eax and ecx, the _srcRegIdx
+ // Although mwait could take hints from eax and ecx, the srcRegIdx
// is not set, and thus should not be printed here
printMnemonic(response, mnemonic);
return response.str();
printMnemonic(response, mnemonic);
ccprintf(response, " ");
- printReg(response, _srcRegIdx[0], machInst.opSize);
+ printReg(response, srcRegIdx(0), machInst.opSize);
return response.str();
}
}};
MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
};
+ private:
+ /// See destRegIdx().
+ RegId _destRegIdx[MaxInstDestRegs];
+ /// See srcRegIdx().
+ RegId _srcRegIdx[MaxInstSrcRegs];
+
protected:
/// Flag values for this instruction.
/// Only the entries from 0 through numDestRegs()-1 are valid.
const RegId& destRegIdx(int i) const { return _destRegIdx[i]; }
+ void setDestRegIdx(int i, const RegId &val) { _destRegIdx[i] = val; }
+
/// Return logical index (architectural reg num) of i'th source reg.
/// Only the entries from 0 through numSrcRegs()-1 are valid.
const RegId& srcRegIdx(int i) const { return _srcRegIdx[i]; }
+ void setSrcRegIdx(int i, const RegId &val) { _srcRegIdx[i] = val; }
+
/// Pointer to a statically allocated "null" instruction object.
static StaticInstPtr nullStaticInstPtr;
protected:
- /// See destRegIdx().
- RegId _destRegIdx[MaxInstDestRegs];
- /// See srcRegIdx().
- RegId _srcRegIdx[MaxInstSrcRegs];
-
/**
* Base mnemonic (e.g., "add"). Used by generateDisassembly()
* methods. Also useful to readily identify instructions from
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