More Modest Changes for FP MIPS execution...

arch/mips/isa/decoder.isa:
    Fix Reg. Operands for FP Conversion Instructions - Must Make Sure That You use 'uw' or 'ud' as needed.
arch/mips/isa_traits.cc:
    if a conversion function isnt implemented yet, than have M5 panic...
    (plan to implement SINGLE_TO_DOUBLE first)

--HG--
extra : convert_revision : 6a7f703a5d65139d3981a8753c31fc8f5bf313cf

diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index 6feaec7cbe1d118794b108a745825b9cf86cce80..99ff4d737f749bdff4084156c76fa3c31136bd00 100644 (file)
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -572,7 +572,7 @@ decode OPCODE_HI default Unknown::unknown() {
                             format FloatOp {
                                 0x1: cvt_d_s({{
                                     int rnd_mode = xc->readMiscReg(FCSR) & 0x03;
-                                    Fd.uw = convert_and_round(Fs.ud, SINGLE_TO_DOUBLE, rnd_mode);
+                                    Fd.ud = convert_and_round(Fs.uw, SINGLE_TO_DOUBLE, rnd_mode);
                                 }});
 
                                 0x4: cvt_w_s({{
@@ -585,7 +585,7 @@ decode OPCODE_HI default Unknown::unknown() {
                             format Float64Op {
                                 0x5: cvt_l_s({{
                                     int rnd_mode = xc->readMiscReg(FCSR) & 0x03;
-                                    Fd.uw = convert_and_round(Fs.ud, SINGLE_TO_LONG, rnd_mode);
+                                    Fd.ud = convert_and_round(Fs.uw, SINGLE_TO_LONG, rnd_mode);
                                 }});
 
                                 0x6: cvt_ps_st({{
@@ -613,37 +613,37 @@ decode OPCODE_HI default Unknown::unknown() {
                         0x1: decode FUNCTION_LO {
                             format Float64Op {
                                 0x0: round_l_d({{
-                                    Fd = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_NEAREST);
+                                    Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_NEAREST);
                                 }});
 
                                 0x1: trunc_l_d({{
-                                    Fd = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_ZERO);
+                                    Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_ZERO);
                                 }});
 
                                 0x2: ceil_l_d({{
-                                    Fd = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_UP);
+                                    Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_UP);
                                 }});
 
                                 0x3: floor_l_d({{
-                                    Fd = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_DOWN);
+                                    Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_DOWN);
                                 }});
                             }
 
                             format FloatOp {
                                 0x4: round_w_d({{
-                                    Fd = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_NEAREST);
+                                    Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_NEAREST);
                                 }});
 
                                 0x5: trunc_w_d({{
-                                    Fd = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_ZERO);
+                                    Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_ZERO);
                                 }});
 
                                 0x6: ceil_w_d({{
-                                    Fd = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_UP);
+                                    Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_UP);
                                 }});
 
                                 0x7: floor_w_d({{
-                                    Fd = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_DOWN);
+                                    Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_DOWN);
                                 }});
                             }
                         }
@@ -671,12 +671,12 @@ decode OPCODE_HI default Unknown::unknown() {
                             format FloatOp {
                                 0x0: cvt_s_d({{
                                     int rnd_mode = xc->readMiscReg(FCSR) & 0x03;
-                                    Fd = convert_and_round(Fs.ud, DOUBLE_TO_SINGLE, rnd_mode);
+                                    Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_SINGLE, rnd_mode);
                                 }});
 
                                 0x4: cvt_w_d({{
                                     int rnd_mode = xc->readMiscReg(FCSR) & 0x03;
-                                    Fd = convert_and_round(Fs.ud, DOUBLE_TO_WORD, rnd_mode);
+                                    Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, rnd_mode);
                                 }});
                             }
 
@@ -684,7 +684,7 @@ decode OPCODE_HI default Unknown::unknown() {
                             format Float64Op {
                                 0x5: cvt_l_d({{
                                     int rnd_mode = xc->readMiscReg(FCSR) & 0x03;
-                                    Fd = convert_and_round(Fs.ud, DOUBLE_TO_LONG, rnd_mode);
+                                    Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, rnd_mode);
                                 }});
                             }
                         }
@@ -695,12 +695,12 @@ decode OPCODE_HI default Unknown::unknown() {
                         format FloatOp {
                             0x20: cvt_s_w({{
                                 int rnd_mode = xc->readMiscReg(FCSR) & 0x03;
-                                Fd = convert_and_round(Fs.uw, WORD_TO_SINGLE, rnd_mode);
+                                Fd.uw = convert_and_round(Fs.uw, WORD_TO_SINGLE, rnd_mode);
                             }});
 
                             0x21: cvt_d_w({{
                                 int rnd_mode = xc->readMiscReg(FCSR) & 0x03;
-                                Fd = convert_and_round(Fs.uw, WORD_TO_DOUBLE, rnd_mode);
+                                Fd.ud = convert_and_round(Fs.uw, WORD_TO_DOUBLE, rnd_mode);
                             }});
                         }
                     }
@@ -712,12 +712,12 @@ decode OPCODE_HI default Unknown::unknown() {
                         format Float64Op {
                             0x10: cvt_s_l({{
                                 int rnd_mode = xc->readMiscReg(FCSR) & 0x03;
-                                Fd = convert_and_round(Fs.ud, LONG_TO_SINGLE, rnd_mode);
+                                Fd.uw = convert_and_round(Fs.ud, LONG_TO_SINGLE, rnd_mode);
                             }});
 
                             0x11: cvt_d_l({{
                                 int rnd_mode = xc->readMiscReg(FCSR) & 0x03;
-                                Fd = convert_and_round(Fs.ud, LONG_TO_DOUBLE, rnd_mode);
+                                Fd.ud = convert_and_round(Fs.ud, LONG_TO_DOUBLE, rnd_mode);
                             }});
                         }
                     }
@@ -778,7 +778,7 @@ decode OPCODE_HI default Unknown::unknown() {
                         0x4: decode FUNCTION_LO {
                             0x0: Float64Op::cvt_s_pu({{
                                 int rnd_mode = xc->readMiscReg(FCSR) & 0x03;
-                                Fd = convert_and_round(Fs.ud, PUPPER_TO_SINGLE, rnd_mode);
+                                Fd.uw = convert_and_round(Fs.ud, PUPPER_TO_SINGLE, rnd_mode);
                             }});
                         }
 
@@ -786,7 +786,7 @@ decode OPCODE_HI default Unknown::unknown() {
                             format Float64Op {
                                 0x0: cvt_s_pl({{
                                     int rnd_mode = xc->readMiscReg(FCSR) & 0x03;
-                                    Fd = convert_and_round(Fs.ud, PLOWER_TO_SINGLE,
+                                    Fd.uw = convert_and_round(Fs.ud, PLOWER_TO_SINGLE,
                                                            rnd_mode);
                                 }});
 

diff --git a/arch/mips/isa_traits.cc b/arch/mips/isa_traits.cc
index d23cdf367802eb9a505c363e6fab2809a1b9338f..648e9ac624f1f47dc810f16ccc982748eba1a0bf 100644 (file)
--- a/arch/mips/isa_traits.cc
+++ b/arch/mips/isa_traits.cc
@@ -41,26 +41,11 @@ MipsISA::convert_and_round(uint64_t fp_val, ConvertType cvt_type, int rnd_mode)
     switch (cvt_type)
     {
       case SINGLE_TO_DOUBLE:
-        break;
-
-      case SINGLE_TO_WORD:
-        break;
-
-      case SINGLE_TO_LONG:
-        break;
-
-      case DOUBLE_TO_SINGLE:
-
-        break;
-
-      case LONG_TO_SINGLE:
-        break;
 
-      case WORD_TO_SINGLE:
         break;
 
       default:
-        panic("Invalid Floating Point Conversion type being used.\n");
+        panic("Invalid Floating Point Conversion Type (%d) being used.\n",cvt_type);
     }
 
     return ret_val;