ARM: Implement the version of VMRS that writes to the APSR.

diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index 83f5415840d740a9ec0e0ac62dc09a80cd9d9356..2848763115d022a20060076726ab0420cc89d71c 100644 (file)
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -409,7 +409,17 @@ let {{
                   default:
                     return new Unknown(machInst);
                 }
-                return new Vmrs(machInst, rt, (IntRegIndex)specReg);
+                if (rt == 0xf) {
+                    CPSR cpsrMask = 0;
+                    cpsrMask.n = 1;
+                    cpsrMask.z = 1;
+                    cpsrMask.c = 1;
+                    cpsrMask.v = 1;
+                    return new VmrsApsr(machInst, INTREG_CONDCODES,
+                            (IntRegIndex)specReg, (uint32_t)cpsrMask);
+                } else {
+                    return new Vmrs(machInst, rt, (IntRegIndex)specReg);
+                }
             }
         } else {
             uint32_t vd = (bits(machInst, 7) << 5) |

diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa
index e3e345c7457f8592b46e73b60916306fcb573490..b3ad567dc0811347be8bf0e4edd123e73f37bb02 100644 (file)
--- a/src/arch/arm/isa/includes.isa
+++ b/src/arch/arm/isa/includes.isa
@@ -63,6 +63,7 @@ output header {{
 
 output decoder {{
 #include "arch/arm/faults.hh"
+#include "arch/arm/intregs.hh"
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/utility.hh"
 #include "base/cprintf.hh"

diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index 0abae6a20159741808280be1ebe0a6e0b4598a87..c5ce813f9096f533c033043a28b94968585be3bd 100644 (file)
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -205,6 +205,14 @@ let {{
     decoder_output += VfpRegRegOpConstructor.subst(vmrsIop);
     exec_output += PredOpExecute.subst(vmrsIop);
 
+    vmrsApsrCode = "Dest = (MiscOp1 & imm) | (Dest & ~imm);"
+    vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "VfpRegRegImmOp",
+                                { "code": vmrsApsrCode,
+                                  "predicate_test": predicateTest }, [])
+    header_output += VfpRegRegImmOpDeclare.subst(vmrsApsrIop);
+    decoder_output += VfpRegRegImmOpConstructor.subst(vmrsApsrIop);
+    exec_output += PredOpExecute.subst(vmrsApsrIop);
+
     vmovImmSCode = '''
         FpDest.uw = bits(imm, 31, 0);
     '''