clarification on 6600

diff --git a/3d_gpu/architecture/6600scoreboard.mdwn b/3d_gpu/architecture/6600scoreboard.mdwn
index 8ad5c6835147fc57638ffaa7461a9bed65025269..0d5e1645e4cfd7fff2bdf89fe65edb295ff6db74 100644 (file)
--- a/3d_gpu/architecture/6600scoreboard.mdwn
+++ b/3d_gpu/architecture/6600scoreboard.mdwn
@@ -75,7 +75,7 @@ ultimately then, there is:
 * an FU-FU Matrix that preserves, as a Directed Acyclic Graph (DAG),
   the instruction order.  again, this is a bit-based system (SR Latches)
   that record which *read port* of the Function Unit needs a write result
-  (when available).
+  (when available), and which write port needs a *read* result.
 * a suite of Function Units with input *and* output latches where the
   register information is *removed* (that being back in the FU-Regs row
   associated with a given FU)