arch-arm: Add set_reg_idx_arr to SveStructMemSIMicroopDeclare
authorGiacomo Travaglini <giacomo.travaglini@arm.com>
Sun, 24 Jan 2021 17:01:24 +0000 (17:01 +0000)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Mon, 25 Jan 2021 09:13:06 +0000 (09:13 +0000)
This should have been part of:

https://gem5-review.googlesource.com/c/public/gem5/+/38381

Change-Id: I1914fdcd0382fc95dcead2eafa09de12a43776ab
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39635
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/arm/isa/templates/sve_mem.isa

index 8bfb423e328f790ae1556f9298dcdc7ecf4d9750..f635870b0643548f14f5edfa4a36c53a1baadbc9 100644 (file)
@@ -911,6 +911,7 @@ def template SveStructMemSIMicroopDeclare {{
             numRegs(_numRegs), regIndex(_regIndex),
             memAccessFlags(ArmISA::TLB::AllowUnaligned)
         {
+            %(set_reg_idx_arr)s;
             %(constructor)s;
             baseIsSP = isSP(_base);
         }