return (inst & ~QPU_COND_MUL_MASK) | QPU_SET_FIELD(sig, QPU_COND_MUL);
}
+bool
+qpu_waddr_is_tlb(uint32_t waddr)
+{
+ switch (waddr) {
+ case QPU_W_TLB_COLOR_ALL:
+ case QPU_W_TLB_COLOR_MS:
+ case QPU_W_TLB_Z:
+ return true;
+ default:
+ return false;
+ }
+}
+
+bool
+qpu_inst_is_tlb(uint64_t inst)
+{
+ uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
+
+ return (qpu_waddr_is_tlb(QPU_GET_FIELD(inst, QPU_WADDR_ADD)) ||
+ qpu_waddr_is_tlb(QPU_GET_FIELD(inst, QPU_WADDR_MUL)) ||
+ sig == QPU_SIG_COLOR_LOAD ||
+ sig == QPU_SIG_WAIT_FOR_SCOREBOARD);
+}
uint64_t qpu_set_cond_add(uint64_t inst, uint32_t cond);
uint64_t qpu_set_cond_mul(uint64_t inst, uint32_t cond);
+bool qpu_waddr_is_tlb(uint32_t waddr);
+bool qpu_inst_is_tlb(uint64_t inst);
+
static inline uint64_t
qpu_load_imm_f(struct qpu_reg dst, float val)
{
void
vc4_qpu_validate(uint64_t *insts, uint32_t num_inst)
{
+ bool scoreboard_locked = false;
+
for (int i = 0; i < num_inst; i++) {
uint64_t inst = insts[i];
- if (QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_PROG_END)
+ if (QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_PROG_END) {
+ if (qpu_inst_is_tlb(inst))
+ scoreboard_locked = true;
+
continue;
+ }
/* "The Thread End instruction must not write to either physical
* regfile A or B."
assert(QPU_GET_FIELD(inst, QPU_WADDR_ADD) >= 32);
assert(QPU_GET_FIELD(inst, QPU_WADDR_MUL) >= 32);
+ /* Can't trigger an implicit wait on scoreboard in the program
+ * end instruction.
+ */
+ assert(!qpu_inst_is_tlb(inst) || scoreboard_locked);
+
/* Two delay slots will be executed. */
assert(i + 2 <= num_inst);
for (int i = 0; i < 2; i++) {
uint64_t inst = insts[i];
- assert(QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_COLOR_LOAD);
- assert(QPU_GET_FIELD(inst, QPU_SIG) !=
- QPU_SIG_WAIT_FOR_SCOREBOARD);
- assert(!writes_reg(inst, QPU_W_TLB_COLOR_MS));
- assert(!writes_reg(inst, QPU_W_TLB_COLOR_ALL));
- assert(!writes_reg(inst, QPU_W_TLB_Z));
-
+ assert(!qpu_inst_is_tlb(inst));
}
/* "If TMU_NOSWAP is written, the write must be three instructions