re PR target/66217 (PowerPC rotate/shift/mask instructions not optimal)

	PR target/66217
	PR target/67045
	* config/rs6000/rs6000.md (and<mode>3): Put a CONST_INT_P check
	around those cases that need one.

From-SVN: r226378

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f4a50610f849da8e177b7232900334e217c96053..d1a9600ae8a7f05d5e86c41b963efab12ca4bf4b 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2015-07-29  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       PR target/66217
+       PR target/67045
+       * config/rs6000/rs6000.md (and<mode>3): Put a CONST_INT_P check
+       around those cases that need one.
+
 2015-07-29  Aditya Kumar  <hiraditya@msn.com>
 
        * params.def (PARAM_GRAPHITE_MAX_NB_SCOP_PARAMS): Default to 3.

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index f7fa3996b98ebe20f9095e8754fe4b39db0dbb39..527ad985423cd141a62eb8fc0145ace7aaf340f9 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -2898,26 +2898,29 @@
       DONE;
     }
 
-  if (rs6000_is_valid_and_mask (operands[2], <MODE>mode))
+  if (CONST_INT_P (operands[2]))
     {
-      emit_insn (gen_and<mode>3_mask (operands[0], operands[1], operands[2]));
-      DONE;
-    }
+      if (rs6000_is_valid_and_mask (operands[2], <MODE>mode))
+       {
+         emit_insn (gen_and<mode>3_mask (operands[0], operands[1], operands[2]));
+         DONE;
+       }
 
-  if (logical_const_operand (operands[2], <MODE>mode)
-      && rs6000_gen_cell_microcode)
-    {
-      emit_insn (gen_and<mode>3_imm (operands[0], operands[1], operands[2]));
-      DONE;
-    }
+      if (logical_const_operand (operands[2], <MODE>mode)
+         && rs6000_gen_cell_microcode)
+       {
+         emit_insn (gen_and<mode>3_imm (operands[0], operands[1], operands[2]));
+         DONE;
+       }
 
-  if (rs6000_is_valid_2insn_and (operands[2], <MODE>mode))
-    {
-      rs6000_emit_2insn_and (<MODE>mode, operands, true, 0);
-      DONE;
-    }
+      if (rs6000_is_valid_2insn_and (operands[2], <MODE>mode))
+       {
+         rs6000_emit_2insn_and (<MODE>mode, operands, true, 0);
+         DONE;
+       }
 
-  operands[2] = force_reg (<MODE>mode, operands[2]);
+      operands[2] = force_reg (<MODE>mode, operands[2]);
+    }
 })