verilog: also set location for simple_behavioral_stmt

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 0dd4e0f61822677ea2ceb4603267834fd29265fe..a558325c3192eb92e8e17595a085656f7b82fb04 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -2113,18 +2113,22 @@ simple_behavioral_stmt:
        lvalue '=' delay expr {
                AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $4);
                ast_stack.back()->children.push_back(node);
+               SET_AST_NODE_LOC(node, @1, @4);
        } |
        lvalue TOK_INCREMENT {
                AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_ADD, $1->clone(), AstNode::mkconst_int(1, true)));
                ast_stack.back()->children.push_back(node);
+               SET_AST_NODE_LOC(node, @1, @2);
        } |
        lvalue TOK_DECREMENT {
                AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_SUB, $1->clone(), AstNode::mkconst_int(1, true)));
                ast_stack.back()->children.push_back(node);
+               SET_AST_NODE_LOC(node, @1, @2);
        } |
        lvalue OP_LE delay expr {
                AstNode *node = new AstNode(AST_ASSIGN_LE, $1, $4);
                ast_stack.back()->children.push_back(node);
+               SET_AST_NODE_LOC(node, @1, @4);
        };
 
 // this production creates the obligatory if-else shift/reduce conflict