+2016-08-11 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+
+ * config/s390/s390-builtin-types.def: Add INT128 types.
+ * config/s390/s390-builtins.def: Add INT128 variants for the add
+ sub low-level builtins dealing with TImode.
+ * config/s390/s390.c (s390_expand_builtin): Allow mode conversions
+ via subreg when expanding a builtin.
+ * config/s390/s390.md: Remove UNSPEC_VEC_ADDC_U128,
+ UNSPEC_VEC_SUB_U128, and UNSPEC_VEC_SUBC_U128 constants.
+ Fix comment.
+ * config/s390/vecintrin.h: Adjust builtin names accordingly.
+ * config/s390/vx-builtins.md ("vec_add_u128"): Remove expander.
+ ("vec_addc<mode>", "vec_addc_u128"): Merge to
+ "vacc<bhfgq>_<mode>".
+ ("vec_adde_u128"): Rename to "vacq". Change mode to TImode.
+ ("vec_addec_u128"): Rename to "vacccq". Change mode to TImode.
+ ("vec_subc<mode>", "vec_subc_u128"): Merge to
+ "vscbi<bhfgq>_<mode>".
+ ("vec_sube_u128"): Rename to "vsbiq". Change mode to TImode.
+ ("vec_subec_u128"): Rename to "vsbcbiq". Change mode to TImode.
+
2016-08-11 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/s390-builtins.def: Mark last operand of s390_vlvg*
DEF_TYPE (BT_UINT, 0, unsigned_type_node, 0)
DEF_TYPE (BT_VOIDCONST, B_VX, void_type_node, 1)
DEF_TYPE (BT_ULONG, B_VX, long_unsigned_type_node, 0)
+DEF_TYPE (BT_INT128, B_VX, intTI_type_node, 0)
DEF_TYPE (BT_USHORTCONST, B_VX, short_unsigned_type_node, 1)
DEF_TYPE (BT_SHORTCONST, B_VX, short_integer_type_node, 1)
DEF_TYPE (BT_INTCONST, B_VX, integer_type_node, 1)
DEF_FN_TYPE_1 (BT_FN_VOID_INT, B_HTM, BT_VOID, BT_INT)
DEF_FN_TYPE_1 (BT_FN_VOID_UINT, 0, BT_VOID, BT_UINT)
DEF_FN_TYPE_2 (BT_FN_DBL_V2DF_INT, B_VX, BT_DBL, BT_V2DF, BT_INT)
+DEF_FN_TYPE_2 (BT_FN_INT128_INT128_INT128, B_VX, BT_INT128, BT_INT128, BT_INT128)
DEF_FN_TYPE_2 (BT_FN_INT_OV4SI_INT, B_VX, BT_INT, BT_OV4SI, BT_INT)
DEF_FN_TYPE_2 (BT_FN_INT_OV4SI_OV4SI, B_VX, BT_INT, BT_OV4SI, BT_OV4SI)
DEF_FN_TYPE_2 (BT_FN_INT_UV16QI_UV16QI, B_VX, BT_INT, BT_UV16QI, BT_UV16QI)
DEF_FN_TYPE_2 (BT_FN_V8HI_V8HI_V8HI, B_VX, BT_V8HI, BT_V8HI, BT_V8HI)
DEF_FN_TYPE_2 (BT_FN_VOID_UINT64PTR_UINT64, B_HTM, BT_VOID, BT_UINT64PTR, BT_UINT64)
DEF_FN_TYPE_2 (BT_FN_VOID_V2DF_FLTPTR, B_VX, BT_VOID, BT_V2DF, BT_FLTPTR)
+DEF_FN_TYPE_3 (BT_FN_INT128_INT128_INT128_INT128, B_VX, BT_INT128, BT_INT128, BT_INT128, BT_INT128)
DEF_FN_TYPE_3 (BT_FN_INT_OV4SI_OV4SI_INTPTR, B_VX, BT_INT, BT_OV4SI, BT_OV4SI, BT_INTPTR)
DEF_FN_TYPE_3 (BT_FN_OV4SI_INT_OV4SI_INT, B_VX, BT_OV4SI, BT_INT, BT_OV4SI, BT_INT)
DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_INT, B_VX, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_INT)
B_DEF (s390_vupllh, vec_unpackl_lv8hi, 0, B_VX, 0, BT_FN_UV4SI_UV8HI)
B_DEF (s390_vuplf, vec_unpacklv4si, 0, B_VX, 0, BT_FN_V2DI_V4SI)
B_DEF (s390_vupllf, vec_unpackl_lv4si, 0, B_VX, 0, BT_FN_UV2DI_UV4SI)
-B_DEF (s390_vaq, vec_add_u128, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI)
OB_DEF (s390_vec_addc, s390_vec_addc_u8, s390_vec_addc_u64, B_VX, BT_FN_OV4SI_OV4SI_OV4SI)
OB_DEF_VAR (s390_vec_addc_u8, s390_vaccb, 0, BT_OV_UV16QI_UV16QI_UV16QI)
OB_DEF_VAR (s390_vec_addc_u32, s390_vaccf, 0, BT_OV_UV4SI_UV4SI_UV4SI)
OB_DEF_VAR (s390_vec_addc_u64, s390_vaccg, 0, BT_OV_UV2DI_UV2DI_UV2DI)
-B_DEF (s390_vaccb, vec_addcv16qi, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI)
-B_DEF (s390_vacch, vec_addcv8hi, 0, B_VX, 0, BT_FN_UV8HI_UV8HI_UV8HI)
-B_DEF (s390_vaccf, vec_addcv4si, 0, B_VX, 0, BT_FN_UV4SI_UV4SI_UV4SI)
-B_DEF (s390_vaccg, vec_addcv2di, 0, B_VX, 0, BT_FN_UV2DI_UV2DI_UV2DI)
-B_DEF (s390_vaccq, vec_addc_u128, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI)
-B_DEF (s390_vacq, vec_adde_u128, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI)
-B_DEF (s390_vacccq, vec_addec_u128, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI)
+B_DEF (s390_vaccb, vaccb_v16qi, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI)
+B_DEF (s390_vacch, vacch_v8hi, 0, B_VX, 0, BT_FN_UV8HI_UV8HI_UV8HI)
+B_DEF (s390_vaccf, vaccf_v4si, 0, B_VX, 0, BT_FN_UV4SI_UV4SI_UV4SI)
+B_DEF (s390_vaccg, vaccg_v2di, 0, B_VX, 0, BT_FN_UV2DI_UV2DI_UV2DI)
+
+B_DEF (s390_vec_add_u128, addti3, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI)
+B_DEF (s390_vec_addc_u128, vaccq_ti, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI)
+B_DEF (s390_vec_adde_u128, vacq, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI)
+B_DEF (s390_vec_addec_u128, vacccq, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI)
+
+B_DEF (s390_vaq, addti3, 0, B_VX, 0, BT_FN_INT128_INT128_INT128)
+B_DEF (s390_vaccq, vaccq_ti, 0, B_VX, 0, BT_FN_INT128_INT128_INT128)
+B_DEF (s390_vacq, vacq, 0, B_VX, 0, BT_FN_INT128_INT128_INT128_INT128)
+B_DEF (s390_vacccq, vacccq, 0, B_VX, 0, BT_FN_INT128_INT128_INT128_INT128)
OB_DEF (s390_vec_and, s390_vec_and_b8, s390_vec_and_dbl_c, B_VX, BT_FN_OV4SI_OV4SI_OV4SI)
OB_DEF_VAR (s390_vec_and_b8, s390_vn, 0, BT_OV_BV16QI_BV16QI_BV16QI)
OB_DEF_VAR (s390_vec_srb_dbl_s64, s390_vsrlb, 0, BT_OV_V2DF_V2DF_V2DI)
B_DEF (s390_vsrlb, vec_srbv16qi, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI)
-B_DEF (s390_vsq, vec_sub_u128, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI)
OB_DEF (s390_vec_subc, s390_vec_subc_u8, s390_vec_subc_u64, B_VX, BT_FN_OV4SI_OV4SI_OV4SI)
OB_DEF_VAR (s390_vec_subc_u8, s390_vscbib, 0, BT_OV_UV16QI_UV16QI_UV16QI)
OB_DEF_VAR (s390_vec_subc_u32, s390_vscbif, 0, BT_OV_UV4SI_UV4SI_UV4SI)
OB_DEF_VAR (s390_vec_subc_u64, s390_vscbig, 0, BT_OV_UV2DI_UV2DI_UV2DI)
-B_DEF (s390_vscbib, vec_subcv16qi, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI)
-B_DEF (s390_vscbih, vec_subcv8hi, 0, B_VX, 0, BT_FN_UV8HI_UV8HI_UV8HI)
-B_DEF (s390_vscbif, vec_subcv4si, 0, B_VX, 0, BT_FN_UV4SI_UV4SI_UV4SI)
-B_DEF (s390_vscbig, vec_subcv2di, 0, B_VX, 0, BT_FN_UV2DI_UV2DI_UV2DI)
-B_DEF (s390_vscbiq, vec_subc_u128, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI)
-B_DEF (s390_vsbiq, vec_sube_u128, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI)
-B_DEF (s390_vsbcbiq, vec_subec_u128, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI)
+B_DEF (s390_vscbib, vscbib_v16qi, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI)
+B_DEF (s390_vscbih, vscbih_v8hi, 0, B_VX, 0, BT_FN_UV8HI_UV8HI_UV8HI)
+B_DEF (s390_vscbif, vscbif_v4si, 0, B_VX, 0, BT_FN_UV4SI_UV4SI_UV4SI)
+B_DEF (s390_vscbig, vscbig_v2di, 0, B_VX, 0, BT_FN_UV2DI_UV2DI_UV2DI)
+
+/* The builtin definitions requires these to use vector unsigned char.
+ But we want the GCC low-level builtins and the insn patterns to
+ allow int128_t and TImode. So we rely on s390_expand_builtin to
+ switch modes. */
+
+B_DEF (s390_vec_sub_u128, subti3, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI)
+B_DEF (s390_vec_subc_u128, vscbiq_ti, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI)
+B_DEF (s390_vec_sube_u128, vsbiq, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI)
+B_DEF (s390_vec_subec_u128, vsbcbiq, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UV16QI_UV16QI)
+
+B_DEF (s390_vsq, subti3, 0, B_VX, 0, BT_FN_INT128_INT128_INT128)
+B_DEF (s390_vscbiq, vscbiq_ti, 0, B_VX, 0, BT_FN_INT128_INT128_INT128)
+B_DEF (s390_vsbiq, vsbiq, 0, B_VX, 0, BT_FN_INT128_INT128_INT128_INT128)
+B_DEF (s390_vsbcbiq, vsbcbiq, 0, B_VX, 0, BT_FN_INT128_INT128_INT128_INT128)
OB_DEF (s390_vec_sum2, s390_vec_sum2_u16, s390_vec_sum2_u32, B_VX, BT_FN_OV4SI_OV4SI_OV4SI)
OB_DEF_VAR (s390_vec_sum2_u16, s390_vsumgh, 0, BT_OV_UV2DI_UV8HI_UV8HI)
arity = 0;
FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
{
+ rtx tmp_rtx;
const struct insn_operand_data *insn_op;
unsigned int op_flags = all_op_flags & ((1 << O_SHIFT) - 1);
copy_to_mode_reg (Pmode,
XEXP (op[arity], 0)));
}
+ /* Some of the builtins require different modes/types than the
+ pattern in order to implement a specific API. Instead of
+ adding many expanders which do the mode change we do it here.
+ E.g. s390_vec_add_u128 required to have vector unsigned char
+ arguments is mapped to addti3. */
+ else if (insn_op->mode != VOIDmode
+ && GET_MODE (op[arity]) != VOIDmode
+ && GET_MODE (op[arity]) != insn_op->mode
+ && ((tmp_rtx = simplify_gen_subreg (insn_op->mode, op[arity],
+ GET_MODE (op[arity]), 0))
+ != NULL_RTX))
+ {
+ op[arity] = tmp_rtx;
+ }
else if (GET_MODE (op[arity]) == insn_op->mode
|| GET_MODE (op[arity]) == VOIDmode
|| (insn_op->predicate == address_operand
UNSPEC_VEC_UNPACKL
UNSPEC_VEC_UNPACKL_L
UNSPEC_VEC_ADDC
- UNSPEC_VEC_ADDC_U128
UNSPEC_VEC_ADDE_U128
UNSPEC_VEC_ADDEC_U128
UNSPEC_VEC_AVG
UNSPEC_VEC_SRL
UNSPEC_VEC_SRLB
- UNSPEC_VEC_SUB_U128
UNSPEC_VEC_SUBC
- UNSPEC_VEC_SUBC_U128
UNSPEC_VEC_SUBE_U128
UNSPEC_VEC_SUBEC_U128
(clobber (reg:CC CC_REGNUM))])]
"TARGET_ZARCH"
{
- /* For z13 we have vaq which doesn't set CC. */
+ /* For z13 we have vsq which doesn't set CC. */
if (TARGET_VX)
{
emit_insn (gen_rtx_SET (operands[0],
#define vec_splat_s32 __builtin_s390_vec_splat_s32
#define vec_splat_u64 __builtin_s390_vec_splat_u64
#define vec_splat_s64 __builtin_s390_vec_splat_s64
-#define vec_add_u128 __builtin_s390_vaq
-#define vec_addc_u128 __builtin_s390_vaccq
-#define vec_adde_u128 __builtin_s390_vacq
-#define vec_addec_u128 __builtin_s390_vacccq
#define vec_checksum __builtin_s390_vcksm
#define vec_gfmsum_128 __builtin_s390_vgfmg
#define vec_gfmsum_accum_128 __builtin_s390_vgfmag
-#define vec_sub_u128 __builtin_s390_vsq
-#define vec_subc_u128 __builtin_s390_vscbiq
-#define vec_sube_u128 __builtin_s390_vsbiq
-#define vec_subec_u128 __builtin_s390_vsbcbiq
#define vec_ceil(X) __builtin_s390_vfidb((X), 4, 6)
#define vec_roundp(X) __builtin_s390_vfidb((X), 4, 6)
#define vec_floor(X) __builtin_s390_vfidb((X), 4, 7)
#define vec_unpackh __builtin_s390_vec_unpackh
#define vec_unpackl __builtin_s390_vec_unpackl
#define vec_addc __builtin_s390_vec_addc
+#define vec_add_u128 __builtin_s390_vec_add_u128
+#define vec_addc_u128 __builtin_s390_vec_addc_u128
+#define vec_adde_u128 __builtin_s390_vec_adde_u128
+#define vec_addec_u128 __builtin_s390_vec_addec_u128
#define vec_and __builtin_s390_vec_and
#define vec_andc __builtin_s390_vec_andc
#define vec_avg __builtin_s390_vec_avg
#define vec_srl __builtin_s390_vec_srl
#define vec_srb __builtin_s390_vec_srb
#define vec_subc __builtin_s390_vec_subc
+#define vec_sub_u128 __builtin_s390_vec_sub_u128
+#define vec_subc_u128 __builtin_s390_vec_subc_u128
+#define vec_sube_u128 __builtin_s390_vec_sube_u128
+#define vec_subec_u128 __builtin_s390_vec_subec_u128
#define vec_sum2 __builtin_s390_vec_sum2
#define vec_sum_u128 __builtin_s390_vec_sum_u128
#define vec_sum4 __builtin_s390_vec_sum4
; Vector add
-; vaq
-
-; zvector builtins uses V16QI operands. So replace the modes in order
-; to map this to a TImode add. We have to keep the V16QI mode
-; operands in the expander in order to allow some operand type
-; checking when expanding the builtin.
-(define_expand "vec_add_u128"
- [(match_operand:V16QI 0 "register_operand" "")
- (match_operand:V16QI 1 "register_operand" "")
- (match_operand:V16QI 2 "register_operand" "")]
- "TARGET_VX"
-{
- rtx op0 = gen_rtx_SUBREG (TImode, operands[0], 0);
- rtx op1 = gen_rtx_SUBREG (TImode, operands[1], 0);
- rtx op2 = gen_rtx_SUBREG (TImode, operands[2], 0);
-
- emit_insn (gen_rtx_SET (op0,
- gen_rtx_PLUS (TImode, op1, op2)));
- DONE;
-})
-
; Vector add compute carry
-(define_insn "vec_addc<mode>"
- [(set (match_operand:VI_HW 0 "register_operand" "=v")
- (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v")
- (match_operand:VI_HW 2 "register_operand" "v")]
- UNSPEC_VEC_ADDC))]
+(define_insn "vacc<bhfgq>_<mode>"
+ [(set (match_operand:VIT_HW 0 "register_operand" "=v")
+ (unspec:VIT_HW [(match_operand:VIT_HW 1 "register_operand" "%v")
+ (match_operand:VIT_HW 2 "register_operand" "v")]
+ UNSPEC_VEC_ADDC))]
"TARGET_VX"
"vacc<bhfgq>\t%v0,%v1,%v2"
[(set_attr "op_type" "VRR")])
-(define_insn "vec_addc_u128"
- [(set (match_operand:V16QI 0 "register_operand" "=v")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "%v")
- (match_operand:V16QI 2 "register_operand" "v")]
- UNSPEC_VEC_ADDC_U128))]
- "TARGET_VX"
- "vaccq\t%v0,%v1,%v2"
- [(set_attr "op_type" "VRR")])
-
-
; Vector add with carry
-(define_insn "vec_adde_u128"
- [(set (match_operand:V16QI 0 "register_operand" "=v")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "%v")
- (match_operand:V16QI 2 "register_operand" "v")
- (match_operand:V16QI 3 "register_operand" "v")]
- UNSPEC_VEC_ADDE_U128))]
+(define_insn "vacq"
+ [(set (match_operand:TI 0 "register_operand" "=v")
+ (unspec:TI [(match_operand:TI 1 "register_operand" "%v")
+ (match_operand:TI 2 "register_operand" "v")
+ (match_operand:TI 3 "register_operand" "v")]
+ UNSPEC_VEC_ADDE_U128))]
"TARGET_VX"
"vacq\t%v0,%v1,%v2,%v3"
[(set_attr "op_type" "VRR")])
; Vector add with carry compute carry
-(define_insn "vec_addec_u128"
- [(set (match_operand:V16QI 0 "register_operand" "=v")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "%v")
- (match_operand:V16QI 2 "register_operand" "v")
- (match_operand:V16QI 3 "register_operand" "v")]
- UNSPEC_VEC_ADDEC_U128))]
+(define_insn "vacccq"
+ [(set (match_operand:TI 0 "register_operand" "=v")
+ (unspec:TI [(match_operand:TI 1 "register_operand" "%v")
+ (match_operand:TI 2 "register_operand" "v")
+ (match_operand:TI 3 "register_operand" "v")]
+ UNSPEC_VEC_ADDEC_U128))]
"TARGET_VX"
"vacccq\t%v0,%v1,%v2,%v3"
[(set_attr "op_type" "VRR")])
; Vector subtract
-(define_insn "vec_sub_u128"
- [(set (match_operand:V16QI 0 "register_operand" "=v")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
- (match_operand:V16QI 2 "register_operand" "v")]
- UNSPEC_VEC_SUB_U128))]
- "TARGET_VX"
- "vsq\t%v0,%v1,%v2"
- [(set_attr "op_type" "VRR")])
-
-
; Vector subtract compute borrow indication
-(define_insn "vec_subc<mode>"
- [(set (match_operand:VI_HW 0 "register_operand" "=v")
- (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v")
- (match_operand:VI_HW 2 "register_operand" "v")]
+(define_insn "vscbi<bhfgq>_<mode>"
+ [(set (match_operand:VIT_HW 0 "register_operand" "=v")
+ (unspec:VIT_HW [(match_operand:VIT_HW 1 "register_operand" "v")
+ (match_operand:VIT_HW 2 "register_operand" "v")]
UNSPEC_VEC_SUBC))]
"TARGET_VX"
"vscbi<bhfgq>\t%v0,%v1,%v2"
[(set_attr "op_type" "VRR")])
-(define_insn "vec_subc_u128"
- [(set (match_operand:V16QI 0 "register_operand" "=v")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
- (match_operand:V16QI 2 "register_operand" "v")]
- UNSPEC_VEC_SUBC_U128))]
- "TARGET_VX"
- "vscbiq\t%v0,%v1,%v2"
- [(set_attr "op_type" "VRR")])
-
-
; Vector subtract with borrow indication
-(define_insn "vec_sube_u128"
- [(set (match_operand:V16QI 0 "register_operand" "=v")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
- (match_operand:V16QI 2 "register_operand" "v")
- (match_operand:V16QI 3 "register_operand" "v")]
+(define_insn "vsbiq"
+ [(set (match_operand:TI 0 "register_operand" "=v")
+ (unspec:TI [(match_operand:TI 1 "register_operand" "v")
+ (match_operand:TI 2 "register_operand" "v")
+ (match_operand:TI 3 "register_operand" "v")]
UNSPEC_VEC_SUBE_U128))]
"TARGET_VX"
"vsbiq\t%v0,%v1,%v2,%v3"
; Vector subtract with borrow compute and borrow indication
-(define_insn "vec_subec_u128"
- [(set (match_operand:V16QI 0 "register_operand" "=v")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
- (match_operand:V16QI 2 "register_operand" "v")
- (match_operand:V16QI 3 "register_operand" "v")]
+(define_insn "vsbcbiq"
+ [(set (match_operand:TI 0 "register_operand" "=v")
+ (unspec:TI [(match_operand:TI 1 "register_operand" "v")
+ (match_operand:TI 2 "register_operand" "v")
+ (match_operand:TI 3 "register_operand" "v")]
UNSPEC_VEC_SUBEC_U128))]
"TARGET_VX"
"vsbcbiq\t%v0,%v1,%v2,%v3"
projects / gcc.git / commitdiff