boards/plarforms: fix issues found while testing simple design on all platforms

diff --git a/litex/boards/platforms/genesys2.py b/litex/boards/platforms/genesys2.py
index e8d8fc3bb5e6468f6a61a64be9dddfb45365ee37..0a454ab86c0a74dd09b0ebc958ffc23257217036 100644 (file)
--- a/litex/boards/platforms/genesys2.py
+++ b/litex/boards/platforms/genesys2.py
@@ -102,6 +102,9 @@ _connectors = [
 ]
 
 class Platform(XilinxPlatform):
+    default_clk_name = "clk200"
+    default_clk_period = 5
+
     def __init__(self, programmer="vivado"):
         XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
         self.programmer = programmer
@@ -114,7 +117,3 @@ class Platform(XilinxPlatform):
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
-        try:
-            self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
-        except ConstraintError:
-            pass

diff --git a/litex/boards/platforms/mimasv2.py b/litex/boards/platforms/mimasv2.py
index ec4c0614414e71dd23b9d27b7e585718bb58a290..b5352a1110f5fe2309af725065bf0972500e3f94 100644 (file)
--- a/litex/boards/platforms/mimasv2.py
+++ b/litex/boards/platforms/mimasv2.py
@@ -121,7 +121,6 @@ _connectors = [
 
 
 class Platform(XilinxPlatform):
-    name = "mimasv2"
     default_clk_name = "clk100"
     default_clk_period = 10
 

diff --git a/litex/boards/platforms/sim.py b/litex/boards/platforms/sim.py
index ce1cd635f14be5a5527211a0c427679150d7e869..f0dc23c7e7a813ac6264ecd3e9f63f9f68a6f553 100644 (file)
--- a/litex/boards/platforms/sim.py
+++ b/litex/boards/platforms/sim.py
@@ -54,7 +54,6 @@ _io = [
 
 
 class Platform(SimPlatform):
-    is_sim = True
     default_clk_name = "sys_clk"
     default_clk_period = 1000  # on modern computers simulate at ~ 1MHz