arch/alpha/isa_desc:
remove the annotation junk
Move some code to AlphaPseudo where it belongs
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
remove the annotation junk
add pseudo instruction code that was previously misplaced
--HG--
extra : convert_revision :
97db8402aa34e0bdf044b138c52331fc9e714986
/* $Id$ */
#include "targetarch/alpha_memory.hh"
-#include "sim/annotation.hh"
#ifdef DEBUG
#include "sim/debug.hh"
#endif
regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
regs.npc = regs.pc + sizeof(MachInst);
-
- Annotate::Ev5Trap(this, fault);
}
old = ipr[idx];
ipr[idx] = val;
kernelStats.context(old, val);
- Annotate::Context(this);
break;
case AlphaISA::IPR_DTB_PTE:
// only write least significant five bits - interrupt level
ipr[idx] = val & 0x1f;
kernelStats.swpipl(ipr[idx]);
- Annotate::IPL(this, val & 0x1f);
break;
case AlphaISA::IPR_DTB_CM:
- Annotate::ChangeMode(this, (val & 0x18) != 0);
kernelStats.mode((val & 0x18) != 0);
case AlphaISA::IPR_ICM:
#include "cpu/full_cpu/dyn_inst.hh"
#include "cpu/simple_cpu/simple_cpu.hh"
#include "cpu/static_inst.hh"
-#include "sim/annotation.hh"
#include "sim/sim_exit.hh"
#ifdef FULL_SYSTEM
// on this PAL call (including maybe suppress it)
dopal = xc->simPalCheck(palFunc);
- Annotate::Callpal(xc->xcBase(), palFunc);
-
if (dopal) {
AlphaISA::swap_palshadow(&xc->xcBase()->regs, true);
xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC);
// M5 special opcodes use the reserved 0x01 opcode space
0x01: decode M5FUNC {
0x00: arm({{
- if (!xc->misspeculating()) {
- Annotate::ARM(xc->xcBase());
- xc->xcBase()->kernelStats.arm();
- }
+ if (!xc->misspeculating())
+ AlphaPseudo::arm(xc->xcBase());
}});
0x01: quiesce({{
if (!xc->misspeculating())
AlphaPseudo::quiesce(xc->xcBase());
}});
0x10: ivlb({{
- if (!xc->misspeculating()) {
- Annotate::BeginInterval(xc->xcBase());
- xc->xcBase()->kernelStats.ivlb();
- }
+ if (!xc->misspeculating())
+ AlphaPseudo::ivlb(xc->xcBase());
}}, No_OpClass);
0x11: ivle({{
if (!xc->misspeculating())
- Annotate::EndInterval(xc->xcBase());
+ AlphaPseudo::ivle(xc->xcBase());
}}, No_OpClass);
0x20: m5exit_old({{
if (!xc->misspeculating())
#include "arch/alpha/pseudo_inst.hh"
#include "cpu/exec_context.hh"
-#include "sim/annotation.hh"
#include "sim/param.hh"
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
bool doCheckpointInsts;
bool doQuiesce;
+ void
+ arm(ExecContext *xc)
+ {
+ xc->kernelStats.arm();
+ }
+
void
quiesce(ExecContext *xc)
{
if (!doQuiesce)
return;
- Annotate::QUIESCE(xc);
xc->suspend();
xc->kernelStats.quiesce();
}
+ void
+ ivlb(ExecContext *xc)
+ {
+ xc->kernelStats.ivlb();
+ }
+
+ void
+ ivle(ExecContext *xc)
+ {
+ }
+
void
m5exit_old(ExecContext *xc)
{
extern bool doCheckpointInsts;
extern bool doQuiesce;
+ void arm(ExecContext *xc);
void quiesce(ExecContext *xc);
+ void ivlb(ExecContext *xc);
+ void ivle(ExecContext *xc);
void m5exit(ExecContext *xc);
void m5exit_old(ExecContext *xc);
void resetstats(ExecContext *xc);
#include "cpu/static_inst.hh"
#include "mem/base_mem.hh"
#include "mem/mem_interface.hh"
-#include "sim/annotation.hh"
#include "sim/builder.hh"
#include "sim/debug.hh"
#include "sim/host.hh"
if (xc->status() == ExecContext::Suspended) {
DPRINTF(IPI,"Suspended Processor awoke\n");
xc->activate();
- Annotate::Resume(xc);
}
}
#endif // FULL_SYSTEM