Intersynth URL

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>

diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index 758a8792bbd321e5336657c9d30dd963e864dfe0..59173c4a2d4ef9ae819b6797e5e3671edca27f49 100644 (file)
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -68,7 +68,7 @@ struct IntersynthBackend : public Backend {
                log("        only write selected modules. modules must be selected entirely or\n");
                log("        not at all.\n");
                log("\n");
-               log("http://www.clifford.at/intersynth/\n");
+               log("http://bygone.clairexen.net/intersynth/\n");
                log("\n");
        }
        void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override

diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex
index a3264b4cd93415dd5a51695e18e0ad887956c322..960078cc7702cd8047a2dfb8c30c1941dc0ecc30 100644 (file)
--- a/manual/command-reference-manual.tex
+++ b/manual/command-reference-manual.tex
@@ -6999,7 +6999,7 @@ a tool for Coarse-Grain Example-Driven Interconnect Synthesis.
         only write selected modules. modules must be selected entirely or
         not at all.
 
-http://www.clifford.at/intersynth/
+http://bygone.clairexen.net/intersynth/
 \end{lstlisting}
 
 \section{write\_json -- write design to a JSON file}