mention misaligned exception;

diff --git a/3d_gpu/architecture/6600scoreboard.mdwn b/3d_gpu/architecture/6600scoreboard.mdwn
index 99ad1fef80f0a221a0a8d87f3e6ec592f1e60b59..c5a5ae8dd88f5825299085e4f092d4e5e4d6b138 100644 (file)
--- a/3d_gpu/architecture/6600scoreboard.mdwn
+++ b/3d_gpu/architecture/6600scoreboard.mdwn
@@ -359,6 +359,9 @@ Notes:
 * It does however mean that the reservation on the row has to wait for
   *both* ports (left and right) to clear out their LD/ST operation(s).
 * Addr[4] still selects whether the request is to go into left or right bank
+* When the misaligned address bits 4-11 are all 0b11111111, this is not
+  a case that can be handled, because it implies that Addr[12:48] will
+  be **different** in the row.  This case throws a misaligned exception.
 
 Other than that, the design remains the same, as does the algorithm to
 merge the bytemasks.  This remains as follows: