+2017-06-01 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/arc/arc.c (arc_expand_prologue): Emit a special barrier
+ to prevent store reordering.
+ * config/arc/arc.md (UNSPEC_ARC_STKTIE): Define.
+ (type): Add block type.
+ (stack_tie): Define special instruction to be used in
+ expand_prologue.
+
2017-06-01 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.md (commutative_binary_comparison): Remove 'I'
frame_size_to_allocate -= first_offset;
/* Allocate the stack frame. */
if (frame_size_to_allocate > 0)
- frame_stack_add ((HOST_WIDE_INT) 0 - frame_size_to_allocate);
+ {
+ frame_stack_add ((HOST_WIDE_INT) 0 - frame_size_to_allocate);
+ /* If the frame pointer is needed, emit a special barrier that
+ will prevent the scheduler from moving stores to the frame
+ before the stack adjustment. */
+ if (arc_frame_pointer_needed ())
+ emit_insn (gen_stack_tie (stack_pointer_rtx,
+ hard_frame_pointer_rtx));
+ }
/* Setup the gp register, if needed. */
if (crtl->uses_pic_offset_table)
UNSPEC_ARC_VMAC2HU
UNSPEC_ARC_VMPY2H
UNSPEC_ARC_VMPY2HU
+ UNSPEC_ARC_STKTIE
])
(define_c_enum "vunspec" [
simd_vcompare, simd_vpermute, simd_vpack, simd_vpack_with_acc,
simd_valign, simd_valign_with_acc, simd_vcontrol,
simd_vspecial_3cycle, simd_vspecial_4cycle, simd_dma, mul16_em, div_rem,
- fpu"
+ fpu, block"
(cond [(eq_attr "is_sfunc" "yes")
(cond [(match_test "!TARGET_LONG_CALLS_SET && (!TARGET_MEDIUM_CALLS || GET_CODE (PATTERN (insn)) != COND_EXEC)") (const_string "call")
(match_test "flag_pic") (const_string "sfunc")]
(set_attr "predicable" "yes,no,no,yes,no")
(set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond")])
+(define_insn "stack_tie"
+ [(set (mem:BLK (scratch))
+ (unspec:BLK [(match_operand:SI 0 "register_operand" "rb")
+ (match_operand:SI 1 "register_operand" "rb")]
+ UNSPEC_ARC_STKTIE))]
+ ""
+ ""
+ [(set_attr "length" "0")
+ (set_attr "iscompact" "false")
+ (set_attr "type" "block")]
+ )
+
;; include the arc-FPX instructions
(include "fpx.md")