Also allow "module foobar(input foo, output bar, ...);" syntax

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 95d7f393552e91321eef75799ba209d9384079a9..f619d3c2b0cba15658c6816def67a86b0e8843b3 100644 (file)
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -247,8 +247,7 @@ single_module_para:
        };
 
 module_args_opt:
-       '(' ')' | /* empty */ | '(' module_args optional_comma ')' |
-       '(' '.' '.' '.' ')' { do_not_require_port_stubs = true; };
+       '(' ')' | /* empty */ | '(' module_args optional_comma ')';
 
 module_args:
        module_arg | module_args ',' module_arg;
@@ -297,7 +296,10 @@ module_arg:
                ast_stack.back()->children.push_back(node);
                append_attr(node, $1);
                delete $4;
-       } module_arg_opt_assignment;
+       } module_arg_opt_assignment |
+       '.' '.' '.' {
+               do_not_require_port_stubs = true;
+       };
 
 wire_type:
        {