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power_insn: support vli specifier
author
Dmitry Selyutin
<ghostmansd@gmail.com>
Tue, 20 Sep 2022 12:55:11 +0000
(15:55 +0300)
committer
Dmitry Selyutin
<ghostmansd@gmail.com>
Tue, 20 Sep 2022 12:55:11 +0000
(15:55 +0300)
src/openpower/decoder/power_insn.py
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diff --git
a/src/openpower/decoder/power_insn.py
b/src/openpower/decoder/power_insn.py
index cfc1bf6f322208f52afe6560689f75951fdc199e..6623836994f49f77a0b44e0ca99e01be9ddfa5ab 100644
(file)
--- a/
src/openpower/decoder/power_insn.py
+++ b/
src/openpower/decoder/power_insn.py
@@
-1483,6
+1483,9
@@
class NormalFFRc0RM(FFPRRc0BaseRM, NormalBaseRM):
RC1: BaseRM.mode[4]
def specifiers(self, record):
+ if self.VLi:
+ yield "vli"
+
yield from super().specifiers(record=record, mode="ff")