+1999-10-11 Jim Blandy <jimb@zwingli.cygnus.com>
+
+ * config/pa/tm-hppa.h (SYMBOLS_CAN_START_WITH_DOLLAR): It's not
+ enough to #define this; you have to give it a non-zero value.
+
+1999-10-11 Jim Blandy <jimb@zenia.red-bean.com>
+
+ Fix from Jim Kingdon <kingdon@redhat.com>, with tweaks to make it
+ gdbarch- and bigendian-friendly:
+ * valops.c (PARM_BOUNDARY): If not #defined, default to zero.
+ (value_push): If PARM_BOUNDARY is not zero, align arguments to
+ that boundary.
+ * config/i386/tm-i386.h: Define PARM_BOUNDARY.
+
+Mon Oct 11 14:23:55 1999 Fred Fish <fnf@cygnus.com>
+
+ * config/mips/tm-irix3.h (PS_REGNUM): Don't undef if we aren't
+ going to redefine it to something else.
+
+1999-10-11 Jason Merrill <jason@yorick.cygnus.com>
+
+ * dwarfread.c (read_func_scope): Don't try to set main_func_*;
+ we handle that in blockframe.c:inside_main_func.
+ * dwarf2read.c (read_func_scope): Likewise.
+ (dwarf2_add_field, dwarf2_add_member_fn): Get member function name
+ directly, not from mangled name.
+ (skip_member_fn_name): Lose.
+
+Mon Oct 11 12:24:52 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * serial.h (enum serial_rc): Clarify SERIAL_TIMEOUT and
+ restrictions on TIMEOUT in ASYNC mode.
+
+ * serial.c (serial_readchar): Check for invalid timeout when in
+ async mode. Disable test.
+
+Thu Oct 7 17:20:01 1999 Andrew Cagney <cagney@amy.cygnus.com>
+
+ * monitor.c (monitor_printable_string): Add length argument. Don't
+ return final string length.
+ (monitor_printf_noecho, monitor_printf, monitor_expect): Update.
+ (monitor_error): Pass real_len to monitor_printable_string.
+ (monitor_error): Rewrite. Replace printf fmt string parameter with
+ function name and message parameters.
+ (monitor_read_memory_single, monitor_read_memory): Update.
+
+1999-10-07 Stan Shebs <shebs@andros.cygnus.com>
+
+ * main.c (print_gdb_help): Fix bug reporting address.
+ * gnu-regex.h, gnu-regex.c: Ditto.
+
+1999-10-07 Jim Blandy <jimb@zwingli.cygnus.com>
+
+ * parse.c (SYMBOLS_CAN_START_WITH_DOLLAR): New macro,
+ whose value can be overridden by target files.
+ (write_dollar_variable): Don't check the symbol table for
+ identifiers beginning with `$' unless
+ SYMBOLS_CAN_START_WITH_DOLLAR is non-zero.
+ * config/pa/tm-hppa.h (SYMBOLS_CAN_START_WITH_DOLLAR): Define.
+ * doc/gdbint.texinfo (SYMBOLS_CAN_START_WITH_DOLLAR): Document.
+
+ Remove all traces of the BINOP_SCOPE operator. It's never
+ generated, and not implemented.
+ * expression.h (enum exp_opcode): Delete BINOP_SCOPE.
+ * c-lang.c (c_op_print_tab): Delete entry for BINOP_SCOPE.
+ * eval.c (evaluate_subexp_standard): Doc fix.
+ * expprint.c (op_name): Remove case for BINOP_SCOPE.
+ (dump_subexp): Same.
+
+ * dwarf2read.c (dwarf2_const_value): Treat DW_FORM_data1,
+ DW_FORM_data2, DW_FORM_data4, and DW_FORM_data8 as signed values,
+ since that's what read_var_value will do anyway.
+
+1999-10-07 Fred Fish <fnf@cygnus.com>
+
+ * objfiles.h (struct objfile): Delete is_solib member, now handled
+ by OBJF_SHARED bit in struct objfile's flags.
+ * objfiles.c (objfile_purge_solibs): Check OBJF_SHARED bit in flags
+ instead of old is_solib int member in objfile struct.
+
+ * objfiles.c (allocate_objfile): Remove is_solib arg. Now passed
+ as a bit in combined flags arg.
+ * symfile.c (symbol_file_add): Ditto.
+ * objfiles.h (allocate_objfile): Adjust prototype after removal
+ of is_solib arg.
+ * symtab.h (symbol_file_add): Ditto.
+
+ * cxux-nat.c (add_shared_symbol_files): Remove zero passed to
+ symbol_file_add in old is_solib arg, defaults to zero now in
+ flags.
+ * irix5-nat.c (symbol_add_stub): Ditto.
+ * remote-mm.c (mm_load): Ditto.
+ * remote-udi.c (udi_load): Ditto.
+ * remote-vx.c (vx_add_symbols): Ditto.
+ * symfile.c (symbol_file_command): Ditto.
+ (add_symbol_file_command): Ditto.
+
+ * coff-solib.c (coff_solib_add): Call symbol_file_add with
+ OBJF_SHARED in flags bit, rather than 1 in old is_solib
+ arg.
+ * osfsolib.c (symbol_add_stub): Ditto.
+ * pa64solib.c (pa64_solib_add_solib_objfile): Ditto.
+ * solib.c (symbol_add_stub): Ditto.
+ * somsolib.c (som_solib_add_solib_objfile): Ditto.
+ * win32-nat.c (handle_load_dll): Ditto.
+
+ * objfiles.c (allocate_objfile): Remove old args "mapped" and
+ "user_loaded". Replaced with new arg "flags" containing specific
+ If global var mapped_symbol_files is nonzero
+ then set OBJF_MAPPED in flags arg. Check for OBJF_MAPPED bit in
+ flags where we used to check mapped arg.
+ Pass flags to open_mapped_file instead of mapped arg.
+ Ensure that OBJF_MAPPED bit is reset in flags when the objfile
+ is not mapped. Add passed flags bits to objfile's flags bits.
+ (open_mapped_file): Replace "mapped" arg with new "flags" arg.
+ Adjust prototype. Pass flags to open_existing_mapped_file.
+ (open_existing_mapped_file): Replace "mapped" arg with new "flags".
+ Check flags for OBJF_MAPPED.
+ * objfiles.h (allocate_objfile): Adjust prototype.
+ * rs6000-nat.c (add_vmap): Pass zero for combined flags, rather
+ than separate zero ints for old "mapped" and "user_loaded" flags.
+ * symfile.c (symbol_file_add): Pass allocate_objfile combined flags
+ rather than individual mapped and user loaded bits.
+
+ * symfile.c (symbol_file_add): Delete user_loaded arg.
+ * symtab.h (symbol_file_add): Adjust prototype for deleted
+ user_loaded arg.
+ * objfiles.h (struct objfile): Delete user_loaded member.
+ (OBJF_USERLOADED): New flag bit to replace user_loaded.
+
+ * symfile.c (symbol_file_command): Add OBJF_USER_LOADED to flags
+ passed to symbol_file_add. Delete previous passing of explicit 1
+ for user_loaded.
+ (add_symbol_file_command): Ditto.
+
+ * coff-solib.c (coff_solib_add): No longer pass zero for user loaded,
+ now defaults to zero in flags.
+ * cxux-nat.c (add_shared_symbol_files): Ditto.
+ * irix5-nat.c (symbol_add_stub): Ditto.
+ * osfsolib.c (symbol_add_stub): Ditto.
+ * remote-mm.c (mm_load): Ditto.
+ * pa64solib.c (pa64_solib_add_solib_objfile): Ditto.
+ * remote-udi.c (udi_load): Ditto.
+ * remote-vx.c (vx_add_symbols): Ditto.
+ * solib.c (symbol_add_stub): Ditto.
+ * somsolib.c (som_solib_add_solib_objfile): Ditto.
+ * win32-nat.c (handle_load_dll): Ditto.
+
+Thu Oct 7 19:24:05 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (monitor.o): Allow monitor.o to be compiled with
+ -Werror.
+
+ * monitor.c (monitor_debug_p): New variable. Replaces macro.
+ (EXTRA_RDEBUG): Delete. Update all uses.
+ (monitor_debug): New function. Replaces macro.
+ (RDEBUG): Delete macro. Update all uses.
+ debug output to gdb_stdlog and not the console.
+
+ * monitor.c: Fix printf formating. Replace printf calls with
+ fprintf_unfiltered.
+
+1999-10-06 Stan Shebs <shebs@andros.cygnus.com>
+
+ * MAINTAINERS: Switch ARM target maintenance from Elena
+ Zannoni to Jim Ingham.
+
+1999-10-06 Frank Ch. Eigler <fche@cygnus.com>
+
+ * remote.c (hexnumnstr): New function. Allow setting of width.
+ (hexnumstr): Call the above.
+ (remote_write_bytes): Fill in X-protocol address field more
+ reliably.
+
+1999-10-06 Fred Fish <fnf@cygnus.com>
+
+ * xcoffread.c (xcoff_symfile_offsets): Fix typo, addr->addrs.
+
+1999-10-06 Elena Zannoni <ezannoni@kwikemart.cygnus.com>
+
+ * remote.c (handle_remote_sigint_twice): Make this signal be
+ handled by inferior_event_handler, via the wrapper function.
+ (async_remote_interrupt_twice): Make not static. Add debug print.
+ * remote.h (async_remote_interrupt_twice): Export for use in
+ inf-loop.c.
+
+ * inf-loop.c (inferior_event_handler_wrapper): New function.
+ (inferior_event_handler): Handle a request to quit and kill the
+ target.
+ Include remote.h.
+ * inf-loop.h (inferior_event_handler_wrapper): Export.
+
1999-10-04 James Ingham <jingham@leda.cygnus.com>
* remote-rdi.c (arm_rdi_open): If the angel_RDI_Open fails, close
* remote-sim.c (gdbsim_create_inferior): Ditto.
* target.c (target_link): Ditto.
* win32-nat.c (child_create_inferior): Ditto.
- * varobj.c (varobj_create, new_root_variable): Ditto.
Thu Sep 30 10:36:19 1999 Andrew Cagney <cagney@b1.cygnus.com>
win32 host & native Chris Faylor cgf@cygnus.com
main (main.c, top.c) Elena Zannoni ezannoni@cygnus.com
readline Elena Zannoni ezannoni@cygnus.com
-arm target Elena Zannoni ezannoni@cygnus.com
powerpc target Elena Zannoni ezannoni@cygnus.com
command interpreter Fernando Nasser fnasser@cygnus.com
generic symtabs Jim Blandy jimb@cygnus.com
x86 linux native Jim Blandy jimb@cygnus.com
Scheme support Jim Blandy jimb@cygnus.com
svr4 shlibs (solib.c) Jim Blandy jimb@cygnus.com
+arm target Jim Ingham jingham@cygnus.com
hurd native Mark Kettenis kettenis@wins.va.nl
hpux, hp pa native Jeff Law law@cygnus.com
m32r target Michael Snyder msnyder@cygnus.com
ADD_FILES = $(REGEX) $(XM_ADD_FILES) $(TM_ADD_FILES) $(NAT_ADD_FILES)
ADD_DEPS = $(REGEX1) $(XM_ADD_FILES) $(TM_ADD_FILES) $(NAT_ADD_FILES)
-VERSION = 19991004
+VERSION = 19991011
DIST=gdb
LINT=/usr/5bin/lint
mipsv4-nat.o: mipsv4-nat.c $(defs_h) $(gdbcore_h) $(inferior_h) target.h
-# FIXME: Monitor.c has -Wformat problems. The code using the macros
-# RDEBUG and EXTRA_RDEBUG needs be replaced with something that:
-# doesn't cause -Wformat errors; sends all output to gdb_stdlog
-# instead of stdout; and controls the output throug a ``set
-# monitordebug'' command/variable. cagney, 1999-09-01.
monitor.o: monitor.c monitor.h $(bfd_h) $(wait_h) $(defs_h) $(gdbcmd_h) \
$(inferior_h) target.h serial.h terminal.h gdb_string.h
- $(CC) -c $(INTERNAL_WARN_CFLAGS) $(NO_WERROR_CFLAGS) $<
news-xdep.o: news-xdep.c
{"sizeof ", UNOP_SIZEOF, PREC_PREFIX, 0},
{"++", UNOP_PREINCREMENT, PREC_PREFIX, 0},
{"--", UNOP_PREDECREMENT, PREC_PREFIX, 0},
- /* C++ */
- {"::", BINOP_SCOPE, PREC_PREFIX, 0},
{NULL, 0, 0, 0}
};
\f
objfile = symbol_file_add (filename, from_tty,
NULL, /* no offsets */
0, /* not mainline */
- 0, /* flags */
- 0, /* Not user loaded */
- 1); /* Is a solib */
+ OBJF_SHARED); /* flags */
libsize -= len * 4;
lib += len * 4;
/* Things needed for making the inferior call functions. */
+/* "An argument's size is increased, if necessary, to make it a
+ multiple of [32 bit] words. This may require tail padding,
+ depending on the size of the argument" - from the x86 ABI. */
+#define PARM_BOUNDARY 32
+
/* Push an empty stack frame, to record the current PC, etc. */
#define PUSH_DUMMY_FRAME { i386_push_dummy_frame (); }
#undef MIPS_REGISTER_NAMES
#undef FP0_REGNUM
#undef PC_REGNUM
-#undef PS_REGNUM
#undef HI_REGNUM
#undef LO_REGNUM
#undef CAUSE_REGNUM
/* Here's how to step off a permanent breakpoint. */
#define SKIP_PERMANENT_BREAKPOINT (hppa_skip_permanent_breakpoint)
extern void hppa_skip_permanent_breakpoint (void);
+
+/* On HP-UX, certain system routines (millicode) have names beginning
+ with $ or $$, e.g. $$dyncall, which handles inter-space procedure
+ calls on PA-RISC. Tell the expression parser to check for those
+ when parsing tokens that begin with "$". */
+#define SYMBOLS_CAN_START_WITH_DOLLAR (1)
return;
}
- objfile = symbol_file_add (LIBC_FILE, 0, NULL, 0, OBJF_READNOW, 0, 0);
+ objfile = symbol_file_add (LIBC_FILE, 0, NULL, 0, OBJF_READNOW);
minsym = lookup_minimal_symbol (LINKS_MAP_POINTER, objfile);
ld_map = (struct link_map *)
struct section_addr_info section_addrs;
memset (§ion_addrs, 0, sizeof (section_addrs));
section_addrs.text_addr = lms.l_addr;
- symbol_file_add (path_name, 1, §ion_addrs, 0, 0, 0, 0);
+ symbol_file_add (path_name, 1, §ion_addrs, 0, 0);
free (path_name);
}
}
+1999-10-11 Jim Kingdon <kingdon@redhat.com>
+
+ * gdbint.texinfo (Target Architecture Definition): Add PARM_BOUNDARY.
+
+1999-10-05 Stan Shebs <shebs@andros.cygnus.com>
+
+ From Dmitry Sivachenko <demon@gpad.ac.ru>:
+ * gdb.texinfo: Use GDBP and GDBN everywhere, fix a couple other
+ typos.
+
+ * gdb.texinfo: Various minor wording and formatting improvements,
+ mentions of additional command-line options.
+
1999-09-30 Fred Fish <fnf@cygnus.com>
* gdb.texinfo: Document additional forms of specifying section
Cygnus Solutions has sponsored GDB maintenance and much of its
development since 1991. Cygnus engineers who have worked on GDB
-fulltime include Mark Alexander, Jim Blandy, Per Bothner, Edith Epstein,
-Chris Faylor, Fred Fish, Martin Hunt, Jim Ingham, John Gilmore, Stu
-Grossman, Kung Hsu, Jim Kingdon, John Metzler, Fernando Nasser, Geoffrey
-Noer, Dawn Perchik, Rich Pixley, Zdenek Radouch, Keith Seitz, Stan
-Shebs, David Taylor, and Elena Zannoni. In addition, Dave Brolley, Ian
-Carmichael, Steve Chamberlain, Nick Clifton, JT Conklin, Stan Cox, DJ
-Delorie, Ulrich Drepper, Frank Eigler, Doug Evans, Sean Fagan, David
-Henkel-Wallace, Richard Henderson, Jeff Holcomb, Jeff Law, Jim Lemke,
-Tom Lord, Bob Manson, Michael Meissner, Jason Merrill, Catherine Moore,
-Drew Moseley, Ken Raeburn, Gavin Romig-Koch, Rob Savoye, Jamie Smith,
-Mike Stump, Ian Taylor, Angela Thomas, Michael Tiemann, Tom Tromey, Ron
-Unrau, Jim Wilson, and David Zuhn have made contributions both large
-and small.
+fulltime include Mark Alexander, Jim Blandy, Per Bothner, Kevin
+Buettner, Edith Epstein, Chris Faylor, Fred Fish, Martin Hunt, Jim
+Ingham, John Gilmore, Stu Grossman, Kung Hsu, Jim Kingdon, John Metzler,
+Fernando Nasser, Geoffrey Noer, Dawn Perchik, Rich Pixley, Zdenek
+Radouch, Keith Seitz, Stan Shebs, David Taylor, and Elena Zannoni. In
+addition, Dave Brolley, Ian Carmichael, Steve Chamberlain, Nick Clifton,
+JT Conklin, Stan Cox, DJ Delorie, Ulrich Drepper, Frank Eigler, Doug
+Evans, Sean Fagan, David Henkel-Wallace, Richard Henderson, Jeff
+Holcomb, Jeff Law, Jim Lemke, Tom Lord, Bob Manson, Michael Meissner,
+Jason Merrill, Catherine Moore, Drew Moseley, Ken Raeburn, Gavin
+Romig-Koch, Rob Savoye, Jamie Smith, Mike Stump, Ian Taylor, Angela
+Thomas, Michael Tiemann, Tom Tromey, Ron Unrau, Jim Wilson, and David
+Zuhn have made contributions both large and small.
@node Sample Session
named @file{1234}; @value{GDBN} does check for a core file first).
Taking advantage of the second command-line argument requires a fairly
-complete operating system; when you use @value{GDBN} as a remote debugger
-attached to a bare board, there may not be any notion of ``process'',
-and there is often no way to get a core dump.
+complete operating system; when you use @value{GDBN} as a remote
+debugger attached to a bare board, there may not be any notion of
+``process'', and there is often no way to get a core dump. @value{GDBN}
+will warn you if it is unable to attach or to read core dumps.
You can run @code{gdb} without printing the front material, which describes
@value{GDBN}'s non-warranty, by specifying @code{-silent}:
@node File Options
@subsection Choosing files
-When @value{GDBN} starts
+When @value{GDBN} starts, it reads any arguments other than options as
specifying an executable file and core file (or process ID). This is
the same as if the arguments were specified by the @samp{-se} and
@samp{-c} options respectively. (@value{GDBN} reads the first argument
@end table
-The @code{-mapped} and @code{-readnow} options are typically combined in
+You typically combine the @code{-mapped} and @code{-readnow} options in
order to build a @file{.syms} file that contains complete symbol
-information. (@xref{Files,,Commands to specify files}, for
-information on @file{.syms} files.) A simple @value{GDBN} invocation to do
-nothing but build a @file{.syms} file for future use is:
+information. (@xref{Files,,Commands to specify files}, for information
+on @file{.syms} files.) A simple @value{GDBN} invocation to do nothing
+but build a @file{.syms} file for future use is:
@example
- gdb -batch -nx -mapped -readnow programname
+gdb -batch -nx -mapped -readnow programname
@end example
@node Mode Options
@table @code
@item -nx
@itemx -n
-Do not execute commands from any initialization files (normally called
-@file{.gdbinit}, or @file{gdb.ini} on PCs). Normally, the commands in
-these files are executed after all the command options and arguments
-have been processed. @xref{Command Files,,Command files}.
+Do not execute commands found in any initialization files (normally
+called @file{.gdbinit}, or @file{gdb.ini} on PCs). Normally,
+@value{GDBN} executes the commands in these files after all the command
+options and arguments have been processed. @xref{Command Files,,Command
+files}.
@item -quiet
@itemx -q
nonzero status if an error occurs in executing the @value{GDBN} commands
in the command files.
-Batch mode may be useful for running @value{GDBN} as a filter, for example to
-download and run a program on another computer; in order to make this
-more useful, the message
+Batch mode may be useful for running @value{GDBN} as a filter, for
+example to download and run a program on another computer; in order to
+make this more useful, the message
@example
Program exited normally.
@end example
@noindent
-(which is ordinarily issued whenever a program running under @value{GDBN} control
-terminates) is not issued when running in batch mode.
+(which is ordinarily issued whenever a program running under
+@value{GDBN} control terminates) is not issued when running in batch
+mode.
+
+@item -nowindows
+@itemx -nw
+``No windows''. If @value{GDBN} comes with a graphical user interface
+(GUI) built in, then this option tells GDB to only use the command-line
+interface. If no GUI is available, this option has no effect.
+
+@item -windows
+@itemx -w
+If @value{GDBN} includes a GUI, then this option requires it to be
+used if possible.
@item -cd @var{directory}
Run @value{GDBN} using @var{directory} as its working directory,
@samp{\032} characters as a signal to display the source code for the
frame.
-@item -b @var{bps}
+@item -baud @var{bps}
+@itemx -b @var{bps}
Set the line speed (baud rate or bits per second) of any serial
interface used by @value{GDBN} for remote debugging.
(@value{GDBP}) help
List of classes of commands:
-running -- Running the program
-stack -- Examining the stack
-data -- Examining data
+aliases -- Aliases of other commands
breakpoints -- Making program stop at certain points
+data -- Examining data
files -- Specifying and examining files
+internals -- Maintenance commands
+obscure -- Obscure features
+running -- Running the program
+stack -- Examining the stack
status -- Status inquiries
support -- Support facilities
+tracepoints -- Tracing of program execution without stopping the program
user-defined -- User-defined commands
-aliases -- Aliases of other commands
-obscure -- Obscure features
Type "help" followed by a class name for a list of
commands in that class.
@c Line break in "show" line falsifies real output, but needed
@c to fit in smallbook page size.
-show -- Generic command for showing things set
- with "set"
-info -- Generic command for printing status
+info -- Generic command for showing things
+ about the program being debugged
+show -- Generic command for showing things
+ about the debugger
Type "help" followed by command name for full
documentation.
@smallexample
@group
+if
+ignore
info
inspect
-ignore
@end group
@end smallexample
@cindex version number
@item show version
Show what version of @value{GDBN} is running. You should include this
-information in @value{GDBN} bug-reports. If multiple versions of @value{GDBN} are in
-use at your site, you may occasionally want to determine which version
-of @value{GDBN} you are running; as @value{GDBN} evolves, new commands are introduced,
-and old ones may wither away. The version number is also announced
-when you start @value{GDBN}.
+information in @value{GDBN} bug-reports. If multiple versions of
+@value{GDBN} are in use at your site, you may need to determine which
+version of @value{GDBN} you are running; as @value{GDBN} evolves, new
+commands are introduced, and old ones may wither away. Also, many
+system vendors ship variant versions of @value{GDBN}, and there are
+variant versions of @value{GDBN} in GNU/Linux distributions as well.
+The version number is the same as the one announced when you start
+@value{GDBN}.
@kindex show copying
@item show copying
@kindex show warranty
@item show warranty
-Display the @sc{gnu} ``NO WARRANTY'' statement.
+Display the @sc{gnu} ``NO WARRANTY'' statement, or a warranty,
+if your version of @value{GDB} comes with one.
+
@end table
@node Running
@table @code
@item parent
The original process is debugged after a fork. The child process runs
-unimpeded.
+unimpeded. This is the default.
@item child
The new process is debugged after a fork. The parent process runs
@end table
@item show follow-fork-mode
-Display the current debugger response to a fork or vfork call.
+Display the current debugger response to a @code{fork} or @code{vfork} call.
@end table
If you ask to debug a child process and a @code{vfork} is followed by an
@itemx break -@var{offset}
Set a breakpoint some number of lines forward or back from the position
at which execution stopped in the currently selected @dfn{stack frame}.
-(@xref{Frames, , Frames}, for a description of stack frames.)
+(@xref{Frames, ,Frames}, for a description of stack frames.)
@item break @var{linenum}
Set a breakpoint at line @var{linenum} in the current source file.
Enabled breakpoints are marked with @samp{y}. @samp{n} marks breakpoints
that are not enabled.
@item Address
-Where the breakpoint is in your program, as a memory address
+Where the breakpoint is in your program, as a memory address.
@item What
Where the breakpoint is in the source for your program, as a file and
line number.
this may happen.
Depending on your system, watchpoints may be implemented in software or
-hardware. GDB does software watchpointing by single-stepping your
+hardware. @value{GDBN} does software watchpointing by single-stepping your
program and testing the variable's value each time, which is hundreds of
times slower than normal execution. (But this may still be worth it, to
catch errors where you have no clue what part of your program is the
culprit.)
On some systems, such as HP-UX, Linux and some other x86-based targets,
-GDB includes support for
+@value{GDBN} includes support for
hardware watchpoints, which do not slow down the running of your
program.
@kindex awatch
@item awatch @var{expr}
-Set a watchpoint that will break when @var{args} is either read or written into
+Set a watchpoint that will break when @var{expr} is either read or written into
by the program.
@kindex info watchpoints
Delete or disable unused watchpoint commands before setting new ones.
If you call a function interactively using @code{print} or @code{call},
-any watchpoints you have set will be inactive until GDB reaches another
+any watchpoints you have set will be inactive until @value{GDBN} reaches another
kind of breakpoint or the call completes.
@value{GDBN} automatically deletes watchpoints that watch local
breakpoint condition, like this:
@smallexample
-(gdb) break frik.c:13 thread 28 if bartab > lim
+(@value{GDBP}) break frik.c:13 thread 28 if bartab > lim
@end smallexample
@end table
function call, and they are completely free to run when you use commands
like @samp{continue}, @samp{until}, or @samp{finish}. However, unless another
thread hits a breakpoint during its timeslice, they will never steal the
-GDB prompt away from the thread that you are debugging.
+@value{GDBN} prompt away from the thread that you are debugging.
@item show scheduler-locking
Display the current scheduler locking mode.
(@value{GDBP}) p g
$1 = 1
(@value{GDBP}) set g=4
-(gdb) p g
+(@value{GDBP}) p g
$2 = 1
(@value{GDBP}) r
The program being debugged has been started already.
@kindex target sim
@item target sim
-Builtin CPU simulator. GDB includes simulators for most architectures.
+Builtin CPU simulator. @value{GDBN} includes simulators for most architectures.
In general,
@example
target sim
@item detach @emph{(optional)}
@tab @code{D}
@tab
-Detach GDB from the remote system. Sent to the remote target before
-GDB disconnects.
+Detach @value{GDBN} from the remote system. Sent to the remote target before
+@value{GDBN} disconnects.
@item
@tab reply @emph{no response}
@tab
-GDB does not check for any response after sending this packet
+@value{GDBN} does not check for any response after sending this packet
@item reserved
@tab @code{e}
Each byte of register data is described by two hex digits. The bytes
with the register are transmitted in target byte order. The size of
each register and their position within the @samp{g} @var{packet} are
-determined by the GDB internal macros @var{REGISTER_RAW_SIZE} and
+determined by the @value{GDBN} internal macros @var{REGISTER_RAW_SIZE} and
@var{REGISTER_NAME} macros. The specification of several standard
@code{g} packets is specified below.
@item
@tab @code{m}@var{addr}@code{,}@var{length}
@tab
Read @var{length} bytes of memory starting at address @var{addr}.
-Neither GDB nor the stub assume that sized memory transfers are assumed
+Neither @value{GDBN} nor the stub assume that sized memory transfers are assumed
using word alligned accesses. FIXME: @emph{A word aligned memory
transfer mechanism is needed.}
@item
@tab reply @var{XX...}
@tab
@var{XX...} is mem contents. Can be fewer bytes than requested if able
-to read only part of the data. Neither GDB nor the stub assume that
+to read only part of the data. Neither @value{GDBN} nor the stub assume that
sized memory transfers are assumed using word alligned accesses. FIXME:
@emph{A word aligned memory transfer mechanism is needed.}
@item
@value{GDBN} which kernel object display module to initialize:
@example
-(gdb) set os cisco
+(@value{GDBP}) set os cisco
@end example
If @code{set os} succeeds, @value{GDBN} will display some information
after the operating system:
@example
-(gdb) info cisco
+(@value{GDBP}) info cisco
List of Cisco Kernel Objects
Object Description
any Any and all objects
that you want to use @samp{target hms}, the remote debugging interface
for Hitachi microprocessors, or @samp{target e7000}, the in-circuit
emulator for the Hitachi SH and the Hitachi 300H. (@samp{target hms} is
-the default when GDB is configured specifically for the Hitachi SH,
+the default when @value{GDBN} is configured specifically for the Hitachi SH,
H8/300, or H8/500.)
@item
@cindex serial line speed, Hitachi micros
@code{@value{GDBP}} has another special command to set the communications
speed: @samp{speed @var{bps}}. This command also is only used from Unix
-hosts; on DOS hosts, set the line speed as usual from outside GDB with
+hosts; on DOS hosts, set the line speed as usual from outside @value{GDBN} with
the DOS @code{mode} command (for instance,
@w{@kbd{mode com2:9600,n,8,1,p}} for a 9600@dmn{bps} connection).
@smallexample
(eg-C:\H8300\TEST) @value{GDBP} t.x
-GDB is free software and you are welcome to distribute copies
+@value{GDBN} is free software and you are welcome to distribute copies
of it under certain conditions; type "show copying" to see
the conditions.
-There is absolutely no warranty for GDB; type "show warranty"
+There is absolutely no warranty for @value{GDBN}; type "show warranty"
for details.
-GDB @value{GDBVN}, Copyright 1992 Free Software Foundation, Inc...
-(gdb) target hms
+@value{GDBN} @value{GDBVN}, Copyright 1992 Free Software Foundation, Inc...
+(@value{GDBP}) target hms
Connected to remote H8/300 HMS system.
-(gdb) load t.x
+(@value{GDBP}) load t.x
.text : 0x8000 .. 0xabde ***********
.data : 0xabde .. 0xad30 *
.stack : 0xf000 .. 0xf014 *
@example
host$ @value{GDBP} @var{prog}
-GDB is free software and @dots{}
-(gdb) target mips /dev/ttyb
-(gdb) load @var{prog}
-(gdb) run
+@value{GDBN} is free software and @dots{}
+(@value{GDBP}) target mips /dev/ttyb
+(@value{GDBP}) load @var{prog}
+(@value{GDBP}) run
@end example
@item target mips @var{hostname}:@var{portnumber}
@node ST2000
@subsection Tandem ST2000
-GDB may be used with a Tandem ST2000 phone switch, running Tandem's
+@value{GDBN} may be used with a Tandem ST2000 phone switch, running Tandem's
STDBUG protocol.
To connect your ST2000 to the host system, see the manufacturer's
@section Architectures
This section describes characteristics of architectures that affect
-all uses of GDB with this architecture, both native and cross.
+all uses of @value{GDBN} with the architecture, both native and cross.
@menu
* A29K::
@cindex number representation
@cindex entering numbers
-You can always enter numbers in octal, decimal, or hexadecimal in @value{GDBN} by
-the usual conventions: octal numbers begin with @samp{0}, decimal
-numbers end with @samp{.}, and hexadecimal numbers begin with @samp{0x}.
-Numbers that begin with none of these are, by default, entered in base
-10; likewise, the default display for numbers---when no particular
-format is specified---is base 10. You can change the default base for
-both input and output with the @code{set radix} command.
+You can always enter numbers in octal, decimal, or hexadecimal in
+@value{GDBN} by the usual conventions: octal numbers begin with
+@samp{0}, decimal numbers end with @samp{.}, and hexadecimal numbers
+begin with @samp{0x}. Numbers that begin with none of these are, by
+default, entered in base 10; likewise, the default display for
+numbers---when no particular format is specified---is base 10. You can
+change the default base for both input and output with the @code{set
+radix} command.
@table @code
@kindex set input-radix
@node Messages/Warnings
@section Optional warnings and messages
-By default, @value{GDBN} is silent about its inner workings. If you are running
-on a slow machine, you may want to use the @code{set verbose} command.
-This makes @value{GDBN} tell you when it does a lengthy internal operation, so
-you will not think it has crashed.
+By default, @value{GDBN} is silent about its inner workings. If you are
+running on a slow machine, you may want to use the @code{set verbose}
+command. This makes @value{GDBN} tell you when it does a lengthy
+internal operation, so you will not think it has crashed.
Currently, the messages controlled by @code{set verbose} are those
which announce that the symbol table for a source file is being read;
Displays whether @code{set verbose} is on or off.
@end table
-By default, if @value{GDBN} encounters bugs in the symbol table of an object
-file, it is silent; but if you are debugging a compiler, you may find
-this information useful (@pxref{Symbol Errors, ,Errors reading symbol files}).
+By default, if @value{GDBN} encounters bugs in the symbol table of an
+object file, it is silent; but if you are debugging a compiler, you may
+find this information useful (@pxref{Symbol Errors, ,Errors reading
+symbol files}).
@table @code
+
@kindex set complaints
@item set complaints @var{limit}
-Permits @value{GDBN} to output @var{limit} complaints about each type of unusual
-symbols before becoming silent about the problem. Set @var{limit} to
-zero to suppress all complaints; set it to a large number to prevent
-complaints from being suppressed.
+Permits @value{GDBN} to output @var{limit} complaints about each type of
+unusual symbols before becoming silent about the problem. Set
+@var{limit} to zero to suppress all complaints; set it to a large number
+to prevent complaints from being suppressed.
@kindex show complaints
@item show complaints
Displays how many symbol complaints @value{GDBN} is permitted to produce.
+
@end table
By default, @value{GDBN} is cautious, and asks what sometimes seems to be a
commands, you can disable this ``feature'':
@table @code
+
@kindex set confirm
@cindex flinching
@cindex confirmation
@kindex show confirm
@item show confirm
Displays state of confirmation requests.
+
@end table
@node Sequences
@chapter Canned Sequences of Commands
Aside from breakpoint commands (@pxref{Break Commands, ,Breakpoint
-command lists}), @value{GDBN} provides two ways to store sequences of commands
-for execution as a unit: user-defined commands and command files.
+command lists}), @value{GDBN} provides two ways to store sequences of
+commands for execution as a unit: user-defined commands and command
+files.
@menu
* Define:: User-defined commands
@section User-defined commands
@cindex user-defined command
-A @dfn{user-defined command} is a sequence of @value{GDBN} commands to which
-you assign a new name as a command. This is done with the @code{define}
-command. User commands may accept up to 10 arguments separated by whitespace.
-Arguments are accessed within the user command via @var{$arg0@dots{}$arg9}.
-A trivial example:
+A @dfn{user-defined command} is a sequence of @value{GDBN} commands to
+which you assign a new name as a command. This is done with the
+@code{define} command. User commands may accept up to 10 arguments
+separated by whitespace. Arguments are accessed within the user command
+via @var{$arg0@dots{}$arg9}. A trivial example:
@smallexample
define adder
functions calls.
@table @code
+
@kindex define
@item define @var{commandname}
Define a command named @var{commandname}. If there is already a command
@kindex show user
@item show user
@itemx show user @var{commandname}
-Display the @value{GDBN} commands used to define @var{commandname} (but not its
-documentation). If no @var{commandname} is given, display the
+Display the @value{GDBN} commands used to define @var{commandname} (but
+not its documentation). If no @var{commandname} is given, display the
definitions for all user-defined commands.
+
@end table
When user-defined commands are executed, the
@dfn{init files}. These are files named @file{.gdbinit} on Unix, or
@file{gdb.ini} on DOS/Windows. @value{GDBN} reads the init file (if
any) in your home directory@footnote{On DOS/Windows systems, the home
-directory is the one pointed to by the @code{HOME} environment variable.},
-then processes command line options and
-operands, and then reads the init file (if any) in the current working
-directory. This is so the init file in your home directory can set
-options (such as @code{set complaints}) which affect the processing of
-the command line options and operands. The init files are not executed
-if you use the @samp{-nx} option; @pxref{Mode Options, ,Choosing modes}.
+directory is the one pointed to by the @code{HOME} environment
+variable.}, then processes command line options and operands, and then
+reads the init file (if any) in the current working directory. This is
+so the init file in your home directory can set options (such as
+@code{set complaints}) which affect the processing of the command line
+options and operands. The init files are not executed if you use the
+@samp{-nx} option; @pxref{Mode Options, ,Choosing modes}.
@cindex init file name
On some configurations of @value{GDBN}, the init file is known by a
feature-specific macros. It was introduced in haste and we are
repenting at leisure.
+@item SYMBOLS_CAN_START_WITH_DOLLAR
+Some systems have routines whose names start with @samp{$}. Giving this
+macro a non-zero value tells GDB's expression parser to check for such
+routines when parsing tokens that begin with @samp{$}.
+
+On HP-UX, certain system routines (millicode) have names beginning with
+@samp{$} or @samp{$$}. For example, @code{$$dyncall} is a millicode
+routine that handles inter-space procedure calls on PA-RISC.
+
@item IEEE_FLOAT
Define this if the target system uses IEEE-format floating point numbers.
The number of the ``next next program counter'' register, if defined.
Currently, this is only defined for the Motorola 88K.
+@item PARM_BOUNDARY
+If non-zero, round arguments to a boundary of this many bits before
+pushing them on the stack.
+
@item PRINT_REGISTER_HOOK (regno)
If defined, this must be a function that prints the contents of the
given register to standard output.
static void dwarf2_const_value PARAMS ((struct attribute *, struct symbol *,
struct objfile *));
+static void dwarf2_const_value_data (struct attribute *attr,
+ struct symbol *sym,
+ int bits);
+
static struct type *die_type PARAMS ((struct die_info *, struct objfile *));
static struct type *die_containing_type PARAMS ((struct die_info *,
struct type *,
struct objfile *));
-static char *skip_member_fn_name PARAMS ((char *));
-
static void dwarf2_add_member_fn PARAMS ((struct field_info *,
struct die_info *, struct type *,
struct objfile * objfile));
objfile->ei.entry_func_highpc = highpc;
}
- if (STREQ (name, "main")) /* FIXME: hardwired name */
- {
- objfile->ei.main_func_lowpc = lowpc;
- objfile->ei.main_func_highpc = highpc;
- }
-
/* Decode DW_AT_frame_base location descriptor if present, keep result
for DW_OP_fbreg operands in decode_locdesc. */
frame_base_reg = -1;
else if (die->tag == DW_TAG_variable)
{
char *physname;
- char *cp;
/* C++ static member.
- Get physical name, extract field name from physical name. */
- physname = dwarf2_linkage_name (die);
- if (physname == NULL)
+ Get name of field. */
+ attr = dwarf_attr (die, DW_AT_name);
+ if (attr && DW_STRING (attr))
+ fieldname = DW_STRING (attr);
+ else
return;
- cp = physname;
- while (*cp && !is_cplus_marker (*cp))
- cp++;
- if (*cp)
- fieldname = cp + 1;
- if (*fieldname == '\0')
- {
- complain (&dwarf2_bad_static_member_name, physname);
- }
+ /* Get physical name. */
+ physname = dwarf2_linkage_name (die);
SET_FIELD_PHYSNAME (*fp, obsavestring (physname, strlen (physname),
&objfile->type_obstack));
}
}
-/* Skip to the end of a member function name in a mangled name. */
-
-static char *
-skip_member_fn_name (physname)
- char *physname;
-{
- char *endname = physname;
-
- /* Skip over leading underscores. */
- while (*endname == '_')
- endname++;
-
- /* Find two succesive underscores. */
- do
- endname = strchr (endname, '_');
- while (endname != NULL && *++endname != '_');
-
- if (endname == NULL)
- {
- complain (&dwarf2_bad_member_name_complaint, physname);
- endname = physname;
- }
- else
- {
- /* Take care of trailing underscores. */
- if (endname[1] != '_')
- endname--;
- }
- return endname;
-}
-
/* Add a member function to the proper fieldlist. */
static void
char *physname;
struct nextfnfield *new_fnfield;
- /* Extract member function name from mangled name. */
- physname = dwarf2_linkage_name (die);
- if (physname == NULL)
- return;
- if ((physname[0] == '_' && physname[1] == '_'
- && strchr ("0123456789Qt", physname[2]))
- || DESTRUCTOR_PREFIX_P (physname))
- {
- /* Constructor and destructor field names are set to the name
- of the class, but without template parameter lists.
- The name might be missing for anonymous aggregates. */
- if (TYPE_TAG_NAME (type))
- {
- char *p = strchr (TYPE_TAG_NAME (type), '<');
-
- if (p == NULL)
- fieldname = TYPE_TAG_NAME (type);
- else
- fieldname = obsavestring (TYPE_TAG_NAME (type),
- p - TYPE_TAG_NAME (type),
- &objfile->type_obstack);
- }
- else
- {
- char *anon_name = "";
- fieldname = obsavestring (anon_name, strlen (anon_name),
- &objfile->type_obstack);
- }
- }
+ /* Get name of member function. */
+ attr = dwarf_attr (die, DW_AT_name);
+ if (attr && DW_STRING (attr))
+ fieldname = DW_STRING (attr);
else
- {
- char *endname = skip_member_fn_name (physname);
+ return;
- /* Ignore member function if we were unable not extract the member
- function name. */
- if (endname == physname)
- return;
- fieldname = obsavestring (physname, endname - physname,
- &objfile->type_obstack);
- }
+ /* Get the mangled name. */
+ physname = dwarf2_linkage_name (die);
/* Look up member function name in fieldlist. */
for (i = 0; i < fip->nfnfields; i++)
to make a symbol table entry for it, and if so, create a new entry
and return a pointer to it.
If TYPE is NULL, determine symbol type from the die, otherwise
- used the passed type.
- */
+ used the passed type. */
static struct symbol *
new_symbol (die, type, objfile)
memcpy (SYMBOL_VALUE_BYTES (sym), blk->data, blk->size);
SYMBOL_CLASS (sym) = LOC_CONST_BYTES;
break;
+
+ /* The DW_AT_const_value attributes are supposed to carry the
+ symbol's value "represented as it would be on the target
+ architecture." By the time we get here, it's already been
+ converted to host endianness, so we just need to sign- or
+ zero-extend it as appropriate. */
+ case DW_FORM_data1:
+ dwarf2_const_value_data (attr, sym, 8);
+ break;
case DW_FORM_data2:
+ dwarf2_const_value_data (attr, sym, 16);
+ break;
case DW_FORM_data4:
+ dwarf2_const_value_data (attr, sym, 32);
+ break;
case DW_FORM_data8:
- case DW_FORM_data1:
+ dwarf2_const_value_data (attr, sym, 64);
+ break;
+
case DW_FORM_sdata:
+ SYMBOL_VALUE (sym) = DW_SND (attr);
+ SYMBOL_CLASS (sym) = LOC_CONST;
+ break;
+
case DW_FORM_udata:
SYMBOL_VALUE (sym) = DW_UNSND (attr);
SYMBOL_CLASS (sym) = LOC_CONST;
break;
+
default:
complain (&dwarf2_unsupported_const_value_attr,
dwarf_form_name (attr->form));
}
}
+
+/* Given an attr with a DW_FORM_dataN value in host byte order, sign-
+ or zero-extend it as appropriate for the symbol's type. */
+static void
+dwarf2_const_value_data (struct attribute *attr,
+ struct symbol *sym,
+ int bits)
+{
+ LONGEST l = DW_UNSND (attr);
+
+ if (bits < sizeof (l) * 8)
+ {
+ if (TYPE_UNSIGNED (SYMBOL_TYPE (sym)))
+ l &= ((LONGEST) 1 << bits) - 1;
+ else
+ l = (l << (sizeof (l) - bits)) >> (sizeof (l) - bits);
+ }
+
+ SYMBOL_VALUE (sym) = l;
+ SYMBOL_CLASS (sym) = LOC_CONST;
+}
+
+
/* Return the type of the die in question using its DW_AT_type attribute. */
static struct type *
objfile->ei.entry_func_lowpc = dip->at_low_pc;
objfile->ei.entry_func_highpc = dip->at_high_pc;
}
- if (STREQ (dip->at_name, "main")) /* FIXME: hardwired name */
- {
- objfile->ei.main_func_lowpc = dip->at_low_pc;
- objfile->ei.main_func_highpc = dip->at_high_pc;
- }
new = push_context (0, dip->at_low_pc);
new->name = new_symbol (dip, objfile);
list_in_scope = &local_symbols;
default:
/* Removing this case and compiling with gcc -Wall reveals that
a lot of cases are hitting this case. Some of these should
- probably be removed from expression.h (e.g. do we need a BINOP_SCOPE
- and an OP_SCOPE?); others are legitimate expressions which are
- (apparently) not fully implemented.
+ probably be removed from expression.h; others are legitimate
+ expressions which are (apparently) not fully implemented.
If there are any cases landing here which mean a user error,
then they should be separate cases, with more descriptive
return "BINOP_MIN";
case BINOP_MAX:
return "BINOP_MAX";
- case BINOP_SCOPE:
- return "BINOP_SCOPE";
case STRUCTOP_MEMBER:
return "STRUCTOP_MEMBER";
case STRUCTOP_MPTR:
case BINOP_EXP:
case BINOP_MIN:
case BINOP_MAX:
- case BINOP_SCOPE:
case BINOP_INTDIV:
case BINOP_ASSIGN_MODIFY:
case BINOP_VAL:
BINOP_MIN, /* <? */
BINOP_MAX, /* >? */
- BINOP_SCOPE, /* :: */
/* STRUCTOP_MEMBER is used for pointer-to-member constructs.
X . * Y translates into X STRUCTOP_MEMBER Y. */
Copyright (C) 1993, 94, 95, 96, 97, 98 Free Software Foundation, Inc.
NOTE: The canonical source of this file is maintained with the
- GNU C Library. Bugs can be reported to bug-glibc@prep.ai.mit.edu.
+ GNU C Library. Bugs can be reported to bug-glibc@gnu.org.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Copyright (C) 1985,89,90,91,92,93,95,96,97,98 Free Software Foundation, Inc.
NOTE: The canonical source of this file is maintained with the
- GNU C Library. Bugs can be reported to bug-glibc@prep.ai.mit.edu.
+ GNU C Library. Bugs can be reported to bug-glibc@gnu.org.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
#include "event-loop.h"
#include "event-top.h"
#include "inf-loop.h"
+#include "remote.h"
static int fetch_inferior_event_wrapper (gdb_client_data client_data);
static void complete_execution (void);
+void
+inferior_event_handler_wrapper (gdb_client_data client_data)
+{
+ inferior_event_handler (INF_QUIT_REQ, client_data);
+}
+
/* General function to handle events in the inferior. So far it just
takes care of detecting errors reported by select() or poll(),
otherwise it assumes that all is OK, and goes on reading data from
complete_execution ();
break;
- case INF_QUIT_REQ:
+ case INF_QUIT_REQ:
+ /* FIXME: ezannoni 1999-10-04. This call should really be a
+ target vector entry, so that it can be used for any kind of
+ targets. */
+ async_remote_interrupt_twice (NULL);
+ break;
+
case INF_TIMER:
default:
printf_unfiltered ("Event type not recognized.\n");
extern void inferior_event_handler (enum inferior_event_type event_type,
void* client_data);
+extern void inferior_event_handler_wrapper (void *client_data);
#endif /* #ifndef INF_LOOP_H */
section_addrs.text_addr = text_addr;
so->objfile = symbol_file_add (so->so_name, so->from_tty,
- §ion_addrs,
- 0, 0, 0, 0);
+ §ion_addrs, 0, 0);
return (1);
}
{
if (dynamics_objfile == NULL)
{
- dynamics_objfile = allocate_objfile (NULL, 0, 0, 0);
+ dynamics_objfile = allocate_objfile (NULL, 0);
}
return dynamics_objfile;
}
fputs_unfiltered ("\n\
For more information, type \"help\" from within GDB, or consult the\n\
GDB manual (available as on-line info or a printed manual).\n\
-Report bugs to \"bug-gdb@prep.ai.mit.edu\".\
+Report bugs to \"bug-gdb@gnu.org\".\
", stream);
}
static void monitor_fetch_register PARAMS ((int regno));
static void monitor_store_register PARAMS ((int regno));
-static int monitor_printable_string PARAMS ((char *newstr, char *oldstr));
-static void monitor_error PARAMS ((char *format, CORE_ADDR memaddr, int len, char *string, int final_char));
+static void monitor_printable_string (char *newstr, char *oldstr, int len);
+static void monitor_error (char *function, char *message, CORE_ADDR memaddr, int len, char *string, int final_char);
static void monitor_detach PARAMS ((char *args, int from_tty));
static void monitor_resume PARAMS ((int pid, int step, enum target_signal sig));
static void monitor_interrupt PARAMS ((int signo));
static CORE_ADDR *breakaddr;
-/* Extra remote debugging for developing a new rom monitor variation */
-#if ! defined(EXTRA_RDEBUG)
-#define EXTRA_RDEBUG 0
-#endif
-#define RDEBUG(stuff) { if (EXTRA_RDEBUG && remote_debug) printf stuff ; }
-
/* Descriptor for I/O to remote machine. Initialize it to NULL so
that monitor_open knows that we don't have a file open when the
program starts. */
#define TARGET_BUF_SIZE 2048
-/* Convert a string into a printable representation, Return # byte in the
- new string. */
+/* Monitor specific debugging information. Typically only useful to
+ the developer of a new monitor interface. */
-static int
-monitor_printable_string (newstr, oldstr)
- char *newstr;
- char *oldstr;
+static void monitor_debug (const char *fmt, ...) ATTR_FORMAT(printf, 1, 2);
+
+static int monitor_debug_p = 0;
+
+/* NOTE: This file alternates between monitor_debug_p and remote_debug
+ when determining if debug information is printed. Perhaphs this
+ could be simplified. */
+
+static void
+monitor_debug (const char *fmt, ...)
+{
+ if (monitor_debug_p)
+ {
+ va_list args;
+ va_start (args, fmt);
+ vfprintf_filtered (gdb_stdlog, fmt, args);
+ va_end (args);
+ }
+}
+
+
+/* Convert a string into a printable representation, Return # byte in
+ the new string. When LEN is >0 it specifies the size of the
+ string. Otherwize strlen(oldstr) is used. */
+
+static void
+monitor_printable_string (char *newstr, char *oldstr, int len)
{
- char *save = newstr;
int ch;
+ int i;
+
+ if (len <= 0)
+ len = strlen (oldstr);
- while ((ch = *oldstr++) != '\0')
+ for (i = 0; i < len; i++)
{
+ ch = oldstr[i];
switch (ch)
{
default:
}
*newstr++ = '\0';
- return newstr - save;
}
/* Print monitor errors with a string, converting the string to printable
representation. */
static void
-monitor_error (format, memaddr, len, string, final_char)
- char *format;
- CORE_ADDR memaddr;
- int len;
- char *string;
- int final_char;
+monitor_error (char *function, char *message,
+ CORE_ADDR memaddr, int len, char *string, int final_char)
{
int real_len = (len == 0 && string != (char *) 0) ? strlen (string) : len;
char *safe_string = alloca ((real_len * 4) + 1);
- char *p;
- int safe_len = monitor_printable_string (safe_string, string);
+ monitor_printable_string (safe_string, string, real_len);
if (final_char)
- error (format, (int) memaddr, p - safe_string, safe_string, final_char);
+ error ("%s (0x%s): %s: %s%c", function, paddr_nz (memaddr), message, safe_string, final_char);
else
- error (format, (int) memaddr, p - safe_string, safe_string);
+ error ("%s (0x%s): %s: %s", function, paddr_nz (memaddr), message, safe_string);
}
/* Convert hex digit A to a number. */
if (len + 1 > sizeof sndbuf)
abort ();
-#if 0
- if (remote_debug > 0)
- puts_debug ("sent -->", sndbuf, "<--");
-#endif
- if (EXTRA_RDEBUG
- && remote_debug)
+ if (monitor_debug_p)
{
char *safe_string = (char *) alloca ((strlen (sndbuf) * 4) + 1);
- monitor_printable_string (safe_string, sndbuf);
- printf ("sent[%s]\n", safe_string);
+ monitor_printable_string (safe_string, sndbuf, 0);
+ fprintf_unfiltered (gdb_stdlog, "sent[%s]\n", safe_string);
}
monitor_write (sndbuf, len);
if (len + 1 > sizeof sndbuf)
abort ();
-#if 0
- if (remote_debug > 0)
- puts_debug ("sent -->", sndbuf, "<--");
-#endif
- if (EXTRA_RDEBUG
- && remote_debug)
+ if (monitor_debug_p)
{
char *safe_string = (char *) alloca ((len * 4) + 1);
- monitor_printable_string (safe_string, sndbuf);
- printf ("sent[%s]\n", safe_string);
+ monitor_printable_string (safe_string, sndbuf, 0);
+ fprintf_unfiltered (gdb_stdlog, "sent[%s]\n", safe_string);
}
monitor_write (sndbuf, len);
just output, but sometimes some extra junk appeared before the characters
we expected, like an extra prompt, or a portmaster sending telnet negotiations.
So, just start searching for what we sent, and skip anything unknown. */
- RDEBUG (("ExpectEcho\n"))
- monitor_expect (sndbuf, (char *) 0, 0);
+ monitor_debug ("ExpectEcho\n");
+ monitor_expect (sndbuf, (char *) 0, 0);
}
c &= 0x7f;
/* This seems to interfere with proper function of the
input stream */
- if (remote_debug > 0)
+ if (monitor_debug_p || remote_debug)
{
char buf[2];
buf[0] = c;
int c;
extern struct target_ops *targ_ops;
- if (EXTRA_RDEBUG
- && remote_debug)
+ if (monitor_debug_p)
{
char *safe_string = (char *) alloca ((strlen (string) * 4) + 1);
- monitor_printable_string (safe_string, string);
- printf ("MON Expecting '%s'\n", safe_string);
+ monitor_printable_string (safe_string, string, 0);
+ fprintf_unfiltered (gdb_stdlog, "MON Expecting '%s'\n", safe_string);
}
immediate_quit = 1;
{
char *mybuf;
char *p;
- RDEBUG (("MON Expecting regexp\n"));
+ monitor_debug ("MON Expecting regexp\n");
if (buf)
mybuf = buf;
else
char *buf;
int buflen;
{
- RDEBUG (("MON Expecting prompt\n"))
- return monitor_expect (current_monitor->prompt, buf, buflen);
+ monitor_debug ("MON Expecting prompt\n");
+ return monitor_expect (current_monitor->prompt, buf, buflen);
}
/* Get N 32-bit words from remote, each preceded by a space, and put
monitor_stop ();
if ((current_monitor->flags & MO_NO_ECHO_ON_OPEN) == 0)
{
- RDEBUG (("EXP Open echo\n"));
+ monitor_debug ("EXP Open echo\n");
monitor_expect_prompt (NULL, 0);
}
}
val <<= 4;
val += fromhex (*p++);
}
- RDEBUG (("Supplying Register %d %s\n", regno, valstr));
+ monitor_debug ("Supplying Register %d %s\n", regno, valstr);
if (*p != '\0')
error ("monitor_supply_register (%d): bad value from monitor: %s.",
enum target_signal sig;
{
/* Some monitors require a different command when starting a program */
- RDEBUG (("MON resume\n"));
+ monitor_debug ("MON resume\n");
if (current_monitor->flags & MO_RUN_FIRST_TIME && first_time == 1)
{
first_time = 0;
char *buf;
int len;
{
- RDEBUG (("MON Parsing register dump\n"))
- while (1)
+ monitor_debug ("MON Parsing register dump\n");
+ while (1)
{
int regnamelen, vallen;
char *regname, *val;
/* If this doesn't work, try more severe steps. */
signal (signo, monitor_interrupt_twice);
- if (remote_debug)
- printf_unfiltered ("monitor_interrupt called\n");
+ if (monitor_debug_p || remote_debug)
+ fprintf_unfiltered (gdb_stdlog, "monitor_interrupt called\n");
target_stop ();
}
/* Print any output characters that were preceded by ^O. */
/* FIXME - This would be great as a user settabgle flag */
- if (remote_debug ||
- current_monitor->flags & MO_PRINT_PROGRAM_OUTPUT)
+ if (monitor_debug_p || remote_debug
+ || current_monitor->flags & MO_PRINT_PROGRAM_OUTPUT)
{
int i;
status->value.integer = 0;
old_chain = make_cleanup (monitor_wait_cleanup, &old_timeout);
- RDEBUG (("MON wait\n"))
+ monitor_debug ("MON wait\n");
#if 0
/* This is somthing other than a maintenance command */
in_monitor_wait = 1;
timeout = watchdog > 0 ? watchdog : -1;
#else
- timeout = -1; /* Don't time out -- user program is running. */
+ timeout = -1; /* Don't time out -- user program is running. */
#endif
ofunc = (void (*)()) signal (SIGINT, monitor_interrupt);
/* Print any output characters that were preceded by ^O. */
/* FIXME - This would be great as a user settabgle flag */
- if (remote_debug ||
- current_monitor->flags & MO_PRINT_PROGRAM_OUTPUT)
+ if (monitor_debug_p || remote_debug
+ || current_monitor->flags & MO_PRINT_PROGRAM_OUTPUT)
{
int i;
if (current_monitor->register_pattern)
parse_register_dump (buf, resp_len);
#else
- RDEBUG (("Wait fetching registers after stop\n"));
+ monitor_debug ("Wait fetching registers after stop\n");
monitor_dump_regs ();
#endif
int i;
name = current_monitor->regnames[regno];
- RDEBUG (("MON fetchreg %d '%s'\n", regno, name ? name : "(null name)"))
+ monitor_debug ("MON fetchreg %d '%s'\n", regno, name ? name : "(null name)");
- if (!name || (*name == '\0'))
+ if (!name || (*name == '\0'))
{
- RDEBUG (("No register known for %d\n", regno))
- supply_register (regno, zerobuf);
+ monitor_debug ("No register known for %d\n", regno);
+ supply_register (regno, zerobuf);
return;
}
if (current_monitor->getreg.resp_delim)
{
- RDEBUG (("EXP getreg.resp_delim\n"))
- monitor_expect (current_monitor->getreg.resp_delim, NULL, 0);
+ monitor_debug ("EXP getreg.resp_delim\n");
+ monitor_expect (current_monitor->getreg.resp_delim, NULL, 0);
/* Handle case of first 32 registers listed in pairs. */
if (current_monitor->flags & MO_32_REGS_PAIRED
&& (regno & 1) != 0 && regno < 32)
{
- RDEBUG (("EXP getreg.resp_delim\n"));
+ monitor_debug ("EXP getreg.resp_delim\n");
monitor_expect (current_monitor->getreg.resp_delim, NULL, 0);
}
}
}
regbuf[i] = '\000'; /* terminate the number */
- RDEBUG (("REGVAL '%s'\n", regbuf));
+ monitor_debug ("REGVAL '%s'\n", regbuf);
/* If TERM is present, we wait for that to show up. Also, (if TERM
is present), we will send TERM_CMD if that is present. In any
if (current_monitor->getreg.term)
{
- RDEBUG (("EXP getreg.term\n"))
- monitor_expect (current_monitor->getreg.term, NULL, 0); /* get response */
+ monitor_debug ("EXP getreg.term\n");
+ monitor_expect (current_monitor->getreg.term, NULL, 0); /* get response */
}
if (current_monitor->getreg.term_cmd)
{
- RDEBUG (("EMIT getreg.term.cmd\n"))
- monitor_printf (current_monitor->getreg.term_cmd);
+ monitor_debug ("EMIT getreg.term.cmd\n");
+ monitor_printf (current_monitor->getreg.term_cmd);
}
if (!current_monitor->getreg.term || /* Already expected or */
current_monitor->getreg.term_cmd) /* ack expected */
monitor_fetch_registers (regno)
int regno;
{
- RDEBUG (("MON fetchregs\n"));
+ monitor_debug ("MON fetchregs\n");
if (current_monitor->getreg.cmd)
{
if (regno >= 0)
name = current_monitor->regnames[regno];
if (!name || (*name == '\0'))
{
- RDEBUG (("MON Cannot store unknown register\n"))
- return;
+ monitor_debug ("MON Cannot store unknown register\n");
+ return;
}
val = read_register (regno);
- RDEBUG (("MON storeg %d %08lx\n", regno, (ULONGEST) val))
+ monitor_debug ("MON storeg %d %s\n", regno, preg (val));
/* send the register deposit command */
- if (current_monitor->flags & MO_REGISTER_VALUE_FIRST)
+ if (current_monitor->flags & MO_REGISTER_VALUE_FIRST)
monitor_printf (current_monitor->setreg.cmd, val, name);
else if (current_monitor->flags & MO_SETREG_INTERACTIVE)
monitor_printf (current_monitor->setreg.cmd, name);
if (current_monitor->setreg.term)
{
- RDEBUG (("EXP setreg.term\n"))
- monitor_expect (current_monitor->setreg.term, NULL, 0);
+ monitor_debug ("EXP setreg.term\n");
+ monitor_expect (current_monitor->setreg.term, NULL, 0);
if (current_monitor->flags & MO_SETREG_INTERACTIVE)
- monitor_printf ("%A\r", val);
+ monitor_printf ("%s\r", paddr_nz (val));
monitor_expect_prompt (NULL, 0);
}
else
monitor_expect_prompt (NULL, 0);
if (current_monitor->setreg.term_cmd) /* Mode exit required */
{
- RDEBUG (("EXP setreg_termcmd\n"));
+ monitor_debug ("EXP setreg_termcmd\n");
monitor_printf ("%s", current_monitor->setreg.term_cmd);
monitor_expect_prompt (NULL, 0);
}
char *cmd;
int i;
- RDEBUG (("MON write %d %08x\n", len, (unsigned long) memaddr))
+ monitor_debug ("MON write %d %s\n", len, paddr (memaddr));
- if (current_monitor->flags & MO_ADDR_BITS_REMOVE)
+ if (current_monitor->flags & MO_ADDR_BITS_REMOVE)
memaddr = ADDR_BITS_REMOVE (memaddr);
/* Use memory fill command for leading 0 bytes. */
if (i > 4) /* More than 4 zeros is worth doing */
{
- RDEBUG (("MON FILL %d\n", i))
- if (current_monitor->flags & MO_FILL_USES_ADDR)
+ monitor_debug ("MON FILL %d\n", i);
+ if (current_monitor->flags & MO_FILL_USES_ADDR)
monitor_printf (current_monitor->fill, memaddr, (memaddr + i) - 1, 0);
else
monitor_printf (current_monitor->fill, memaddr, i, 0);
if (len == 4)
{
hostval = *(unsigned int *) myaddr;
- RDEBUG (("Hostval(%08x) val(%08x)\n", hostval, val));
+ monitor_debug ("Hostval(%08x) val(%08x)\n", hostval, val);
}
if (current_monitor->setmem.term)
{
- RDEBUG (("EXP setmem.term"));
+ monitor_debug ("EXP setmem.term");
monitor_expect (current_monitor->setmem.term, NULL, 0);
monitor_printf ("%x\r", val);
}
myaddr += 4;
memaddr += 4;
written += 4;
- RDEBUG ((" @ %08x\n", memaddr))
+ monitor_debug (" @ %s\n", paddr (memaddr));
/* If we wanted to, here we could validate the address */
- monitor_expect_prompt (NULL, 0);
+ monitor_expect_prompt (NULL, 0);
}
/* Now exit the sub mode */
monitor_printf (current_monitor->getreg.term_cmd);
char *cmd;
int i;
- RDEBUG (("MON read single\n"));
+ monitor_debug ("MON read single\n");
#if 0
/* Can't actually use long longs (nice idea, though). In fact, the
call to strtoul below will fail if it tries to convert a value
if (current_monitor->getmem.resp_delim)
{
- RDEBUG (("EXP getmem.resp_delim\n"));
+ monitor_debug ("EXP getmem.resp_delim\n");
monitor_expect_regexp (&getmem_resp_delim_pattern, NULL, 0);
}
if ((c == '0') && ((c = readchar (timeout)) == 'x'))
;
else
- monitor_error ("monitor_read_memory_single (0x%x): bad response from monitor: %.*s%c.",
+ monitor_error ("monitor_read_memory_single",
+ "bad response from monitor",
memaddr, i, membuf, c);
}
for (i = 0; i < len * 2; i++)
if (c == ' ')
continue;
- monitor_error ("monitor_read_memory_single (0x%x): bad response from monitor: %.*s%c.",
+ monitor_error ("monitor_read_memory_single",
+ "bad response from monitor",
memaddr, i, membuf, c);
}
val = strtoul (membuf, &p, 16);
if (val == 0 && membuf == p)
- monitor_error ("monitor_read_memory_single (0x%x): bad value from monitor: %s.",
+ monitor_error ("monitor_read_memory_single",
+ "bad value from monitor",
memaddr, 0, membuf, 0);
/* supply register stores in target byte order, so swap here */
if (len <= 0)
{
- RDEBUG (("Zero length call to monitor_read_memory\n"));
+ monitor_debug ("Zero length call to monitor_read_memory\n");
return 0;
}
- if (remote_debug)
- printf ("MON read block ta(%08x) ha(%08x) %d\n",
- (unsigned long) memaddr, (unsigned long) myaddr, len);
+ monitor_debug ("MON read block ta(%s) ha(%lx) %d\n",
+ paddr_nz (memaddr), (long) myaddr, len);
if (current_monitor->flags & MO_ADDR_BITS_REMOVE)
memaddr = ADDR_BITS_REMOVE (memaddr);
resp_len = monitor_expect (current_monitor->getmem.term, buf, sizeof buf); /* get response */
if (resp_len <= 0)
- monitor_error ("monitor_read_memory (0x%x): excessive response from monitor: %.*s.",
+ monitor_error ("monitor_read_memory",
+ "excessive response from monitor",
memaddr, resp_len, buf, 0);
if (current_monitor->getmem.term_cmd)
{
int retval, tmp;
struct re_registers resp_strings;
- RDEBUG (("MON getmem.resp_delim %s\n", current_monitor->getmem.resp_delim));
+ monitor_debug ("MON getmem.resp_delim %s\n", current_monitor->getmem.resp_delim);
memset (&resp_strings, 0, sizeof (struct re_registers));
tmp = strlen (p);
&resp_strings);
if (retval < 0)
- monitor_error ("monitor_read_memory (0x%x): bad response from monitor: %.*s.",
+ monitor_error ("monitor_read_memory",
+ "bad response from monitor",
memaddr, resp_len, buf, 0);
p += resp_strings.end[0];
#if 0
p = strstr (p, current_monitor->getmem.resp_delim);
if (!p)
- monitor_error ("monitor_read_memory (0x%x): bad response from monitor: %.*s.",
+ monitor_error ("monitor_read_memory",
+ "bad response from monitor",
memaddr, resp_len, buf, 0);
p += strlen (current_monitor->getmem.resp_delim);
#endif
}
- if (remote_debug)
- printf ("MON scanning %d ,%08x '%s'\n", len, p, p);
+ monitor_debug ("MON scanning %d ,%lx '%s'\n", len, (long) p, p);
if (current_monitor->flags & MO_GETMEM_16_BOUNDARY)
{
char c;
{
val = fromhex (c) * 16 + fromhex (*(p + 1));
*myaddr++ = val;
- if (remote_debug)
- printf ("[%02x]", val);
+ if (monitor_debug_p || remote_debug)
+ fprintf_unfiltered (gdb_stdlog, "[%02x]", val);
--i;
fetched++;
}
}
if (fetched == 0)
error ("Failed to read via monitor");
- if (remote_debug)
- printf ("\n");
+ if (monitor_debug_p || remote_debug)
+ fprintf_unfiltered (gdb_stdlog, "\n");
return fetched; /* Return the number of bytes actually read */
}
- RDEBUG (("MON scanning bytes\n"));
+ monitor_debug ("MON scanning bytes\n");
for (i = len; i > 0; i--)
{
break;
if (*p == '\000' || *p == '\n' || *p == '\r')
- monitor_error ("monitor_read_memory (0x%x): badly terminated response from monitor: %.*s",
+ monitor_error ("monitor_read_memory",
+ "badly terminated response from monitor",
memaddr, resp_len, buf, 0);
p++;
}
val = strtoul (p, &p1, 16);
if (val == 0 && p == p1)
- monitor_error ("monitor_read_memory (0x%x): bad value from monitor: %.*s.",
+ monitor_error ("monitor_read_memory",
+ "bad value from monitor",
memaddr, resp_len, buf, 0);
*myaddr++ = val;
unsigned char *bp;
int bplen;
- RDEBUG (("MON inst bkpt %08x\n", addr))
- if (current_monitor->set_break == NULL)
+ monitor_debug ("MON inst bkpt %s\n", paddr (addr));
+ if (current_monitor->set_break == NULL)
error ("No set_break defined for this monitor");
if (current_monitor->flags & MO_ADDR_BITS_REMOVE)
{
int i;
- RDEBUG (("MON rmbkpt %08x\n", addr))
- if (current_monitor->clr_break == NULL)
+ monitor_debug ("MON rmbkpt %s\n", paddr (addr));
+ if (current_monitor->clr_break == NULL)
error ("No clr_break defined for this monitor");
if (current_monitor->flags & MO_ADDR_BITS_REMOVE)
}
}
fprintf_unfiltered (gdb_stderr,
- "Can't find breakpoint associated with 0x%x\n", addr);
+ "Can't find breakpoint associated with 0x%s\n",
+ paddr_nz (addr));
return 1;
}
int from_tty;
{
dcache_flush (remote_dcache);
- RDEBUG (("MON load\n"))
+ monitor_debug ("MON load\n");
- if (current_monitor->load_routine)
+ if (current_monitor->load_routine)
current_monitor->load_routine (monitor_desc, file, hashmark);
else
{ /* The default is ascii S-records */
static void
monitor_stop ()
{
- RDEBUG (("MON stop\n"));
+ monitor_debug ("MON stop\n");
if ((current_monitor->flags & MO_SEND_BREAK_ON_STOP) != 0)
SERIAL_SEND_BREAK (monitor_desc);
if (current_monitor->stop)
When enabled, a hashmark \'#\' is displayed.",
&setlist),
&showlist);
+
+#if 0
+ /* FIXME: cagney/1999-10-07: Wait until there is a generic ``set
+ debug ...'' rather than another ``set ...debug'' command. */
+ add_show_from_set
+ (add_set_cmd ("monitordebug", no_class, var_zinteger,
+ (char *) &monitor_debug_p,
+ "Set debugging of remote monitor communication.\n\
+When enabled, communication between GDB and the remote monitor\n\
+is displayed.", &setlist),
+ &showlist);
+#endif
}
open_existing_mapped_file PARAMS ((char *, long, int));
static int
-open_mapped_file PARAMS ((char *filename, long mtime, int mapped));
+open_mapped_file PARAMS ((char *filename, long mtime, int flags));
static PTR
map_to_file PARAMS ((int));
return (0);
}
-/* Given a pointer to an initialized bfd (ABFD) and a flag that indicates
- whether or not an objfile is to be mapped (MAPPED), allocate a new objfile
- struct, fill it in as best we can, link it into the list of all known
- objfiles, and return a pointer to the new objfile struct.
+/* Given a pointer to an initialized bfd (ABFD) and some flag bits
+ allocate a new objfile struct, fill it in as best we can, link it
+ into the list of all known objfiles, and return a pointer to the
+ new objfile struct.
- USER_LOADED is simply recorded in the objfile. This record offers a way for
- run_command to remove old objfile entries which are no longer valid (i.e.,
- are associated with an old inferior), but to preserve ones that the user
- explicitly loaded via the add-symbol-file command.
-
- IS_SOLIB is also simply recorded in the objfile. */
+ The FLAGS word contains various bits (OBJF_*) that can be taken as
+ requests for specific operations, like trying to open a mapped
+ version of the objfile (OBJF_MAPPED). Other bits like
+ OBJF_SHARED are simply copied through to the new objfile flags
+ member. */
struct objfile *
-allocate_objfile (abfd, mapped, user_loaded, is_solib)
+allocate_objfile (abfd, flags)
bfd *abfd;
- int mapped;
- int user_loaded;
- int is_solib;
+ int flags;
{
struct objfile *objfile = NULL;
struct objfile *last_one = NULL;
- mapped |= mapped_symbol_files;
+ if (mapped_symbol_files)
+ flags |= OBJF_MAPPED;
#if defined(USE_MMALLOC) && defined(HAVE_MMAP)
if (abfd != NULL)
int fd;
fd = open_mapped_file (bfd_get_filename (abfd), bfd_get_mtime (abfd),
- mapped);
+ flags);
if (fd >= 0)
{
PTR md;
}
}
- if (mapped && (objfile == NULL))
+ if ((flags & OBJF_MAPPED) && (objfile == NULL))
{
warning ("symbol table for '%s' will not be mapped",
bfd_get_filename (abfd));
+ flags &= ~OBJF_MAPPED;
}
}
#else /* !defined(USE_MMALLOC) || !defined(HAVE_MMAP) */
- if (mapped)
+ if (flags & OBJF_MAPPED)
{
warning ("mapped symbol tables are not supported on this machine; missing or broken mmap().");
"mapped" keyword again. */
mapped_symbol_files = 0;
+ flags &= ~OBJF_MAPPED;
}
#endif /* defined(USE_MMALLOC) && defined(HAVE_MMAP) */
free);
obstack_specify_allocation (&objfile->type_obstack, 0, 0, xmalloc,
free);
+ flags &= ~OBJF_MAPPED;
}
/* Update the per-objfile information that comes from the bfd, ensuring
last_one->next = objfile;
}
- /* Record whether this objfile was created because the user explicitly
- caused it (e.g., used the add-symbol-file command).
- */
- objfile->user_loaded = user_loaded;
-
- /* Record whether this objfile definitely represents a solib. */
- objfile->is_solib = is_solib;
+ /* Save passed in flag bits. */
+ objfile->flags |= flags;
return (objfile);
}
/* We assume that the solib package has been purged already, or will
be soon.
*/
- if (!objf->user_loaded && objf->is_solib)
+ if (!(objf->flags & OBJF_USERLOADED) && (objf->flags & OBJF_SHARED))
free_objfile (objf);
}
}
Otherwise, returns the open file descriptor. */
static int
-open_existing_mapped_file (symsfilename, mtime, mapped)
+open_existing_mapped_file (symsfilename, mtime, flags)
char *symsfilename;
long mtime;
- int mapped;
+ int flags;
{
int fd = -1;
struct stat sbuf;
{
if (sbuf.st_mtime < mtime)
{
- if (!mapped)
+ if (!(flags & OBJF_MAPPED))
{
warning ("mapped symbol file `%s' is out of date, ignored it",
symsfilename);
/bin for example). */
static int
-open_mapped_file (filename, mtime, mapped)
+open_mapped_file (filename, mtime, flags)
char *filename;
long mtime;
- int mapped;
+ int flags;
{
int fd;
char *symsfilename;
then try the directory where the symbol file is located. */
symsfilename = concat ("./", basename (filename), ".syms", (char *) NULL);
- if ((fd = open_existing_mapped_file (symsfilename, mtime, mapped)) < 0)
+ if ((fd = open_existing_mapped_file (symsfilename, mtime, flags)) < 0)
{
free (symsfilename);
symsfilename = concat (filename, ".syms", (char *) NULL);
char *name;
- /* TRUE if this objfile was created because the user explicitly caused
- it (e.g., used the add-symbol-file command).
- */
- int user_loaded;
-
- /* TRUE if this objfile was explicitly created to represent a solib.
-
- (If FALSE, the objfile may actually be a solib. This can happen if
- the user created the objfile by using the add-symbol-file command.
- GDB doesn't in that situation actually check whether the file is a
- solib. Rather, the target's implementation of the solib interface
- is responsible for setting this flag when noticing solibs used by
- an inferior.)
- */
- int is_solib;
-
/* Some flag bits for this objfile. */
unsigned short flags;
#define OBJF_REORDERED (1 << 2) /* Functions are reordered */
-/* Distinguish between an objfile for a shared library and a
- "vanilla" objfile. */
+/* Distinguish between an objfile for a shared library and a "vanilla"
+ objfile. (If not set, the objfile may still actually be a solib.
+ This can happen if the user created the objfile by using the
+ add-symbol-file command. GDB doesn't in that situation actually
+ check whether the file is a solib. Rather, the target's
+ implementation of the solib interface is responsible for setting
+ this flag when noticing solibs used by an inferior.) */
#define OBJF_SHARED (1 << 3) /* From a shared library */
#define OBJF_READNOW (1 << 4) /* Immediate full read */
+/* This objfile was created because the user explicitly caused it
+ (e.g., used the add-symbol-file command). This bit offers a way
+ for run_command to remove old objfile entries which are no longer
+ valid (i.e., are associated with an old inferior), but to preserve
+ ones that the user explicitly loaded via the add-symbol-file
+ command. */
+
+#define OBJF_USERLOADED (1 << 5) /* User loaded */
+
/* The object file that the main symbol table was loaded from (e.g. the
argument to the "symbol-file" or "file" command). */
/* Declarations for functions defined in objfiles.c */
extern struct objfile *
- allocate_objfile PARAMS ((bfd *, int, int, int));
+allocate_objfile PARAMS ((bfd *, int));
extern int
build_objfile_section_table PARAMS ((struct objfile *));
section_addrs.text_addr = text_addr;
so->objfile = symbol_file_add (so->so_name, so->from_tty,
- §ion_addrs,
- 0, 0, 0, 1);
+ §ion_addrs, 0, OBJF_SHARED);
return (1);
}
/* Now let the generic code load up symbols for this library. */
section_addrs.text_addr = text_addr;
- so->objfile = symbol_file_add (name, from_tty, §ion_addrs, 0, 0, 0, 1);
+ so->objfile = symbol_file_add (name, from_tty, §ion_addrs, 0, OBJF_SHARED);
so->abfd = so->objfile->obfd;
/* Mark this as a shared library and save private data. */
#include "parser-defs.h"
#include "gdbcmd.h"
#include "symfile.h" /* for overlay functions */
+\f
+/* Symbols which architectures can redefine. */
+
+/* Some systems have routines whose names start with `$'. Giving this
+ macro a non-zero value tells GDB's expression parser to check for
+ such routines when parsing tokens that begin with `$'.
+
+ On HP-UX, certain system routines (millicode) have names beginning
+ with `$' or `$$'. For example, `$$dyncall' is a millicode routine
+ that handles inter-space procedure calls on PA-RISC. */
+#ifndef SYMBOLS_CAN_START_WITH_DOLLAR
+#define SYMBOLS_CAN_START_WITH_DOLLAR (0)
+#endif
+
+
\f
/* Global variables declared in parser-defs.h (and commented there). */
struct expression *expout;
/* Handle the tokens $digits; also $ (short for $0) and $$ (short for $$1)
and $$digits (equivalent to $<-digits> if you could type that). */
- struct symbol *sym = NULL;
- struct minimal_symbol *msym = NULL;
-
int negate = 0;
int i = 1;
/* Double dollar means negate the number and add -1 as well.
if (i >= 0)
goto handle_register;
- /* On HP-UX, certain system routines (millicode) have names beginning
- with $ or $$, e.g. $$dyncall, which handles inter-space procedure
- calls on PA-RISC. Check for those, first. */
-
- sym = lookup_symbol (copy_name (str), (struct block *) NULL,
- VAR_NAMESPACE, (int *) NULL, (struct symtab **) NULL);
- if (sym)
+ if (SYMBOLS_CAN_START_WITH_DOLLAR)
{
- write_exp_elt_opcode (OP_VAR_VALUE);
- write_exp_elt_block (block_found); /* set by lookup_symbol */
- write_exp_elt_sym (sym);
- write_exp_elt_opcode (OP_VAR_VALUE);
- return;
- }
- msym = lookup_minimal_symbol (copy_name (str), NULL, NULL);
- if (msym)
- {
- write_exp_msymbol (msym,
- lookup_function_type (builtin_type_int),
- builtin_type_int);
- return;
+ struct symbol *sym = NULL;
+ struct minimal_symbol *msym = NULL;
+
+ /* On HP-UX, certain system routines (millicode) have names beginning
+ with $ or $$, e.g. $$dyncall, which handles inter-space procedure
+ calls on PA-RISC. Check for those, first. */
+
+ /* This code is not enabled on non HP-UX systems, since worst case
+ symbol table lookup performance is awful, to put it mildly. */
+
+ sym = lookup_symbol (copy_name (str), (struct block *) NULL,
+ VAR_NAMESPACE, (int *) NULL, (struct symtab **) NULL);
+ if (sym)
+ {
+ write_exp_elt_opcode (OP_VAR_VALUE);
+ write_exp_elt_block (block_found); /* set by lookup_symbol */
+ write_exp_elt_sym (sym);
+ write_exp_elt_opcode (OP_VAR_VALUE);
+ return;
+ }
+ msym = lookup_minimal_symbol (copy_name (str), NULL, NULL);
+ if (msym)
+ {
+ write_exp_msymbol (msym,
+ lookup_function_type (builtin_type_int),
+ builtin_type_int);
+ return;
+ }
}
/* Any other names starting in $ are debugger internal variables. */
/* You may need to do an init_target_mm() */
/* init_target_mm(?,?,?,?,?,?,?,?); */
immediate_quit--;
- /* symbol_file_add (arg_string, from_tty, text_addr, 0, 0, 0, 0); */
+ /* symbol_file_add (arg_string, from_tty, text_addr, 0, 0); */
#endif
}
/* As a convenience, pick up any symbol info that is in the program
being loaded. Note that we assume that the program is the``mainline'';
if this is not always true, then this code will need to be augmented. */
- symbol_file_add (strtok (args, " \t"), from_tty, NULL, 1, 0, 0, 0);
+ symbol_file_add (strtok (args, " \t"), from_tty, NULL, 1, 0);
/* Getting new symbols may change our opinion about what is
frameless. */
/* It might be nice to suppress the breakpoint_re_set which happens here
because we are going to do one again after the objfile_relocate. */
- objfile = symbol_file_add (name, from_tty, NULL, 0, 0, 0, 0);
+ objfile = symbol_file_add (name, from_tty, NULL, 0, 0);
/* This is a (slightly cheesy) way of superceding the old symbols. A less
cheesy way would be to find the objfile with the same name and
static void handle_remote_sigint PARAMS ((int));
static void handle_remote_sigint_twice PARAMS ((int));
static void async_remote_interrupt PARAMS ((gdb_client_data));
-static void async_remote_interrupt_twice PARAMS ((gdb_client_data));
+void async_remote_interrupt_twice PARAMS ((gdb_client_data));
static void build_remote_gdbarch_data PARAMS ((void));
static int hexnumstr PARAMS ((char *, ULONGEST));
+static int hexnumnstr PARAMS ((char *, ULONGEST, int));
+
static CORE_ADDR remote_address_masked PARAMS ((CORE_ADDR));
static void print_packet PARAMS ((char *));
{
signal (sig, handle_sigint);
sigint_remote_twice_token =
- create_async_signal_handler (async_remote_interrupt_twice, NULL);
+ create_async_signal_handler (inferior_event_handler_wrapper, NULL);
mark_async_signal_handler_wrapper (sigint_remote_twice_token);
}
/* Perform interrupt, if the first attempt did not succeed. Just give
up on the target alltogether. */
-static void
+void
async_remote_interrupt_twice (arg)
gdb_client_data arg;
{
+ if (remote_debug)
+ fprintf_unfiltered (gdb_stdlog, "remote_interrupt_twice called\n");
/* Do something only if the target was not killed by the previous
cntl-C. */
if (target_executing)
return max (i, 1);
}
-/* Set BUF to the hex digits representing NUM. */
+/* Set BUF to the minimum number of hex digits representing NUM. */
static int
hexnumstr (buf, num)
char *buf;
ULONGEST num;
{
- int i;
int len = hexnumlen (num);
+ return hexnumnstr (buf, num, len);
+}
- buf[len] = '\0';
- for (i = len - 1; i >= 0; i--)
+/* Set BUF to the hex digits representing NUM, padded to WIDTH characters. */
+
+static int
+hexnumnstr (buf, num, width)
+ char *buf;
+ ULONGEST num;
+ int width;
+{
+ int i;
+
+ buf[width] = '\0';
+
+ for (i = width - 1; i >= 0; i--)
{
buf[i] = "0123456789abcdef"[(num & 0xf)];
num >>= 4;
}
- return len;
+ return width;
}
/* Mask all but the least significant REMOTE_ADDRESS_SIZE bits. */
while (len > 0)
{
unsigned char *p, *plen;
+ int plenlen;
int todo;
int i;
*p++ = ',';
plen = p; /* remember where len field goes */
- p += hexnumstr (p, (ULONGEST) todo);
+ plenlen = hexnumstr (p, (ULONGEST) todo);
+ p += plenlen;
*p++ = ':';
*p = '\0';
{
/* Escape chars have filled up the buffer prematurely,
and we have actually sent fewer bytes than planned.
- Fix-up the length field of the packet. */
-
- /* FIXME: will fail if new len is a shorter string than
- old len. */
+ Fix-up the length field of the packet. Use the same
+ number of characters as before. */
- plen += hexnumstr (plen, (ULONGEST) i);
- *plen++ = ':';
+ plen += hexnumnstr (plen, (ULONGEST) i, plenlen);
+ *plen = ':'; /* overwrite \0 from hexnumnstr() */
}
break;
}
bfd_signed_vma data_off,
bfd_signed_vma bss_off);
+extern void async_remote_interrupt_twice (void *arg);
+
#endif
objname, bfd_errmsg (bfd_get_error ()));
/*NOTREACHED */
}
- obj = allocate_objfile (vp->bfd, 0, 0, 0);
+ obj = allocate_objfile (vp->bfd, 0);
vp->objfile = obj;
#ifndef SOLIB_SYMBOLS_MANUAL
{
int ch;
+ /* FIXME: cagney/1999-10-11: Don't enable this check until the ASYNC
+ code is finished. */
+ if (0 && SERIAL_IS_ASYNC_P (scb) && timeout < 0)
+ internal_error ("serial_readchar: blocking read in async mode");
+
ch = scb->ops->readchar (scb, timeout);
if (serial_logfp != NULL)
{
#define SERIAL_UN_FDOPEN(SERIAL_T) serial_un_fdopen ((SERIAL_T))
/* Read one char from the serial device with TIMEOUT seconds to wait
- or -1 to wait forever. Use timeout of 0 to effect a poll. Returns
- unsigned char if ok, else one of the following codes. Note that
- all error return-codes are guaranteed to be < 0. */
+ or -1 to wait forever. Use timeout of 0 to effect a poll.
+ Infinite waits are not permitted. Returns unsigned char if ok, else
+ one of the following codes. Note that all error return-codes are
+ guaranteed to be < 0. */
enum serial_rc {
SERIAL_ERROR = -1, /* General error. */
- SERIAL_TIMEOUT = -2, /* Timeout during read. ui_loop_hook() can,
- unfortunatly, force this to be returned. */
+ SERIAL_TIMEOUT = -2, /* Timeout or data-not-ready during read.
+ Unfortunatly, through ui_loop_hook(), this
+ can also be a QUIT indication. */
SERIAL_EOF = -3 /* General end-of-file or remote target
connection closed, indication. Includes
things like the line dropping dead. */
section_addrs.text_addr = text_addr;
so->objfile =
symbol_file_add (so->so_name, so->from_tty,
- §ion_addrs,
- 0, 0, 0, 1);
+ §ion_addrs, 0, OBJF_SHARED);
return (1);
}
memset (§ion_addrs, 0, sizeof (section_addrs));
section_addrs.text_addr = text_addr;
- so->objfile = symbol_file_add (name, from_tty, §ion_addrs, 0, 0, 0, 1);
+ so->objfile = symbol_file_add (name, from_tty, §ion_addrs, 0, OBJF_SHARED);
so->abfd = so->objfile->obfd;
/* Mark this as a shared library and save private data.
as dynamically loaded code. If !mainline, ADDR is the address
where the text segment was loaded.
- USER_LOADED is TRUE if the add-symbol-file command was how this
- symbol file came to be processed.
-
- IS_SOLIB is TRUE if this symbol file represents a solib, as discovered
- by the target's implementation of the solib package.
-
Upon success, returns a pointer to the objfile that was added.
Upon failure, jumps back to command level (never returns). */
struct objfile *
-symbol_file_add (name, from_tty, addrs, mainline, flags, user_loaded, is_solib)
+symbol_file_add (name, from_tty, addrs, mainline, flags)
char *name;
int from_tty;
struct section_addr_info *addrs;
int mainline;
int flags;
- int user_loaded;
- int is_solib;
{
struct objfile *objfile;
struct partial_symtab *psymtab;
&& !query ("Load new symbol table from \"%s\"? ", name))
error ("Not confirmed.");
- objfile = allocate_objfile (abfd, flags & OBJF_MAPPED, user_loaded, is_solib);
+ objfile = allocate_objfile (abfd, flags);
/* If the objfile uses a mapped symbol file, and we have a psymtab for
it, then skip reading any symbols at this time. */
char *name = NULL;
CORE_ADDR text_relocation = 0; /* text_relocation */
struct cleanup *cleanups;
- int flags = 0;
+ int flags = OBJF_USERLOADED;
dont_repeat ();
return;
else if (text_relocation == (CORE_ADDR) -1)
{
- symbol_file_add (name, from_tty, NULL,
- 1, flags, 1, 0);
+ symbol_file_add (name, from_tty, NULL, 1, flags);
#ifdef HPUXHPPA
RESET_HP_UX_GLOBALS ();
#endif
struct section_addr_info section_addrs;
memset (§ion_addrs, 0, sizeof (section_addrs));
section_addrs.text_addr = (CORE_ADDR) text_relocation;
- symbol_file_add (name, from_tty, §ion_addrs,
- 0, flags, 1, 0);
+ symbol_file_add (name, from_tty, §ion_addrs, 0, flags);
}
/* Getting new symbols may change our opinion about what is
{
char *name = NULL;
CORE_ADDR text_addr;
- int flags = 0;
+ int flags = OBJF_USERLOADED;
char *arg;
int expecting_option = 0;
int option_index = 0;
if (from_tty && (!query ("%s", "")))
error ("Not confirmed.");
- symbol_file_add (name, from_tty, §ion_addrs, 0, flags,
- 1, /* user_loaded */
- 0); /* We'll guess it's ! is_solib */
+ symbol_file_add (name, from_tty, §ion_addrs, 0, flags);
/* Getting new symbols may change our opinion about what is
frameless. */
clear_solib PARAMS ((void));
extern struct objfile *
- symbol_file_add PARAMS ((char *, int, struct section_addr_info *, int, int, int, int));
+symbol_file_add PARAMS ((char *, int, struct section_addr_info *, int, int));
/* source.c */
+Wed Oct 6 12:05:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * gdb.base/watchpoint.exp: Match fail ``finish from marker1'' with
+ a pass case.
+
1999-10-01 Kevin Buettner <kevinb@cygnus.com>
* gdb.base/break.c (main): Added a statement that we can step
send_gdb "finish\n"
gdb_expect {
- -re "Run.*exit from.*marker1.* at" { }
+ -re "Run.*exit from.*marker1.* at" {
+ pass "finish from marker1"
+ }
default { fail "finish from marker1" ; return }
}
return sp;
}
-/* Push onto the stack the specified value VALUE. */
+#ifndef PARM_BOUNDARY
+#define PARM_BOUNDARY (0)
+#endif
+
+/* Push onto the stack the specified value VALUE. Pad it correctly for
+ it to be an argument to a function. */
static CORE_ADDR
value_push (sp, arg)
value_ptr arg;
{
register int len = TYPE_LENGTH (VALUE_ENCLOSING_TYPE (arg));
+ register int container_len;
+ register int offset;
+
+ /* How big is the container we're going to put this value in? */
+ if (PARM_BOUNDARY)
+ container_len = ((len + PARM_BOUNDARY / TARGET_CHAR_BIT - 1)
+ & ~(PARM_BOUNDARY / TARGET_CHAR_BIT - 1));
+
+ /* Are we going to put it at the high or low end of the container? */
+ if (TARGET_BYTE_ORDER == BIG_ENDIAN)
+ offset = container_len - len;
+ else
+ offset = 0;
if (INNER_THAN (1, 2))
{
/* stack grows downward */
- sp -= len;
- write_memory (sp, VALUE_CONTENTS_ALL (arg), len);
+ sp -= container_len;
+ write_memory (sp + offset, VALUE_CONTENTS_ALL (arg), len);
}
else
{
/* stack grows upward */
- write_memory (sp, VALUE_CONTENTS_ALL (arg), len);
- sp += len;
+ write_memory (sp + offset, VALUE_CONTENTS_ALL (arg), len);
+ sp += container_len;
}
return sp;
printf_unfiltered ("%x:%s", event->lpBaseOfDll, dll_name);
section_addrs.text_addr = (int) event->lpBaseOfDll + 0x1000;
- symbol_file_add (dll_name, 0, §ion_addrs, 0, 0, 0, 1);
+ symbol_file_add (dll_name, 0, §ion_addrs, 0, OBJF_SHARED);
printf_unfiltered ("\n");
return 1;
}
\f
static void
-xcoff_symfile_offsets (objfile, addr)
+xcoff_symfile_offsets (objfile, addrs)
struct objfile *objfile;
struct section_addr_info *addrs;
{
+1999-10-08 Ulrich Drepper <drepper@cygnus.com>
+
+ * armos.c (SWIopen): Always pass third parameter with 0666 since
+ otherwise uninitialized memory gets access if the O_CREAT bit is
+ set and so we possibly cannot access the file afterwards.
+
1999-09-29 Doug Evans <devans@casey.cygnus.com>
* armos.c (SWIWrite0): Send output to stdout instead of stderr.
}
else
{
- state->Reg[0] = (int) open (dummy, flags);
+ state->Reg[0] = (int) open (dummy, flags, 0666);
OSptr->ErrorNo = errno;
}
}
+1999-10-07 Dave Brolley <brolley@cygnus.com>
+
+ * cgen-par.h (CGEN_FN_HI_WRITE): New enumerator.
+ (fn_hi_write): New union member.
+ (sim_queue_fn_hi_write): New function.
+ * cgen-par.c (sim_queue_fn_hi_write): New function.
+ (cgen_write_queue_element_execute): Handle CGEN_FN_HI_WRITE.
+
1999-09-29 Doug Evans <devans@casey.cygnus.com>
* cgen-defs.h (sim_engine_invalid_insn): New arg `vpc'.
element->kinds.pc_write.value = value;
}
+void sim_queue_fn_hi_write (
+ SIM_CPU *cpu,
+ void (*write_function)(SIM_CPU *cpu, UINT, UHI),
+ UINT regno,
+ UHI value
+)
+{
+ CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+ CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+ element->kind = CGEN_FN_HI_WRITE;
+ element->kinds.fn_hi_write.function = write_function;
+ element->kinds.fn_hi_write.regno = regno;
+ element->kinds.fn_hi_write.value = value;
+}
+
void sim_queue_fn_si_write (
SIM_CPU *cpu,
void (*write_function)(SIM_CPU *cpu, UINT, USI),
case CGEN_PC_WRITE:
CPU_PC_SET (cpu, item->kinds.pc_write.value);
break;
+ case CGEN_FN_HI_WRITE:
+ item->kinds.fn_hi_write.function (cpu,
+ item->kinds.fn_hi_write.regno,
+ item->kinds.fn_hi_write.value);
+ break;
case CGEN_FN_SI_WRITE:
item->kinds.fn_si_write.function (cpu,
item->kinds.fn_si_write.regno,
enum cgen_write_queue_kind {
CGEN_BI_WRITE, CGEN_QI_WRITE, CGEN_SI_WRITE, CGEN_SF_WRITE,
CGEN_PC_WRITE,
- CGEN_FN_SI_WRITE, CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE,
+ CGEN_FN_HI_WRITE, CGEN_FN_SI_WRITE, CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE,
CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE,
CGEN_NUM_WRITE_KINDS
};
struct {
USI value;
} pc_write;
+ struct {
+ UINT regno;
+ UHI value;
+ void (*function)(SIM_CPU *, UINT, UHI);
+ } fn_hi_write;
struct {
UINT regno;
SI value;
extern void sim_queue_pc_write (SIM_CPU *, USI);
+extern void sim_queue_fn_hi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, UHI), UINT, UHI);
extern void sim_queue_fn_si_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, USI), UINT, SI);
extern void sim_queue_fn_di_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DI);
extern void sim_queue_fn_df_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DF);
+1999-10-04 Doug Evans <devans@casey.cygnus.com>
+
+ * arch.c,arch.h,cpuall.h: Rebuild.
+ * cpux.h,decodex.c,decodex.h,modelx.c,semx-switch.c: Rebuild.
+
1999-09-29 Doug Evans <devans@casey.cygnus.com>
* mloop.in: Update call to sim_engine_invalid_insn.
* sem.c,sem-switch.c: Rebuild.
* traps.c (sim_engine_invalid_insn): New arg `vpc'. Change type of
result to SEM_PC. Return vpc.
+ * mloopx.in: Ditto.
+ * semx-switch.c: Rebuild.
Wed Sep 29 14:47:20 1999 Dave Brolley <brolley@cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
+1999-09-01 Doug Evans <devans@casey.cygnus.com>
+
+ * decodex.c: Rebuild.
+
1999-08-28 Doug Evans <devans@casey.cygnus.com>
* sem.c: Rebuild
+ * cpux.h: Rebuild.
+
1999-08-09 Doug Evans <devans@casey.cygnus.com>
* cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Rebuild.
+ * cpux.h,decodex.c,decodex.h,modelx.c,semx-switch.c: Rebuild.
1999-08-04 Doug Evans <devans@casey.cygnus.com>
* m32r-sim.h (SEM_SKIP_INSN): Delete.
* cpu.h,cpuall.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild.
+ * cpux.h,decodex.c,modelx.c,semx-switch.c: Rebuild.
+ * mloopx.in (emit_parallel): Call SEM_SKIP_COMPILE.
+ (emit_full_parallel): Ditto.
1999-05-08 Felix Lee <flee@cygnus.com>
1999-04-10 Doug Evans <devans@casey.cygnus.com>
* sem-switch.c,sem.c: Rebuild.
+ * cpux.h,semx-switch.c: Rebuild.
1999-03-27 Doug Evans <devans@casey.cygnus.com>
* decode.c: Rebuild.
+ * decodex.c: Rebuild.
1999-03-26 Doug Evans <devans@casey.cygnus.com>
1999-03-22 Doug Evans <devans@casey.cygnus.com>
* arch.c,arch.h,model.c: Rebuild.
+ * modelx.c: Rebuild.
* m32r-sim.h (a_m32r_h_gr_get,a_m32r_h_gr_set): Declare.
(a_m32r_h_cr_get,a_m32r_h_cr_set): Declare.
* m32r.c (m32rbf_fetch_register): Replace calls to a_m32r_h_pc_get,
1999-03-11 Doug Evans <devans@casey.cygnus.com>
* arch.c,arch.h,cpu.c,cpu.h,sem.c,sem-switch.c: Rebuild.
+ * cpux.c,cpux.h,semx-switch.c: Rebuild.
* m32r-sim.h (GET_H_*,SET_H_*, except GET_H_SM): Delete.
* sim-if.c (sim_open): Update call to m32r_cgen_cpu_open.
* cpu.c,cpu.h: Rebuild.
+start-sanitize-cygnus
+1999-02-12 Doug Evans <devans@casey.cygnus.com>
+
+ * Makefile.in (stamp-arch,stamp-cpu,stamp-xcpu): CGEN_MAIN_SCM
+ renamed to CGEN_READ_SCM.
+
+end-sanitize-cygnus
1999-02-09 Doug Evans <devans@casey.cygnus.com>
* Makefile.in (SIM_EXTRA_DEPS): Add m32r-desc.h, delete cpu-opc.h.
(stamp-xmloop): s/-parallel/-parallel-write/.
+start-sanitize-cygnus
+ (stamp-arch,stamp-cpu): Update FLAGS variable, option syntax changed.
+ (stamp-xcpu): Update FLAGS variable, option syntax changed.
+end-sanitize-cygnus
* configure.in (sim_link_files,sim_link_links): Delete.
* configure: Rebuild.
* decode.c,decode.h,model.c,sem-switch.c,sem.c: Rebuild.
+ * decodex.c,decodex.h,modelx.c,semx-switch.c: Rebuild.
* mloop.in (execute): CGEN_INSN_ATTR renamed to CGEN_INSN_ATTR_VALUE.
* sim-if.c (sim_open): m32r_cgen_cpu_open renamed from
m32r_cgen_opcode_open. Set disassembler.
* sim-main.h: Don't include cpu-opc.h,cpu-sim.h. Include
m32r-desc.h,m32r-opc.h,m32r-sim.h.
+Thu Feb 4 16:04:26 1999 Doug Evans <devans@canuck.cygnus.com>
+
+ * cpux.h,decodex.c,modelx.c,semx-switch.c: Regenerate.
+
1999-01-27 Doug Evans <devans@casey.cygnus.com>
* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild.
+ * cpux.h,decodex.c,modelx.c,semx-switch.c: Rebuild.
1999-01-15 Doug Evans <devans@casey.cygnus.com>
* decode.h,model.c: Regenerate.
+ * decodex.h,modelx.c: Regenerate.
1999-01-14 Doug Evans <devans@casey.cygnus.com>
+start-sanitize-cygnus
+ * Makefile.in (stamp-arch): Pass FLAGS to cgen.
+end-sanitize-cygnus
* arch.c,arch.h,cpuall.h: Regenerate.
* cpu.c,cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Regenerate.
* traps.c (sim_engine_invalid_insn): PCADDR->IADDR.
+ * cpux.c,cpux.h,decodex.c,decodex.h,modelx.c,semx-switch.c: Regenerate.
1999-01-11 Doug Evans <devans@casey.cygnus.com>
* Makefile.in (m32r-clean): rm eng.h.
* sim-main.h: Delete inclusion of ansidecl.h.
* cpu.h: Regenerate.
+ * cpux.h: Regenerate.
1999-01-06 Doug Evans <devans@casey.cygnus.com>
* cpu.h: Regenerate.
+ * cpux.h: Regenerate.
1999-01-05 Doug Evans <devans@casey.cygnus.com>
(arch.o,traps.o,devices.o): Ditto.
(M32RBF_INCLUDE_DEPS): Use CGEN_MAIN_CPU_DEPS.
(m32r.o,mloop.o,cpu.o,decode.o,sem.o,model.o): Simplify dependencies.
+ (m32rx.o,mloopx.o,cpux.o,decodex.o,semx.o,modelx.o): Ditto.
+start-sanitize-cygnus
+ (stamp-arch): Pass mach=all to cgen-arch.
+end-sanitize-cygnus
* cpu.c,cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerate.
* m32r-sim.h (m32rbf_h_cr_[gs]et_handler): Declare.
([GS]ET_H_CR): Define.
([GS]ET_H_PSW): Define.
(m32rbf_h_accum_[gs]et_handler): Declare.
([GS]ET_H_ACCUM): Define.
+ (m32rxf_h_{cr,psw,accum}_[gs]et_handler): Declare.
+ (m32rxf_h_accums_[gs]et_handler): Declare.
+ ([GS]ET_H_ACCUMS): Define.
* sim-if.c (sim_open): Model probing code moved to sim-model.c.
* m32r.c (WANT_CPU): Define as m32rbf.
(all register access fns): Rename to ..._handler.
+ * cpux.c,cpux.h,decodex.c,modelx.c,semx.c: Regenerate.
+ * m32rx.c (WANT_CPU): Define as m32rxf.
+ (all register access fns): Rename to ..._handler.
1998-12-14 Doug Evans <devans@casey.cygnus.com>
1998-12-09 Doug Evans <devans@casey.cygnus.com>
* cpu.h,decode.c,sem-switch.c,sem.c: Regenerate.
+ * cpux.h,decodex.c,semx-switch.c: Regenerate.
* sim-if.c: Include string.h or strings.h if present.
Simplify with call to @cpu@_fill_argbuf,@cpu@_fill_argbuf_tp.
(execute): Test ARGBUF_PROFILE_P before profiling.
Update calls to TRACE_INSN_INIT,TRACE_INSN_FINI.
+ * cpux.h,decodex.c,modelx.c,semx-switch.c: Regenerate.
+ * mloopx.in: Rewrite.
1998-11-22 Doug Evans <devans@tobor.to.cygnus.com>
* Makefile.in (M32R_OBJS): Delete extract.o.
(extract.o): Delete.
+start-sanitize-cygnus
+ (stamp-arch): Depend on $(CGEN_ARCH_SCM).
+ (stamp-cpu): Don't build extract.c.
+end-sanitize-cygnus
* cpu.c,cpu.h,decode.c,decode.h,sem-switch.c,sem.c: Rebuild.
* mloop.in (extract16): Update type of `insn' arg.
Delete call to d->extract.
(extract32): Ditto.
+start-sanitize-cygnus
+ * Makefile.in (M32RX_OBJS): Delete extractx.o.
+ (extractx.o): Delete.
+ (stamp-xcpu): Don't build extractx.c.
+end-sanitize-cygnus
+ * cpux.c,cpux.h,decodex.c,decodex.h,semx-switch.c: Rebuild.
+ * mloopx.in (extractx16): Update type of `insn' arg.
+ Delete call to d->extract. Delete arg pbb_p. All callers updated.
+ (extract-simple,full-exec-simple,fast-exec-simple): Delete.
+ (extractx32): Ditto.
Wed Nov 4 23:55:37 1998 Doug Evans <devans@seba.cygnus.com>
before cgen-types.h.
* tconfig.in: Guard against multiple inclusion.
* cpu.h: Delete decls moved to genmloop.sh.
+ * cpux.h: Ditto.
Mon Oct 19 14:13:05 1998 Doug Evans <devans@seba.cygnus.com>
* sim-main.h: #include cpu-opc.h.
* arch.c,arch.h,decode.c,extract.c,model.c,sem.c: Regenerate
to get #include cleanup.
+ * decodex.c,extractx.c,modelx.c: Ditto.
* Makefile.in (SIM_EXTRA_DEPS): Replace cgen headers with
CGEN_INCLUDE_DEPS.
* sim-main.h: Delete inclusion of cpu.h,decode.h, moved to cpuall.h.
#include cgen-scache.h,cgen-cpu.h.
* tconfig.in (WITH_FOO semantic macros): Delete.
+ * Makefile.in (M32RXF_INCLUDE_DEPS): Define.
+ (m32rx .o's): Depend on it.
+ (mloopx.c): Update call to genmloop.sh.
+ * cpux.h: Regenerate.
Fri Oct 16 09:15:29 1998 Doug Evans <devans@charmed.cygnus.com>
* sim-if.c (sim_do_command): Handle "sim info reg {bbpsw,bbpc}".
+start-sanitize-cygnus
+Wed Oct 14 14:49:50 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * Makefile.in (mloop.o): Don't depend on stamp-cpu, depend on
+ explicit files.
+ (mloopx.o): Ditto for stamp-xcpu.
+
+end-sanitize-cygnus
Fri Oct 9 16:11:58 1998 Doug Evans <devans@seba.cygnus.com>
Add pseudo-basic-block execution support.
(SIM_EXTRA_DEPS): Add include/opcode/cgen.h.
(INCLUDE_DEPS): Delete cpu-sim.h, include/opcode/cgen.h.
(mloop.c): Build pseudo-basic-block version. Depend on stamp-cpu.
+start-sanitize-cygnus
+ (stamp-decode): Delete, build decode files with other cpu files.
+end-sanitize-cygnus
* arch.c,arch.h,cpuall.h: Regenerate.
* cpu.c,cpu.h,decode.c,decode.h,extract.c,model.c: Regenerate.
* sem-switch.c,sem.c: Regenerate.
(m32r_trap): Pass pc to sim_engine_halt.
* configure.in (SIM_AC_OPTION_SCACHE): Change 1024 to 16384.
* configure: Regenerate.
+ * Makefile.in (M32RX_OBJS): Delete semx.o, add extract.o.
+ (mloopx.c): Build pseudo-basic-block version.
+start-sanitize-cygnus
+ Depend on stamp-xcpu.
+end-sanitize-cygnus
+ (semx.o): Delete.
+ (extractx.o): Add.
+start-sanitize-cygnus
+ (stamp-xdecode): Delete, build decode files with other cpu files.
+end-sanitize-cygnus
+ * cpux.c,cpux.h,decodex.c,decodex.h,modelx.c: Regenerate.
+ * readx.c: Delete.
+ * semx.c: Delete.
+ * extractx.c: New file.
+ * semx-switch.c: New file.
+ * m32r-sim.h (BRANCH_NEW_PC): Delete.
+ (SEM_SKIP_INSN): New macro.
+ * m32rx.c (m32rxf_fetch_register): Renamed from m32rx_fetch_register.
+ (m32rxf_store_register,m32rxf_h_cr_get,m32rxf_h_cr_set,
+ m32rxf_h_psw_get,m32rxf_h_psw_set,m32rxf_h_accum_get,
+ m32rxf_h_accum_set,m32rxf_h_accums_get,m32rxf_h_accums_set): Likewise.
+ (m32rxf_model_insn_{before,after}): New fns.
+ (m32rx_model_mark_get_h_gr,m32rx_model_mark_set_h_gr): Delete.
+ (m32rx_model_mark_busy_reg,m32rx_model_mark_unbusy_reg): Delete.
+ (check_load_stall): New fn.
+ (m32rxf_model_m32rx_u_{exec,cmp,mac,cti,load,store}): New fns.
+ * mloopx.in: Rewrite, use pbb support.
+ * tconfig.in (WITH_SCACHE_PBB_M32RXF): Define.
+ (WITH_SEM_SWITCH_FULL): Change from 0 to 1.
Wed Sep 16 18:22:27 1998 Doug Evans <devans@canuck.cygnus.com>
(m32r_decode_gdb_ctrl_regnum): Add prototype.
* m32r.c (m32r_decode_gdb_ctrl_regnum): New function.
(m32r_fetch_register,m32r_store_register): Rewrite.
+ * m32rx.c (m32rx_fetch_register,m32rx_store_register): Rewrite.
Tue Sep 15 15:01:14 1998 Doug Evans <devans@canuck.cygnus.com>
* m32r.c (m32rb_h_cr_get,m32rb_h_cr_set): Handle bbpc,bbpsw.
(m32rb_h_psw_get,m32rb_h_psw_set): New functions.
* arch.c,arch.h,cpu.c,cpu.h,sem-switch.c,sem.c: Regenerate.
+ * m32rx.c (m32rx_h_cr_get,m32rx_h_cr_set): Handle bbpc,bbpsw.
+ (m32rx_h_psw_get,m32rx_h_psw_set): New functions.
+ * cpux.c,cpux.h,readx.c,semx.c: Regenerate.
Wed Sep 9 15:29:36 1998 Doug Evans <devans@canuck.cygnus.com>
* m32r-sim.h (m32r_trap): Update prototype.
* traps.c (m32r_trap): New arg `pc'.
* sem.c,sem-switch.c: Regenerated.
+ * cpux.h,readx.c,semx.c: Regenerated.
Mon Aug 3 12:59:17 1998 Doug Evans <devans@seba.cygnus.com>
Rename cpu m32r to m32rb to distinguish from architecture name.
* Makefile.in (mloop.c): cpu m32r renamed to m32rb.
+start-sanitize-cygnus
+ (stamp-cpu): Ditto.
+end-sanitize-cygnus
* sim-main.h (WANT_CPU_M32RB): Renamed from WANT_CPU_M32R.
* tconfig.in (WANT_CPU_M32RB): Ditto.
* m32r.c (WANT_CPU_M32RB): Ditto.
* sim-if.c (sim_open): Open opcode table.
(sim_close): Close it.
+Tue Jul 28 13:06:19 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ Add support for new versions of mulwhi,mulwlo,macwhi,macwlo that
+ accept an accumulator choice.
+ * cpux.c,decodex.c,decodex.h,modelx.c,readx.c,semx.c: Regenerate.
+
Fri Jul 24 13:00:29 1998 Doug Evans <devans@canuck.cygnus.com>
* m32r.c: Include cgen-mem.h.
* traps.c (m32r_trap): Tweak for -Wall.
+ * m32rx.c: Include cgen-mem.h.
+ * semx.c: Regenerate, get -Wall cleanups.
Tue Jul 21 16:53:10 1998 Doug Evans <devans@seba.cygnus.com>
* cpu.h,extract.c: Regenerate. pc-rel calcs done on f_dispNN now.
+ * cpux.h,readx.c,semx.c: Ditto.
Wed Jul 1 16:51:15 1998 Doug Evans <devans@seba.cygnus.com>
* arch.c,arch.h,cpuall.h: Regenerate.
* cpu.c,cpu.h,decode.c,decode.h,extract.c,model.c: Regenerate.
* sem-switch.c,sem.c: Regenerate.
+ * cpux.c,cpux.h,decodex.c,decodex.h,modelx.c,readx.c: Regenerate.
+ * semx.c: Regenerate.
+ * mloopx.in (icount): Moved here from genmloop.sh.
Sat Jun 13 07:49:23 1998 Doug Evans <devans@fallis.cygnus.com>
(m32r_model_record_cti,m32r_model_record_cycles): New functions.
* mloop.in: Call cycle init/update fns.
* model.c: Regenerate.
+ * m32rx.c (m32rx_model_mark_get_h_gr): Update.
+ * mloopx.in: Call cycle init/update fns.
+ * modelx.c: Regenerate.
+
+start-sanitize-cygnus
+Thu Jun 11 23:39:53 1998 Doug Evans <devans@seba.cygnus.com>
+ * Makefile.in (stamp-{arch,cpu,decode}): Pass CGEN_FLAGS_TO_PASS
+ to recursive makes.
+ (stamp-{xcpu,xdecode}): Ditto.
+
+end-sanitize-cygnus
Wed Jun 10 17:39:29 1998 Doug Evans <devans@canuck.cygnus.com>
* traps.c: New file. Trap support moved here from sim-if.c.
(TRAP_SYSCALL,TRAP_BREAKPOINT): New macros.
* extract.c,sem-switch.c,sem.c: Regenerate.
+ * cpux.h,readx.c,semx.c: Regenerate.
Wed May 20 00:10:40 1998 Doug Evans <devans@seba.cygnus.com>
Zero bottom two bits of pc in jmp,jl insns.
* sem.c,sem-switch.c: Regenerate.
+ * semx.c: Regenerate.
Tue May 19 16:45:33 1998 Doug Evans <devans@seba.cygnus.com>
* arch.h,cpu.c,cpu.h,cpuall.h: Regenerate.
* sem-switch.c,sem.c: Regenerate.
* mloop.in (execute): Update calls to TRACE_INSN_{INIT,FINI}.
+ * cpux.c,cpux.h,modelx.c,semx.c: Regenerate.
+ * m32rx.c (m32rx_model_mark_{busy,unbusy}_reg): New functions.
+ * mloopx.in (execute): Update calls to TRACE_INSN_{INIT,FINI}.
+ Fix pc value passed to TRACE_INSN for second parallel insn.
Thu May 7 02:51:35 1998 Doug Evans <devans@seba.cygnus.com>
* arch.h,arch.c,cpu.h,cpuall.h: Regenerate, tweaks mostly.
* model.c: Ditto. Reorganize model/mach data.
+ * cpux.h: Ditto.
+ * modelx.c: Ditto.
* Makefile.in (m32r.o,mloop.o,cpu.o,model.o): Add decode.h dependency.
+ (m32rx.o,mloopx.o,cpux.o,modelx.o): Add decodex.h dependency.
* decode.c,decode.h: Regenerate, introduces IDESC table.
* mloop.in (extract16,extract32): Add IDESC support.
Update names of semantic handler member names.
(execute): Ditto. Delete call to PROFILE_COUNT_INSN.
+ * decodex.c,decodex.h: Regenerate, introduces IDESC table.
+ * mloopx.in: Add IDESC support.
+ Update names of semantic handler member names.
+ Delete call to PROFILE_COUNT_INSN.
* sem-switch.c: Regenerate. Redo computed goto label handling.
* sem.c: Regenerate. Call PROFILE_COUNT_INSN.
+ * readx.c: Regenerate. Redo computed goto label handling.
+ * semx.c: Regenerate. Call PROFILE_COUNT_INSN. Finish profiling
+ support.
+start-sanitize-cygnus
+ * Makefile.in (stamp-xcpu): Turn on profiling support.
+end-sanitize-cygnus
* m32r.c (m32r_fetch_register): Change result type and args to
conform to sim_fetch_register interface.
(m32r_store_register): Ditto for sim_store_register interface.
+ * m32rx.c (m32rx_fetch_register): Change result type and args to
+ conform to sim_fetch_register interface.
+ (m32rx_store_register): Ditto for sim_store_register interface.
* sim-if.c (alloc_cpu): Delete.
(free_state): Uninstall modules here ...
* sim-main.h (sim_cia): Change to USI.
(sim_cpu): Move m32r_misc_profile before machine generated part.
+start-sanitize-cygnus
+Fri May 1 18:25:41 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * Makefile.in: Replace @MAINT@ with $(CGEN_MAINT).
+ (CGEN_MAINT): New variable.
+ * configure.in: Add support for --enable-cgen-maint.
+ * configure: Regenerate.
+
+end-sanitize-cygnus
Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Tue Apr 28 18:05:53 1998 Nick Clifton <nickc@cygnus.com>
* model.c: Rebuilt.
+ * modelx.c: Rebuilt.
Mon Apr 27 15:36:30 1998 Doug Evans <devans@seba.cygnus.com>
* cpu.h,model.c,sem-switch.c,sem.c: Regenerated. Mostly comment
and variable renaming due to macro insn additions.
* mloop.in: Update to use CGEN_INSN_NUM.
+ * cpux.h,modelx.c,readx.c,semx.c: Regenerated.
+ * mloopx.in: Update to use CGEN_INSN_NUM.
Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
- cgen/m32r.cpu (h-accum): Add attribute FUN-ACCESS.
* m32r.c (m32r_h_accum_get,m32r_h_accum_set): New functions.
#include cgen-ops.h.
+ * cpux.c,readx.c,semx.c: Regenerate.
+ * m32rx.c (m32r_h_accum_get,m32r_h_accum_set): New functions.
+ #include cgen-ops.h. Delete inclusion of several unnecessary headers.
+ (m32r_h_accums_get): Sign extend top 8 bits.
+
+Tue Apr 14 14:04:07 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * semx.c: Regenerate.
Fri Apr 10 18:22:41 1998 Doug Evans <devans@canuck.cygnus.com>
* cpu.h,decode.c,decode.h,extract.c,sem.c,sem-switch.c: Regenerate.
+ * cpux.h,decodex.c,decodex.h,readx.c,semx.c: Regenerate.
Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
* sim-if.c (do_trap): Result is new pc.
Handle --environment=operating.
* sem-switch.c,sem.c: Regenerate.
+ * semx.c: Regenerate.
Wed Mar 11 14:07:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
* Makefile.in (SIM_EXTRA_DEPS): Add cpu-opc.h.
(arch.o): Delete cpu-opc.h dependency.
(decode.o,model.o): Likewise.
+ (decodex.o,modelx.o): Likewise.
* cpu.h,model.c,sem-switch.c,sem.c: Regenerate.
+ * cpux.h,decodex.[ch],modelx.c,readx.c,semx.c: Regenerate.
Thu Feb 26 18:38:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
* sim-if.c (sim_info): Delete.
+Fri Feb 27 10:14:29 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * mloopx.in: Fix handling of branch in parallel with another insn.
+ * semx.c: Regenerate.
+
Mon Feb 23 13:30:46 1998 Doug Evans <devans@seba.cygnus.com>
* sim-main.h: #include symcat.h.
(NEW_PC_{BASE,SKIP,2,4,BRANCH_P}): New macros.
* cpu.[ch],decode.[ch],extract.c,model.c: Regenerate.
* sem.c,sem-switch.c: Regenerate.
+ * m32r-sim.h (SEM_NEXT_PC): Modify to handle parallel exec.
+ * mloopx.in: Rewrite.
+ * cpux.[ch],decodex.[ch],readx.c,semx.c: Regenerate.
Mon Feb 23 12:27:52 1998 Nick Clifton <nickc@cygnus.com>
* m32r.c (m32r_h_cr_set, m32r_h_cr_get): Shadow control register 6
in the backup PC register.
+ * m32rx.c (m32r_h_cr_set, m32r_h_cr_get): Shadow control register 6
+ in the backup PC register.
Thu Feb 19 16:39:35 1998 Doug Evans <devans@canuck.cygnus.com>
* m32r.c (do_lock,do_unlock): Delete.
* cpu.[ch],decode.[ch],extract.c,model.c: Regenerate.
* sem.c,sem-switch.c: Regenerate.
+ * cpux.[ch],decodex.[ch],readx.c,semx.c: Regenerate.
Tue Feb 17 18:18:10 1998 Doug Evans <devans@seba.cygnus.com>
* cpuall.h,cpu.h,decode.c,decode.h,extract.c,model.c: Regenerate.
* sem-switch.c,sem.c: Regenerate.
* mloop.in (execute): Update call to semantic fn.
+ (M32RX_OBJS): Add cpux.o.
+ (cpux.o): Add rule for.
+ cpux.c: New file.
+ * cpux.h,decodex.c,decodex.h,modelx.c,readx.c,semx.c: Regenerate.
+ * m32rx.c (m32rx_h_accums_{get,set}): Rewrite.
+ (m32rx_h_cr_{get,set}): New functions.
+ (m32rx_h_accums_{get,set}): New functions.
+ * mloopx.in: Rewrite main loop.
* m32r.c (do_trap): Move from here.
* sim-if.c (do_trap): To here, and rewrite to use CB_SYSCALL support.
* sim-main.h (CIA_GET,CIA_SET): Provide dummy definitions for now.
* decode.c, decode.h, sem.c, sem-switch.c, model.c: Regenerate.
+ * cpux.c, decodex.c, decodex.h, readx.c, semx.c, modelx.c: Regenerate.
Mon Feb 9 19:41:54 1998 Doug Evans <devans@canuck.cygnus.com>
* decode.c, sem.c: Regenerate.
+ * cpux.h, decodex.c, readx.c, semx.c: Regenerate.
+ * m32rx.c (m32rx_h_accums_set): New function.
+ (m32rx_model_mark_[gs]et_h_gr): New function.
+ * mloopx.in: Rewrite.
+ * Makefile.in (mloopx.o): Build with -parallel.
+ * sim-main.h (_sim_cpu): Delete member `par_exec'.
+ * tconfig.in (WITH_SEM_SWITCH_FULL): Define as 0 for m32rx.
Thu Feb 5 12:44:31 1998 Doug Evans <devans@seba.cygnus.com>
* extract.c,model.c,sem-switch.c,sem.c: Regenerate.
* sim-main.h: #include "ansidecl.h".
Don't include cpu-opc.h, done by arch.h.
+ * Makefile.in (M32RX_OBJS): Build m32rx support now.
+ (m32rx.o): New rule.
+ * m32r-sim.h (m32rx_h_cr_[gs]et): Define.
+ * m32rx.c (m32rx_{fetch,store}_register): Update {get,set} of PC.
+ (m32rx_h_accums_get): New function.
+ * mloopx.in: Update call to m32rx_decode. Rewrite exec loop.
+ * cpux.h,decodex.[ch],modelx.c,readx.c,semx.c: Regenerate.
Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
+Thu Jan 29 11:22:00 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * Makefile.in (M32RX_OBJS): Comment out until m32rx port working.
+ * arch.h (HAVE_CPU_M32R{,X}): Delete, moved to m32r-opc.h.
+ * arch.c (machs): Check ifdef HAVE_CPU_FOO for each entry.
+
Tue Jan 20 14:16:02 1998 Nick Clifton <nickc@cygnus.com>
* cpux.h: Fix duplicate definition of h_accums field for
fmt_53_sadd structure.
+Tue Jan 20 01:42:17 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * Makefile.in: Add m32rx objs, and rules to build them.
+ * cpux.h, decodex.h, decodex.c, readx.c, semx.c, modelx.c: New files.
+ * m32rx.c, mloopx.in: New files.
+
Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
* configure: Regenerated to track ../common/aclocal.m4 changes.
* Makefile.in: Update.
* sem-ops.h: Deleted.
* mem-ops.h: Deleted.
+start-sanitize-cygnus
+ Add cgen support for generating files.
+end-sanitize-cygnus
(arch): Renamed from CPU.
* cpu.h: New file.
* decode.c: Redone.
(sim_open): Call sim_state_alloc, and malloc space for selected cpu
type. Call sim_analyze_program.
(sim_create_inferior): Handle selected cpu type when setting PC.
+ (sim_resume): Handle m32rx.
(sim_stop_reason): Deleted.
(print_m32r_misc_cpu): Update.
+ (sim_{fetch,store}_register): Handle m32rx.
(sim_{read,write}): Deleted.
(sim_engine_illegal_insn): New function.
* sim-main.h: Don't include arch-defs.h,sim-core.h,sim-events.h.
Include arch.h,cpuall.h. Include cpu.h,decode.h if m32r.
+ Include cpux.h,decodex.h if m32rx.
(_sim_cpu): Include member appropriate cpu_data member for the cpu.
(M32R_MISC_PROFILE): Renamed from M32R_PROFILE.
(sim_state): Delete members core,events,halt_jmp_buf.
## COMMON_PRE_CONFIG_FRAG
M32R_OBJS = m32r.o cpu.o decode.o sem.o model.o mloop.o
+M32RX_OBJS = m32rx.o cpux.o decodex.o modelx.o mloopx.o
CONFIG_DEVICES = dv-sockser.o
CONFIG_DEVICES =
cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
sim-if.o arch.o \
$(M32R_OBJS) \
+ $(M32RX_OBJS) \
traps.o devices.o \
$(CONFIG_DEVICES)
sem.o: sem.c $(M32RBF_INCLUDE_DEPS)
model.o: model.c $(M32RBF_INCLUDE_DEPS)
+# M32RX objs
+
+M32RXF_INCLUDE_DEPS = \
+ $(CGEN_MAIN_CPU_DEPS) \
+ cpux.h decodex.h engx.h
+
+m32rx.o: m32rx.c $(M32RXF_INCLUDE_DEPS)
+
+# FIXME: Use of `mono' is wip.
+mloopx.c engx.h: stamp-xmloop
+stamp-xmloop: $(srcdir)/../common/genmloop.sh mloopx.in Makefile
+ $(SHELL) $(srccom)/genmloop.sh \
+ -mono -no-fast -pbb -parallel-write -switch semx-switch.c \
+ -cpu m32rxf -infile $(srcdir)/mloopx.in
+ $(SHELL) $(srcroot)/move-if-change eng.hin engx.h
+ $(SHELL) $(srcroot)/move-if-change mloop.cin mloopx.c
+ touch stamp-xmloop
+mloopx.o: mloopx.c semx-switch.c $(M32RXF_INCLUDE_DEPS)
+
+cpux.o: cpux.c $(M32RXF_INCLUDE_DEPS)
+decodex.o: decodex.c $(M32RXF_INCLUDE_DEPS)
+semx.o: semx.c $(M32RXF_INCLUDE_DEPS)
+modelx.o: modelx.c $(M32RXF_INCLUDE_DEPS)
m32r-clean:
rm -f mloop.c eng.h stamp-mloop
+ rm -f mloopx.c engx.h stamp-xmloop
+# start-sanitize-cygnus
+ rm -f stamp-arch stamp-cpu stamp-xcpu
+# end-sanitize-cygnus
rm -f tmp-*
-
+# start-sanitize-cygnus
+# cgen support, enable with --enable-cgen-maint
+CGEN_MAINT = ; @true
+# The following line is commented in or out depending upon --enable-cgen-maint.
+@CGEN_MAINT@CGEN_MAINT =
+
+stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(srccgen)/m32r.cpu
+ $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all \
+ FLAGS="with-scache with-profile=fn"
+ touch stamp-arch
+arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
+ @true
+
+stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
+ $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
+ cpu=m32rbf mach=m32r SUFFIX= \
+ FLAGS="with-scache with-profile=fn" \
+ EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
+ touch stamp-cpu
+cpu.h sem.c sem-switch.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu
+ @true
+
+stamp-xcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
+ $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
+ cpu=m32rxf mach=m32rx SUFFIX=x FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"
+ touch stamp-xcpu
+cpux.h semx-switch.c modelx.c decodex.c decodex.h: $(CGEN_MAINT) stamp-xcpu
+ @true
+# end-sanitize-cygnus
{
#ifdef HAVE_CPU_M32RBF
& m32r_mach,
+#endif
+#ifdef HAVE_CPU_M32RXF
+ & m32rx_mach,
#endif
0
};
/* Enum declaration for model types. */
typedef enum model_type {
- MODEL_M32R_D, MODEL_TEST
- , MODEL_MAX
+ MODEL_M32R_D, MODEL_TEST, MODEL_M32RX, MODEL_MAX
} MODEL_TYPE;
#define MAX_MODELS ((int) MODEL_MAX)
typedef enum unit_type {
UNIT_NONE, UNIT_M32R_D_U_STORE, UNIT_M32R_D_U_LOAD, UNIT_M32R_D_U_CTI
, UNIT_M32R_D_U_MAC, UNIT_M32R_D_U_CMP, UNIT_M32R_D_U_EXEC, UNIT_TEST_U_EXEC
- , UNIT_MAX
+ , UNIT_M32RX_U_STORE, UNIT_M32RX_U_LOAD, UNIT_M32RX_U_CTI, UNIT_M32RX_U_MAC
+ , UNIT_M32RX_U_CMP, UNIT_M32RX_U_EXEC, UNIT_MAX
} UNIT_TYPE;
#define MAX_UNITS (2)
#endif
extern const MACH m32r_mach;
+extern const MACH m32rx_mach;
#ifndef WANT_CPU
/* The ARGBUF struct. */
--- /dev/null
+/* Misc. support for CPU family m32rxf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU m32rxf
+#define WANT_CPU_M32RXF
+
+#include "sim-main.h"
+#include "cgen-ops.h"
+
+/* Get the value of h-pc. */
+
+USI
+m32rxf_h_pc_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_pc);
+}
+
+/* Set a value for h-pc. */
+
+void
+m32rxf_h_pc_set (SIM_CPU *current_cpu, USI newval)
+{
+ CPU (h_pc) = newval;
+}
+
+/* Get the value of h-gr. */
+
+SI
+m32rxf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return CPU (h_gr[regno]);
+}
+
+/* Set a value for h-gr. */
+
+void
+m32rxf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ CPU (h_gr[regno]) = newval;
+}
+
+/* Get the value of h-cr. */
+
+USI
+m32rxf_h_cr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_CR (regno);
+}
+
+/* Set a value for h-cr. */
+
+void
+m32rxf_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
+{
+ SET_H_CR (regno, newval);
+}
+
+/* Get the value of h-accum. */
+
+DI
+m32rxf_h_accum_get (SIM_CPU *current_cpu)
+{
+ return GET_H_ACCUM ();
+}
+
+/* Set a value for h-accum. */
+
+void
+m32rxf_h_accum_set (SIM_CPU *current_cpu, DI newval)
+{
+ SET_H_ACCUM (newval);
+}
+
+/* Get the value of h-accums. */
+
+DI
+m32rxf_h_accums_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_ACCUMS (regno);
+}
+
+/* Set a value for h-accums. */
+
+void
+m32rxf_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval)
+{
+ SET_H_ACCUMS (regno, newval);
+}
+
+/* Get the value of h-cond. */
+
+BI
+m32rxf_h_cond_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_cond);
+}
+
+/* Set a value for h-cond. */
+
+void
+m32rxf_h_cond_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_cond) = newval;
+}
+
+/* Get the value of h-psw. */
+
+UQI
+m32rxf_h_psw_get (SIM_CPU *current_cpu)
+{
+ return GET_H_PSW ();
+}
+
+/* Set a value for h-psw. */
+
+void
+m32rxf_h_psw_set (SIM_CPU *current_cpu, UQI newval)
+{
+ SET_H_PSW (newval);
+}
+
+/* Get the value of h-bpsw. */
+
+UQI
+m32rxf_h_bpsw_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_bpsw);
+}
+
+/* Set a value for h-bpsw. */
+
+void
+m32rxf_h_bpsw_set (SIM_CPU *current_cpu, UQI newval)
+{
+ CPU (h_bpsw) = newval;
+}
+
+/* Get the value of h-bbpsw. */
+
+UQI
+m32rxf_h_bbpsw_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_bbpsw);
+}
+
+/* Set a value for h-bbpsw. */
+
+void
+m32rxf_h_bbpsw_set (SIM_CPU *current_cpu, UQI newval)
+{
+ CPU (h_bbpsw) = newval;
+}
+
+/* Get the value of h-lock. */
+
+BI
+m32rxf_h_lock_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_lock);
+}
+
+/* Set a value for h-lock. */
+
+void
+m32rxf_h_lock_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_lock) = newval;
+}
+
+/* Record trace results for INSN. */
+
+void
+m32rxf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
+ int *indices, TRACE_RECORD *tr)
+{
+}
--- /dev/null
+/* CPU family header for m32rxf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef CPU_M32RXF_H
+#define CPU_M32RXF_H
+
+/* Maximum number of instructions that are fetched at a time.
+ This is for LIW type instructions sets (e.g. m32r). */
+#define MAX_LIW_INSNS 2
+
+/* Maximum number of instructions that can be executed in parallel. */
+#define MAX_PARALLEL_INSNS 2
+
+/* CPU state information. */
+typedef struct {
+ /* Hardware elements. */
+ struct {
+ /* program counter */
+ USI h_pc;
+#define GET_H_PC() CPU (h_pc)
+#define SET_H_PC(x) (CPU (h_pc) = (x))
+ /* general registers */
+ SI h_gr[16];
+#define GET_H_GR(a1) CPU (h_gr)[a1]
+#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
+ /* control registers */
+ USI h_cr[16];
+#define GET_H_CR(index) m32rxf_h_cr_get_handler (current_cpu, index)
+#define SET_H_CR(index, x) \
+do { \
+m32rxf_h_cr_set_handler (current_cpu, (index), (x));\
+} while (0)
+ /* accumulator */
+ DI h_accum;
+#define GET_H_ACCUM() m32rxf_h_accum_get_handler (current_cpu)
+#define SET_H_ACCUM(x) \
+do { \
+m32rxf_h_accum_set_handler (current_cpu, (x));\
+} while (0)
+ /* accumulators */
+ DI h_accums[2];
+#define GET_H_ACCUMS(index) m32rxf_h_accums_get_handler (current_cpu, index)
+#define SET_H_ACCUMS(index, x) \
+do { \
+m32rxf_h_accums_set_handler (current_cpu, (index), (x));\
+} while (0)
+ /* condition bit */
+ BI h_cond;
+#define GET_H_COND() CPU (h_cond)
+#define SET_H_COND(x) (CPU (h_cond) = (x))
+ /* psw part of psw */
+ UQI h_psw;
+#define GET_H_PSW() m32rxf_h_psw_get_handler (current_cpu)
+#define SET_H_PSW(x) \
+do { \
+m32rxf_h_psw_set_handler (current_cpu, (x));\
+} while (0)
+ /* backup psw */
+ UQI h_bpsw;
+#define GET_H_BPSW() CPU (h_bpsw)
+#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
+ /* backup bpsw */
+ UQI h_bbpsw;
+#define GET_H_BBPSW() CPU (h_bbpsw)
+#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
+ /* lock */
+ BI h_lock;
+#define GET_H_LOCK() CPU (h_lock)
+#define SET_H_LOCK(x) (CPU (h_lock) = (x))
+ } hardware;
+#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
+} M32RXF_CPU_DATA;
+
+/* Cover fns for register access. */
+USI m32rxf_h_pc_get (SIM_CPU *);
+void m32rxf_h_pc_set (SIM_CPU *, USI);
+SI m32rxf_h_gr_get (SIM_CPU *, UINT);
+void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
+USI m32rxf_h_cr_get (SIM_CPU *, UINT);
+void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
+DI m32rxf_h_accum_get (SIM_CPU *);
+void m32rxf_h_accum_set (SIM_CPU *, DI);
+DI m32rxf_h_accums_get (SIM_CPU *, UINT);
+void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
+BI m32rxf_h_cond_get (SIM_CPU *);
+void m32rxf_h_cond_set (SIM_CPU *, BI);
+UQI m32rxf_h_psw_get (SIM_CPU *);
+void m32rxf_h_psw_set (SIM_CPU *, UQI);
+UQI m32rxf_h_bpsw_get (SIM_CPU *);
+void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
+UQI m32rxf_h_bbpsw_get (SIM_CPU *);
+void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
+BI m32rxf_h_lock_get (SIM_CPU *);
+void m32rxf_h_lock_set (SIM_CPU *, BI);
+
+/* These must be hand-written. */
+extern CPUREG_FETCH_FN m32rxf_fetch_register;
+extern CPUREG_STORE_FN m32rxf_store_register;
+
+typedef struct {
+ int empty;
+} MODEL_M32RX_DATA;
+
+/* Instruction argument buffer. */
+
+union sem_fields {
+ struct { /* no operands */
+ int empty;
+ } fmt_empty;
+ struct { /* */
+ UINT f_uimm4;
+ } sfmt_trap;
+ struct { /* */
+ IADDR i_disp24;
+ unsigned char out_h_gr_14;
+ } sfmt_bl24;
+ struct { /* */
+ IADDR i_disp8;
+ unsigned char out_h_gr_14;
+ } sfmt_bl8;
+ struct { /* */
+ SI* i_dr;
+ UINT f_hi16;
+ unsigned char out_dr;
+ } sfmt_seth;
+ struct { /* */
+ SI f_imm1;
+ UINT f_accd;
+ UINT f_accs;
+ } sfmt_rac_dsi;
+ struct { /* */
+ SI* i_sr;
+ UINT f_r1;
+ unsigned char in_sr;
+ } sfmt_mvtc;
+ struct { /* */
+ SI* i_src1;
+ UINT f_accs;
+ unsigned char in_src1;
+ } sfmt_mvtachi_a;
+ struct { /* */
+ SI* i_dr;
+ UINT f_r2;
+ unsigned char out_dr;
+ } sfmt_mvfc;
+ struct { /* */
+ SI* i_dr;
+ UINT f_accs;
+ unsigned char out_dr;
+ } sfmt_mvfachi_a;
+ struct { /* */
+ ADDR i_uimm24;
+ SI* i_dr;
+ unsigned char out_dr;
+ } sfmt_ld24;
+ struct { /* */
+ SI* i_sr;
+ unsigned char in_sr;
+ unsigned char out_h_gr_14;
+ } sfmt_jl;
+ struct { /* */
+ SI* i_dr;
+ UINT f_uimm5;
+ unsigned char in_dr;
+ unsigned char out_dr;
+ } sfmt_slli;
+ struct { /* */
+ SI* i_dr;
+ INT f_simm8;
+ unsigned char in_dr;
+ unsigned char out_dr;
+ } sfmt_addi;
+ struct { /* */
+ SI* i_src1;
+ SI* i_src2;
+ unsigned char in_src1;
+ unsigned char in_src2;
+ unsigned char out_src2;
+ } sfmt_st_plus;
+ struct { /* */
+ SI* i_src1;
+ SI* i_src2;
+ INT f_simm16;
+ unsigned char in_src1;
+ unsigned char in_src2;
+ } sfmt_st_d;
+ struct { /* */
+ SI* i_src1;
+ SI* i_src2;
+ UINT f_acc;
+ unsigned char in_src1;
+ unsigned char in_src2;
+ } sfmt_machi_a;
+ struct { /* */
+ SI* i_dr;
+ SI* i_sr;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ unsigned char out_sr;
+ } sfmt_ld_plus;
+ struct { /* */
+ IADDR i_disp16;
+ SI* i_src1;
+ SI* i_src2;
+ unsigned char in_src1;
+ unsigned char in_src2;
+ } sfmt_beq;
+ struct { /* */
+ SI* i_dr;
+ SI* i_sr;
+ UINT f_uimm16;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } sfmt_and3;
+ struct { /* */
+ SI* i_dr;
+ SI* i_sr;
+ INT f_simm16;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } sfmt_add3;
+ struct { /* */
+ SI* i_dr;
+ SI* i_sr;
+ unsigned char in_dr;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } sfmt_add;
+#if WITH_SCACHE_PBB
+ /* Writeback handler. */
+ struct {
+ /* Pointer to argbuf entry for insn whose results need writing back. */
+ const struct argbuf *abuf;
+ } write;
+ /* x-before handler */
+ struct {
+ /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
+ int first_p;
+ } before;
+ /* x-after handler */
+ struct {
+ int empty;
+ } after;
+ /* This entry is used to terminate each pbb. */
+ struct {
+ /* Number of insns in pbb. */
+ int insn_count;
+ /* Next pbb to execute. */
+ SCACHE *next;
+ SCACHE *branch_target;
+ } chain;
+#endif
+};
+
+/* The ARGBUF struct. */
+struct argbuf {
+ /* These are the baseclass definitions. */
+ IADDR addr;
+ const IDESC *idesc;
+ char trace_p;
+ char profile_p;
+ /* ??? Temporary hack for skip insns. */
+ char skip_count;
+ char unused;
+ /* cpu specific data follows */
+ union sem semantic;
+ int written;
+ union sem_fields fields;
+};
+
+/* A cached insn.
+
+ ??? SCACHE used to contain more than just argbuf. We could delete the
+ type entirely and always just use ARGBUF, but for future concerns and as
+ a level of abstraction it is left in. */
+
+struct scache {
+ struct argbuf argbuf;
+};
+
+/* Macros to simplify extraction, reading and semantic code.
+ These define and assign the local vars that contain the insn's fields. */
+
+#define EXTRACT_IFMT_EMPTY_VARS \
+ unsigned int length;
+#define EXTRACT_IFMT_EMPTY_CODE \
+ length = 0; \
+
+#define EXTRACT_IFMT_ADD_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_CODE \
+ length = 2; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_ADD3_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ INT f_simm16; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD3_CODE \
+ length = 4; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_AND3_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ UINT f_uimm16; \
+ unsigned int length;
+#define EXTRACT_IFMT_AND3_CODE \
+ length = 4; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_OR3_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ UINT f_uimm16; \
+ unsigned int length;
+#define EXTRACT_IFMT_OR3_CODE \
+ length = 4; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_ADDI_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ INT f_simm8; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADDI_CODE \
+ length = 2; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \
+
+#define EXTRACT_IFMT_ADDV3_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ INT f_simm16; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADDV3_CODE \
+ length = 4; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_BC8_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ SI f_disp8; \
+ unsigned int length;
+#define EXTRACT_IFMT_BC8_CODE \
+ length = 2; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
+
+#define EXTRACT_IFMT_BC24_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ SI f_disp24; \
+ unsigned int length;
+#define EXTRACT_IFMT_BC24_CODE \
+ length = 4; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
+
+#define EXTRACT_IFMT_BEQ_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ SI f_disp16; \
+ unsigned int length;
+#define EXTRACT_IFMT_BEQ_CODE \
+ length = 4; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
+
+#define EXTRACT_IFMT_BEQZ_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ SI f_disp16; \
+ unsigned int length;
+#define EXTRACT_IFMT_BEQZ_CODE \
+ length = 4; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
+
+#define EXTRACT_IFMT_CMP_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ unsigned int length;
+#define EXTRACT_IFMT_CMP_CODE \
+ length = 2; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_CMPI_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ INT f_simm16; \
+ unsigned int length;
+#define EXTRACT_IFMT_CMPI_CODE \
+ length = 4; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_CMPZ_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ unsigned int length;
+#define EXTRACT_IFMT_CMPZ_CODE \
+ length = 2; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_DIV_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ INT f_simm16; \
+ unsigned int length;
+#define EXTRACT_IFMT_DIV_CODE \
+ length = 4; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_JC_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ unsigned int length;
+#define EXTRACT_IFMT_JC_CODE \
+ length = 2; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_LD24_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_uimm24; \
+ unsigned int length;
+#define EXTRACT_IFMT_LD24_CODE \
+ length = 4; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
+
+#define EXTRACT_IFMT_LDI16_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ INT f_simm16; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDI16_CODE \
+ length = 4; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_MACHI_A_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_acc; \
+ UINT f_op23; \
+ UINT f_r2; \
+ unsigned int length;
+#define EXTRACT_IFMT_MACHI_A_CODE \
+ length = 2; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); \
+ f_op23 = EXTRACT_MSB0_UINT (insn, 16, 9, 3); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_MVFACHI_A_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_accs; \
+ UINT f_op3; \
+ unsigned int length;
+#define EXTRACT_IFMT_MVFACHI_A_CODE \
+ length = 2; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
+ f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
+
+#define EXTRACT_IFMT_MVFC_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ unsigned int length;
+#define EXTRACT_IFMT_MVFC_CODE \
+ length = 2; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_MVTACHI_A_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_accs; \
+ UINT f_op3; \
+ unsigned int length;
+#define EXTRACT_IFMT_MVTACHI_A_CODE \
+ length = 2; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
+ f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
+
+#define EXTRACT_IFMT_MVTC_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ unsigned int length;
+#define EXTRACT_IFMT_MVTC_CODE \
+ length = 2; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_NOP_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ unsigned int length;
+#define EXTRACT_IFMT_NOP_CODE \
+ length = 2; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_RAC_DSI_VARS \
+ UINT f_op1; \
+ UINT f_accd; \
+ UINT f_bits67; \
+ UINT f_op2; \
+ UINT f_accs; \
+ UINT f_bit14; \
+ SI f_imm1; \
+ unsigned int length;
+#define EXTRACT_IFMT_RAC_DSI_CODE \
+ length = 2; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); \
+ f_bits67 = EXTRACT_MSB0_UINT (insn, 16, 6, 2); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
+ f_bit14 = EXTRACT_MSB0_UINT (insn, 16, 14, 1); \
+ f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); \
+
+#define EXTRACT_IFMT_SETH_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ UINT f_hi16; \
+ unsigned int length;
+#define EXTRACT_IFMT_SETH_CODE \
+ length = 4; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_SLLI_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_shift_op2; \
+ UINT f_uimm5; \
+ unsigned int length;
+#define EXTRACT_IFMT_SLLI_CODE \
+ length = 2; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
+ f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
+
+#define EXTRACT_IFMT_ST_D_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ INT f_simm16; \
+ unsigned int length;
+#define EXTRACT_IFMT_ST_D_CODE \
+ length = 4; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_TRAP_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_uimm4; \
+ unsigned int length;
+#define EXTRACT_IFMT_TRAP_CODE \
+ length = 2; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+ f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_SATB_VARS \
+ UINT f_op1; \
+ UINT f_r1; \
+ UINT f_op2; \
+ UINT f_r2; \
+ UINT f_uimm16; \
+ unsigned int length;
+#define EXTRACT_IFMT_SATB_CODE \
+ length = 4; \
+ f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+ f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+ f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+/* Queued output values of an instruction. */
+
+struct parexec {
+ union {
+ struct { /* empty sformat for unspecified field list */
+ int empty;
+ } sfmt_empty;
+ struct { /* e.g. add $dr,$sr */
+ SI dr;
+ } sfmt_add;
+ struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
+ SI dr;
+ } sfmt_add3;
+ struct { /* e.g. and3 $dr,$sr,$uimm16 */
+ SI dr;
+ } sfmt_and3;
+ struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
+ SI dr;
+ } sfmt_or3;
+ struct { /* e.g. addi $dr,$simm8 */
+ SI dr;
+ } sfmt_addi;
+ struct { /* e.g. addv $dr,$sr */
+ BI condbit;
+ SI dr;
+ } sfmt_addv;
+ struct { /* e.g. addv3 $dr,$sr,$simm16 */
+ BI condbit;
+ SI dr;
+ } sfmt_addv3;
+ struct { /* e.g. addx $dr,$sr */
+ BI condbit;
+ SI dr;
+ } sfmt_addx;
+ struct { /* e.g. bc.s $disp8 */
+ USI pc;
+ } sfmt_bc8;
+ struct { /* e.g. bc.l $disp24 */
+ USI pc;
+ } sfmt_bc24;
+ struct { /* e.g. beq $src1,$src2,$disp16 */
+ USI pc;
+ } sfmt_beq;
+ struct { /* e.g. beqz $src2,$disp16 */
+ USI pc;
+ } sfmt_beqz;
+ struct { /* e.g. bl.s $disp8 */
+ SI h_gr_14;
+ USI pc;
+ } sfmt_bl8;
+ struct { /* e.g. bl.l $disp24 */
+ SI h_gr_14;
+ USI pc;
+ } sfmt_bl24;
+ struct { /* e.g. bcl.s $disp8 */
+ SI h_gr_14;
+ USI pc;
+ } sfmt_bcl8;
+ struct { /* e.g. bcl.l $disp24 */
+ SI h_gr_14;
+ USI pc;
+ } sfmt_bcl24;
+ struct { /* e.g. bra.s $disp8 */
+ USI pc;
+ } sfmt_bra8;
+ struct { /* e.g. bra.l $disp24 */
+ USI pc;
+ } sfmt_bra24;
+ struct { /* e.g. cmp $src1,$src2 */
+ BI condbit;
+ } sfmt_cmp;
+ struct { /* e.g. cmpi $src2,$simm16 */
+ BI condbit;
+ } sfmt_cmpi;
+ struct { /* e.g. cmpz $src2 */
+ BI condbit;
+ } sfmt_cmpz;
+ struct { /* e.g. div $dr,$sr */
+ SI dr;
+ } sfmt_div;
+ struct { /* e.g. jc $sr */
+ USI pc;
+ } sfmt_jc;
+ struct { /* e.g. jl $sr */
+ SI h_gr_14;
+ USI pc;
+ } sfmt_jl;
+ struct { /* e.g. jmp $sr */
+ USI pc;
+ } sfmt_jmp;
+ struct { /* e.g. ld $dr,@$sr */
+ SI dr;
+ } sfmt_ld;
+ struct { /* e.g. ld $dr,@($slo16,$sr) */
+ SI dr;
+ } sfmt_ld_d;
+ struct { /* e.g. ld $dr,@$sr+ */
+ SI dr;
+ SI sr;
+ } sfmt_ld_plus;
+ struct { /* e.g. ld24 $dr,$uimm24 */
+ SI dr;
+ } sfmt_ld24;
+ struct { /* e.g. ldi8 $dr,$simm8 */
+ SI dr;
+ } sfmt_ldi8;
+ struct { /* e.g. ldi16 $dr,$hash$slo16 */
+ SI dr;
+ } sfmt_ldi16;
+ struct { /* e.g. lock $dr,@$sr */
+ SI dr;
+ BI h_lock;
+ } sfmt_lock;
+ struct { /* e.g. machi $src1,$src2,$acc */
+ DI acc;
+ } sfmt_machi_a;
+ struct { /* e.g. mulhi $src1,$src2,$acc */
+ DI acc;
+ } sfmt_mulhi_a;
+ struct { /* e.g. mv $dr,$sr */
+ SI dr;
+ } sfmt_mv;
+ struct { /* e.g. mvfachi $dr,$accs */
+ SI dr;
+ } sfmt_mvfachi_a;
+ struct { /* e.g. mvfc $dr,$scr */
+ SI dr;
+ } sfmt_mvfc;
+ struct { /* e.g. mvtachi $src1,$accs */
+ DI accs;
+ } sfmt_mvtachi_a;
+ struct { /* e.g. mvtc $sr,$dcr */
+ USI dcr;
+ } sfmt_mvtc;
+ struct { /* e.g. nop */
+ int empty;
+ } sfmt_nop;
+ struct { /* e.g. rac $accd,$accs,$imm1 */
+ DI accd;
+ } sfmt_rac_dsi;
+ struct { /* e.g. rte */
+ UQI h_bpsw;
+ USI h_cr_6;
+ UQI h_psw;
+ USI pc;
+ } sfmt_rte;
+ struct { /* e.g. seth $dr,$hash$hi16 */
+ SI dr;
+ } sfmt_seth;
+ struct { /* e.g. sll3 $dr,$sr,$simm16 */
+ SI dr;
+ } sfmt_sll3;
+ struct { /* e.g. slli $dr,$uimm5 */
+ SI dr;
+ } sfmt_slli;
+ struct { /* e.g. st $src1,@$src2 */
+ SI h_memory_src2;
+ USI h_memory_src2_idx;
+ } sfmt_st;
+ struct { /* e.g. st $src1,@($slo16,$src2) */
+ SI h_memory_add__DFLT_src2_slo16;
+ USI h_memory_add__DFLT_src2_slo16_idx;
+ } sfmt_st_d;
+ struct { /* e.g. stb $src1,@$src2 */
+ QI h_memory_src2;
+ USI h_memory_src2_idx;
+ } sfmt_stb;
+ struct { /* e.g. stb $src1,@($slo16,$src2) */
+ QI h_memory_add__DFLT_src2_slo16;
+ USI h_memory_add__DFLT_src2_slo16_idx;
+ } sfmt_stb_d;
+ struct { /* e.g. sth $src1,@$src2 */
+ HI h_memory_src2;
+ USI h_memory_src2_idx;
+ } sfmt_sth;
+ struct { /* e.g. sth $src1,@($slo16,$src2) */
+ HI h_memory_add__DFLT_src2_slo16;
+ USI h_memory_add__DFLT_src2_slo16_idx;
+ } sfmt_sth_d;
+ struct { /* e.g. st $src1,@+$src2 */
+ SI h_memory_new_src2;
+ USI h_memory_new_src2_idx;
+ SI src2;
+ } sfmt_st_plus;
+ struct { /* e.g. trap $uimm4 */
+ UQI h_bbpsw;
+ UQI h_bpsw;
+ USI h_cr_14;
+ USI h_cr_6;
+ UQI h_psw;
+ SI pc;
+ } sfmt_trap;
+ struct { /* e.g. unlock $src1,@$src2 */
+ BI h_lock;
+ SI h_memory_src2;
+ USI h_memory_src2_idx;
+ } sfmt_unlock;
+ struct { /* e.g. satb $dr,$sr */
+ SI dr;
+ } sfmt_satb;
+ struct { /* e.g. sat $dr,$sr */
+ SI dr;
+ } sfmt_sat;
+ struct { /* e.g. sadd */
+ DI h_accums_0;
+ } sfmt_sadd;
+ struct { /* e.g. macwu1 $src1,$src2 */
+ DI h_accums_1;
+ } sfmt_macwu1;
+ struct { /* e.g. msblo $src1,$src2 */
+ DI accum;
+ } sfmt_msblo;
+ struct { /* e.g. mulwu1 $src1,$src2 */
+ DI h_accums_1;
+ } sfmt_mulwu1;
+ struct { /* e.g. sc */
+ int empty;
+ } sfmt_sc;
+ } operands;
+ /* For conditionally written operands, bitmask of which ones were. */
+ int written;
+};
+
+/* Collection of various things for the trace handler to use. */
+
+typedef struct trace_record {
+ IADDR pc;
+ /* FIXME:wip */
+} TRACE_RECORD;
+
+#endif /* CPU_M32RXF_H */
--- /dev/null
+/* Simulator instruction decoder for m32rxf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU m32rxf
+#define WANT_CPU_M32RXF
+
+#include "sim-main.h"
+#include "sim-assert.h"
+
+/* Insn can't be executed in parallel.
+ Or is that "do NOt Pass to Air defense Radar"? :-) */
+#define NOPAR (-1)
+
+/* The instruction descriptor array.
+ This is computed at runtime. Space for it is not malloc'd to save a
+ teensy bit of cpu in the decoder. Moving it to malloc space is trivial
+ but won't be done until necessary (we don't currently support the runtime
+ addition of instructions nor an SMP machine with different cpus). */
+static IDESC m32rxf_insn_data[M32RXF_INSN_MAX];
+
+/* Commas between elements are contained in the macros.
+ Some of these are conditionally compiled out. */
+
+static const struct insn_sem m32rxf_insn_sem[] =
+{
+ { VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
+ { VIRTUAL_INSN_X_AFTER, M32RXF_INSN_X_AFTER, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
+ { VIRTUAL_INSN_X_BEFORE, M32RXF_INSN_X_BEFORE, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
+ { VIRTUAL_INSN_X_CTI_CHAIN, M32RXF_INSN_X_CTI_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
+ { VIRTUAL_INSN_X_CHAIN, M32RXF_INSN_X_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
+ { VIRTUAL_INSN_X_BEGIN, M32RXF_INSN_X_BEGIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
+ { M32R_INSN_ADD, M32RXF_INSN_ADD, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_ADD, M32RXF_INSN_WRITE_ADD },
+ { M32R_INSN_ADD3, M32RXF_INSN_ADD3, M32RXF_SFMT_ADD3, NOPAR, NOPAR },
+ { M32R_INSN_AND, M32RXF_INSN_AND, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_AND, M32RXF_INSN_WRITE_AND },
+ { M32R_INSN_AND3, M32RXF_INSN_AND3, M32RXF_SFMT_AND3, NOPAR, NOPAR },
+ { M32R_INSN_OR, M32RXF_INSN_OR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_OR, M32RXF_INSN_WRITE_OR },
+ { M32R_INSN_OR3, M32RXF_INSN_OR3, M32RXF_SFMT_OR3, NOPAR, NOPAR },
+ { M32R_INSN_XOR, M32RXF_INSN_XOR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_XOR, M32RXF_INSN_WRITE_XOR },
+ { M32R_INSN_XOR3, M32RXF_INSN_XOR3, M32RXF_SFMT_AND3, NOPAR, NOPAR },
+ { M32R_INSN_ADDI, M32RXF_INSN_ADDI, M32RXF_SFMT_ADDI, M32RXF_INSN_PAR_ADDI, M32RXF_INSN_WRITE_ADDI },
+ { M32R_INSN_ADDV, M32RXF_INSN_ADDV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_ADDV, M32RXF_INSN_WRITE_ADDV },
+ { M32R_INSN_ADDV3, M32RXF_INSN_ADDV3, M32RXF_SFMT_ADDV3, NOPAR, NOPAR },
+ { M32R_INSN_ADDX, M32RXF_INSN_ADDX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_ADDX, M32RXF_INSN_WRITE_ADDX },
+ { M32R_INSN_BC8, M32RXF_INSN_BC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BC8, M32RXF_INSN_WRITE_BC8 },
+ { M32R_INSN_BC24, M32RXF_INSN_BC24, M32RXF_SFMT_BC24, NOPAR, NOPAR },
+ { M32R_INSN_BEQ, M32RXF_INSN_BEQ, M32RXF_SFMT_BEQ, NOPAR, NOPAR },
+ { M32R_INSN_BEQZ, M32RXF_INSN_BEQZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
+ { M32R_INSN_BGEZ, M32RXF_INSN_BGEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
+ { M32R_INSN_BGTZ, M32RXF_INSN_BGTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
+ { M32R_INSN_BLEZ, M32RXF_INSN_BLEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
+ { M32R_INSN_BLTZ, M32RXF_INSN_BLTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
+ { M32R_INSN_BNEZ, M32RXF_INSN_BNEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
+ { M32R_INSN_BL8, M32RXF_INSN_BL8, M32RXF_SFMT_BL8, M32RXF_INSN_PAR_BL8, M32RXF_INSN_WRITE_BL8 },
+ { M32R_INSN_BL24, M32RXF_INSN_BL24, M32RXF_SFMT_BL24, NOPAR, NOPAR },
+ { M32R_INSN_BCL8, M32RXF_INSN_BCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BCL8, M32RXF_INSN_WRITE_BCL8 },
+ { M32R_INSN_BCL24, M32RXF_INSN_BCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR },
+ { M32R_INSN_BNC8, M32RXF_INSN_BNC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BNC8, M32RXF_INSN_WRITE_BNC8 },
+ { M32R_INSN_BNC24, M32RXF_INSN_BNC24, M32RXF_SFMT_BC24, NOPAR, NOPAR },
+ { M32R_INSN_BNE, M32RXF_INSN_BNE, M32RXF_SFMT_BEQ, NOPAR, NOPAR },
+ { M32R_INSN_BRA8, M32RXF_INSN_BRA8, M32RXF_SFMT_BRA8, M32RXF_INSN_PAR_BRA8, M32RXF_INSN_WRITE_BRA8 },
+ { M32R_INSN_BRA24, M32RXF_INSN_BRA24, M32RXF_SFMT_BRA24, NOPAR, NOPAR },
+ { M32R_INSN_BNCL8, M32RXF_INSN_BNCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BNCL8, M32RXF_INSN_WRITE_BNCL8 },
+ { M32R_INSN_BNCL24, M32RXF_INSN_BNCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR },
+ { M32R_INSN_CMP, M32RXF_INSN_CMP, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMP, M32RXF_INSN_WRITE_CMP },
+ { M32R_INSN_CMPI, M32RXF_INSN_CMPI, M32RXF_SFMT_CMPI, NOPAR, NOPAR },
+ { M32R_INSN_CMPU, M32RXF_INSN_CMPU, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPU, M32RXF_INSN_WRITE_CMPU },
+ { M32R_INSN_CMPUI, M32RXF_INSN_CMPUI, M32RXF_SFMT_CMPI, NOPAR, NOPAR },
+ { M32R_INSN_CMPEQ, M32RXF_INSN_CMPEQ, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPEQ, M32RXF_INSN_WRITE_CMPEQ },
+ { M32R_INSN_CMPZ, M32RXF_INSN_CMPZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_CMPZ, M32RXF_INSN_WRITE_CMPZ },
+ { M32R_INSN_DIV, M32RXF_INSN_DIV, M32RXF_SFMT_DIV, NOPAR, NOPAR },
+ { M32R_INSN_DIVU, M32RXF_INSN_DIVU, M32RXF_SFMT_DIV, NOPAR, NOPAR },
+ { M32R_INSN_REM, M32RXF_INSN_REM, M32RXF_SFMT_DIV, NOPAR, NOPAR },
+ { M32R_INSN_REMU, M32RXF_INSN_REMU, M32RXF_SFMT_DIV, NOPAR, NOPAR },
+ { M32R_INSN_DIVH, M32RXF_INSN_DIVH, M32RXF_SFMT_DIV, NOPAR, NOPAR },
+ { M32R_INSN_JC, M32RXF_INSN_JC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JC, M32RXF_INSN_WRITE_JC },
+ { M32R_INSN_JNC, M32RXF_INSN_JNC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JNC, M32RXF_INSN_WRITE_JNC },
+ { M32R_INSN_JL, M32RXF_INSN_JL, M32RXF_SFMT_JL, M32RXF_INSN_PAR_JL, M32RXF_INSN_WRITE_JL },
+ { M32R_INSN_JMP, M32RXF_INSN_JMP, M32RXF_SFMT_JMP, M32RXF_INSN_PAR_JMP, M32RXF_INSN_WRITE_JMP },
+ { M32R_INSN_LD, M32RXF_INSN_LD, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LD, M32RXF_INSN_WRITE_LD },
+ { M32R_INSN_LD_D, M32RXF_INSN_LD_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR },
+ { M32R_INSN_LDB, M32RXF_INSN_LDB, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LDB, M32RXF_INSN_WRITE_LDB },
+ { M32R_INSN_LDB_D, M32RXF_INSN_LDB_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR },
+ { M32R_INSN_LDH, M32RXF_INSN_LDH, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LDH, M32RXF_INSN_WRITE_LDH },
+ { M32R_INSN_LDH_D, M32RXF_INSN_LDH_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR },
+ { M32R_INSN_LDUB, M32RXF_INSN_LDUB, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LDUB, M32RXF_INSN_WRITE_LDUB },
+ { M32R_INSN_LDUB_D, M32RXF_INSN_LDUB_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR },
+ { M32R_INSN_LDUH, M32RXF_INSN_LDUH, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LDUH, M32RXF_INSN_WRITE_LDUH },
+ { M32R_INSN_LDUH_D, M32RXF_INSN_LDUH_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR },
+ { M32R_INSN_LD_PLUS, M32RXF_INSN_LD_PLUS, M32RXF_SFMT_LD_PLUS, M32RXF_INSN_PAR_LD_PLUS, M32RXF_INSN_WRITE_LD_PLUS },
+ { M32R_INSN_LD24, M32RXF_INSN_LD24, M32RXF_SFMT_LD24, NOPAR, NOPAR },
+ { M32R_INSN_LDI8, M32RXF_INSN_LDI8, M32RXF_SFMT_LDI8, M32RXF_INSN_PAR_LDI8, M32RXF_INSN_WRITE_LDI8 },
+ { M32R_INSN_LDI16, M32RXF_INSN_LDI16, M32RXF_SFMT_LDI16, NOPAR, NOPAR },
+ { M32R_INSN_LOCK, M32RXF_INSN_LOCK, M32RXF_SFMT_LOCK, M32RXF_INSN_PAR_LOCK, M32RXF_INSN_WRITE_LOCK },
+ { M32R_INSN_MACHI_A, M32RXF_INSN_MACHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACHI_A, M32RXF_INSN_WRITE_MACHI_A },
+ { M32R_INSN_MACLO_A, M32RXF_INSN_MACLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACLO_A, M32RXF_INSN_WRITE_MACLO_A },
+ { M32R_INSN_MACWHI_A, M32RXF_INSN_MACWHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWHI_A, M32RXF_INSN_WRITE_MACWHI_A },
+ { M32R_INSN_MACWLO_A, M32RXF_INSN_MACWLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWLO_A, M32RXF_INSN_WRITE_MACWLO_A },
+ { M32R_INSN_MUL, M32RXF_INSN_MUL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_MUL, M32RXF_INSN_WRITE_MUL },
+ { M32R_INSN_MULHI_A, M32RXF_INSN_MULHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULHI_A, M32RXF_INSN_WRITE_MULHI_A },
+ { M32R_INSN_MULLO_A, M32RXF_INSN_MULLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULLO_A, M32RXF_INSN_WRITE_MULLO_A },
+ { M32R_INSN_MULWHI_A, M32RXF_INSN_MULWHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWHI_A, M32RXF_INSN_WRITE_MULWHI_A },
+ { M32R_INSN_MULWLO_A, M32RXF_INSN_MULWLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWLO_A, M32RXF_INSN_WRITE_MULWLO_A },
+ { M32R_INSN_MV, M32RXF_INSN_MV, M32RXF_SFMT_MV, M32RXF_INSN_PAR_MV, M32RXF_INSN_WRITE_MV },
+ { M32R_INSN_MVFACHI_A, M32RXF_INSN_MVFACHI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACHI_A, M32RXF_INSN_WRITE_MVFACHI_A },
+ { M32R_INSN_MVFACLO_A, M32RXF_INSN_MVFACLO_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACLO_A, M32RXF_INSN_WRITE_MVFACLO_A },
+ { M32R_INSN_MVFACMI_A, M32RXF_INSN_MVFACMI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACMI_A, M32RXF_INSN_WRITE_MVFACMI_A },
+ { M32R_INSN_MVFC, M32RXF_INSN_MVFC, M32RXF_SFMT_MVFC, M32RXF_INSN_PAR_MVFC, M32RXF_INSN_WRITE_MVFC },
+ { M32R_INSN_MVTACHI_A, M32RXF_INSN_MVTACHI_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACHI_A, M32RXF_INSN_WRITE_MVTACHI_A },
+ { M32R_INSN_MVTACLO_A, M32RXF_INSN_MVTACLO_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACLO_A, M32RXF_INSN_WRITE_MVTACLO_A },
+ { M32R_INSN_MVTC, M32RXF_INSN_MVTC, M32RXF_SFMT_MVTC, M32RXF_INSN_PAR_MVTC, M32RXF_INSN_WRITE_MVTC },
+ { M32R_INSN_NEG, M32RXF_INSN_NEG, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NEG, M32RXF_INSN_WRITE_NEG },
+ { M32R_INSN_NOP, M32RXF_INSN_NOP, M32RXF_SFMT_NOP, M32RXF_INSN_PAR_NOP, M32RXF_INSN_WRITE_NOP },
+ { M32R_INSN_NOT, M32RXF_INSN_NOT, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NOT, M32RXF_INSN_WRITE_NOT },
+ { M32R_INSN_RAC_DSI, M32RXF_INSN_RAC_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RAC_DSI, M32RXF_INSN_WRITE_RAC_DSI },
+ { M32R_INSN_RACH_DSI, M32RXF_INSN_RACH_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RACH_DSI, M32RXF_INSN_WRITE_RACH_DSI },
+ { M32R_INSN_RTE, M32RXF_INSN_RTE, M32RXF_SFMT_RTE, M32RXF_INSN_PAR_RTE, M32RXF_INSN_WRITE_RTE },
+ { M32R_INSN_SETH, M32RXF_INSN_SETH, M32RXF_SFMT_SETH, NOPAR, NOPAR },
+ { M32R_INSN_SLL, M32RXF_INSN_SLL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SLL, M32RXF_INSN_WRITE_SLL },
+ { M32R_INSN_SLL3, M32RXF_INSN_SLL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR },
+ { M32R_INSN_SLLI, M32RXF_INSN_SLLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SLLI, M32RXF_INSN_WRITE_SLLI },
+ { M32R_INSN_SRA, M32RXF_INSN_SRA, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRA, M32RXF_INSN_WRITE_SRA },
+ { M32R_INSN_SRA3, M32RXF_INSN_SRA3, M32RXF_SFMT_SLL3, NOPAR, NOPAR },
+ { M32R_INSN_SRAI, M32RXF_INSN_SRAI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRAI, M32RXF_INSN_WRITE_SRAI },
+ { M32R_INSN_SRL, M32RXF_INSN_SRL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRL, M32RXF_INSN_WRITE_SRL },
+ { M32R_INSN_SRL3, M32RXF_INSN_SRL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR },
+ { M32R_INSN_SRLI, M32RXF_INSN_SRLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRLI, M32RXF_INSN_WRITE_SRLI },
+ { M32R_INSN_ST, M32RXF_INSN_ST, M32RXF_SFMT_ST, M32RXF_INSN_PAR_ST, M32RXF_INSN_WRITE_ST },
+ { M32R_INSN_ST_D, M32RXF_INSN_ST_D, M32RXF_SFMT_ST_D, NOPAR, NOPAR },
+ { M32R_INSN_STB, M32RXF_INSN_STB, M32RXF_SFMT_STB, M32RXF_INSN_PAR_STB, M32RXF_INSN_WRITE_STB },
+ { M32R_INSN_STB_D, M32RXF_INSN_STB_D, M32RXF_SFMT_STB_D, NOPAR, NOPAR },
+ { M32R_INSN_STH, M32RXF_INSN_STH, M32RXF_SFMT_STH, M32RXF_INSN_PAR_STH, M32RXF_INSN_WRITE_STH },
+ { M32R_INSN_STH_D, M32RXF_INSN_STH_D, M32RXF_SFMT_STH_D, NOPAR, NOPAR },
+ { M32R_INSN_ST_PLUS, M32RXF_INSN_ST_PLUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_PLUS, M32RXF_INSN_WRITE_ST_PLUS },
+ { M32R_INSN_ST_MINUS, M32RXF_INSN_ST_MINUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_MINUS, M32RXF_INSN_WRITE_ST_MINUS },
+ { M32R_INSN_SUB, M32RXF_INSN_SUB, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SUB, M32RXF_INSN_WRITE_SUB },
+ { M32R_INSN_SUBV, M32RXF_INSN_SUBV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_SUBV, M32RXF_INSN_WRITE_SUBV },
+ { M32R_INSN_SUBX, M32RXF_INSN_SUBX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_SUBX, M32RXF_INSN_WRITE_SUBX },
+ { M32R_INSN_TRAP, M32RXF_INSN_TRAP, M32RXF_SFMT_TRAP, M32RXF_INSN_PAR_TRAP, M32RXF_INSN_WRITE_TRAP },
+ { M32R_INSN_UNLOCK, M32RXF_INSN_UNLOCK, M32RXF_SFMT_UNLOCK, M32RXF_INSN_PAR_UNLOCK, M32RXF_INSN_WRITE_UNLOCK },
+ { M32R_INSN_SATB, M32RXF_INSN_SATB, M32RXF_SFMT_SATB, NOPAR, NOPAR },
+ { M32R_INSN_SATH, M32RXF_INSN_SATH, M32RXF_SFMT_SATB, NOPAR, NOPAR },
+ { M32R_INSN_SAT, M32RXF_INSN_SAT, M32RXF_SFMT_SAT, NOPAR, NOPAR },
+ { M32R_INSN_PCMPBZ, M32RXF_INSN_PCMPBZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_PCMPBZ, M32RXF_INSN_WRITE_PCMPBZ },
+ { M32R_INSN_SADD, M32RXF_INSN_SADD, M32RXF_SFMT_SADD, M32RXF_INSN_PAR_SADD, M32RXF_INSN_WRITE_SADD },
+ { M32R_INSN_MACWU1, M32RXF_INSN_MACWU1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACWU1, M32RXF_INSN_WRITE_MACWU1 },
+ { M32R_INSN_MSBLO, M32RXF_INSN_MSBLO, M32RXF_SFMT_MSBLO, M32RXF_INSN_PAR_MSBLO, M32RXF_INSN_WRITE_MSBLO },
+ { M32R_INSN_MULWU1, M32RXF_INSN_MULWU1, M32RXF_SFMT_MULWU1, M32RXF_INSN_PAR_MULWU1, M32RXF_INSN_WRITE_MULWU1 },
+ { M32R_INSN_MACLH1, M32RXF_INSN_MACLH1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACLH1, M32RXF_INSN_WRITE_MACLH1 },
+ { M32R_INSN_SC, M32RXF_INSN_SC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SC, M32RXF_INSN_WRITE_SC },
+ { M32R_INSN_SNC, M32RXF_INSN_SNC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SNC, M32RXF_INSN_WRITE_SNC },
+};
+
+static const struct insn_sem m32rxf_insn_sem_invalid = {
+ VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR
+};
+
+/* Initialize an IDESC from the compile-time computable parts. */
+
+static INLINE void
+init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
+{
+ const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
+
+ id->num = t->index;
+ id->sfmt = t->sfmt;
+ if ((int) t->type <= 0)
+ id->idata = & cgen_virtual_insn_table[- (int) t->type];
+ else
+ id->idata = & insn_table[t->type];
+ id->attrs = CGEN_INSN_ATTRS (id->idata);
+ /* Oh my god, a magic number. */
+ id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
+
+#if WITH_PROFILE_MODEL_P
+ id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
+ {
+ SIM_DESC sd = CPU_STATE (cpu);
+ SIM_ASSERT (t->index == id->timing->num);
+ }
+#endif
+
+ /* Semantic pointers are initialized elsewhere. */
+}
+
+/* Initialize the instruction descriptor table. */
+
+void
+m32rxf_init_idesc_table (SIM_CPU *cpu)
+{
+ IDESC *id,*tabend;
+ const struct insn_sem *t,*tend;
+ int tabsize = M32RXF_INSN_MAX;
+ IDESC *table = m32rxf_insn_data;
+
+ memset (table, 0, tabsize * sizeof (IDESC));
+
+ /* First set all entries to the `invalid insn'. */
+ t = & m32rxf_insn_sem_invalid;
+ for (id = table, tabend = table + tabsize; id < tabend; ++id)
+ init_idesc (cpu, id, t);
+
+ /* Now fill in the values for the chosen cpu. */
+ for (t = m32rxf_insn_sem, tend = t + sizeof (m32rxf_insn_sem) / sizeof (*t);
+ t != tend; ++t)
+ {
+ init_idesc (cpu, & table[t->index], t);
+ if (t->par_index != NOPAR)
+ {
+ init_idesc (cpu, &table[t->par_index], t);
+ table[t->index].par_idesc = &table[t->par_index];
+ }
+ if (t->par_index != NOPAR)
+ {
+ init_idesc (cpu, &table[t->write_index], t);
+ table[t->par_index].par_idesc = &table[t->write_index];
+ }
+ }
+
+ /* Link the IDESC table into the cpu. */
+ CPU_IDESC (cpu) = table;
+}
+
+/* Given an instruction, return a pointer to its IDESC entry. */
+
+const IDESC *
+m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
+ CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
+ ARGBUF *abuf)
+{
+ /* Result of decoder. */
+ M32RXF_INSN_TYPE itype;
+
+ {
+ CGEN_INSN_INT insn = base_insn;
+
+ {
+ unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = M32RXF_INSN_SUBV; goto extract_sfmt_addv;
+ case 1 : itype = M32RXF_INSN_SUBX; goto extract_sfmt_addx;
+ case 2 : itype = M32RXF_INSN_SUB; goto extract_sfmt_add;
+ case 3 : itype = M32RXF_INSN_NEG; goto extract_sfmt_mv;
+ case 4 : itype = M32RXF_INSN_CMP; goto extract_sfmt_cmp;
+ case 5 : itype = M32RXF_INSN_CMPU; goto extract_sfmt_cmp;
+ case 6 : itype = M32RXF_INSN_CMPEQ; goto extract_sfmt_cmp;
+ case 7 :
+ {
+ unsigned int val = (((insn >> 8) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = M32RXF_INSN_CMPZ; goto extract_sfmt_cmpz;
+ case 3 : itype = M32RXF_INSN_PCMPBZ; goto extract_sfmt_cmpz;
+ default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 8 : itype = M32RXF_INSN_ADDV; goto extract_sfmt_addv;
+ case 9 : itype = M32RXF_INSN_ADDX; goto extract_sfmt_addx;
+ case 10 : itype = M32RXF_INSN_ADD; goto extract_sfmt_add;
+ case 11 : itype = M32RXF_INSN_NOT; goto extract_sfmt_mv;
+ case 12 : itype = M32RXF_INSN_AND; goto extract_sfmt_add;
+ case 13 : itype = M32RXF_INSN_XOR; goto extract_sfmt_add;
+ case 14 : itype = M32RXF_INSN_OR; goto extract_sfmt_add;
+ case 16 : itype = M32RXF_INSN_SRL; goto extract_sfmt_add;
+ case 18 : itype = M32RXF_INSN_SRA; goto extract_sfmt_add;
+ case 20 : itype = M32RXF_INSN_SLL; goto extract_sfmt_add;
+ case 22 : itype = M32RXF_INSN_MUL; goto extract_sfmt_add;
+ case 24 : itype = M32RXF_INSN_MV; goto extract_sfmt_mv;
+ case 25 : itype = M32RXF_INSN_MVFC; goto extract_sfmt_mvfc;
+ case 26 : itype = M32RXF_INSN_MVTC; goto extract_sfmt_mvtc;
+ case 28 :
+ {
+ unsigned int val = (((insn >> 8) & (15 << 0)));
+ switch (val)
+ {
+ case 12 : itype = M32RXF_INSN_JC; goto extract_sfmt_jc;
+ case 13 : itype = M32RXF_INSN_JNC; goto extract_sfmt_jc;
+ case 14 : itype = M32RXF_INSN_JL; goto extract_sfmt_jl;
+ case 15 : itype = M32RXF_INSN_JMP; goto extract_sfmt_jmp;
+ default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 29 : itype = M32RXF_INSN_RTE; goto extract_sfmt_rte;
+ case 31 : itype = M32RXF_INSN_TRAP; goto extract_sfmt_trap;
+ case 32 : itype = M32RXF_INSN_STB; goto extract_sfmt_stb;
+ case 34 : itype = M32RXF_INSN_STH; goto extract_sfmt_sth;
+ case 36 : itype = M32RXF_INSN_ST; goto extract_sfmt_st;
+ case 37 : itype = M32RXF_INSN_UNLOCK; goto extract_sfmt_unlock;
+ case 38 : itype = M32RXF_INSN_ST_PLUS; goto extract_sfmt_st_plus;
+ case 39 : itype = M32RXF_INSN_ST_MINUS; goto extract_sfmt_st_plus;
+ case 40 : itype = M32RXF_INSN_LDB; goto extract_sfmt_ld;
+ case 41 : itype = M32RXF_INSN_LDUB; goto extract_sfmt_ld;
+ case 42 : itype = M32RXF_INSN_LDH; goto extract_sfmt_ld;
+ case 43 : itype = M32RXF_INSN_LDUH; goto extract_sfmt_ld;
+ case 44 : itype = M32RXF_INSN_LD; goto extract_sfmt_ld;
+ case 45 : itype = M32RXF_INSN_LOCK; goto extract_sfmt_lock;
+ case 46 : itype = M32RXF_INSN_LD_PLUS; goto extract_sfmt_ld_plus;
+ case 48 : /* fall through */
+ case 56 : itype = M32RXF_INSN_MULHI_A; goto extract_sfmt_mulhi_a;
+ case 49 : /* fall through */
+ case 57 : itype = M32RXF_INSN_MULLO_A; goto extract_sfmt_mulhi_a;
+ case 50 : /* fall through */
+ case 58 : itype = M32RXF_INSN_MULWHI_A; goto extract_sfmt_mulhi_a;
+ case 51 : /* fall through */
+ case 59 : itype = M32RXF_INSN_MULWLO_A; goto extract_sfmt_mulhi_a;
+ case 52 : /* fall through */
+ case 60 : itype = M32RXF_INSN_MACHI_A; goto extract_sfmt_machi_a;
+ case 53 : /* fall through */
+ case 61 : itype = M32RXF_INSN_MACLO_A; goto extract_sfmt_machi_a;
+ case 54 : /* fall through */
+ case 62 : itype = M32RXF_INSN_MACWHI_A; goto extract_sfmt_machi_a;
+ case 55 : /* fall through */
+ case 63 : itype = M32RXF_INSN_MACWLO_A; goto extract_sfmt_machi_a;
+ case 64 : /* fall through */
+ case 65 : /* fall through */
+ case 66 : /* fall through */
+ case 67 : /* fall through */
+ case 68 : /* fall through */
+ case 69 : /* fall through */
+ case 70 : /* fall through */
+ case 71 : /* fall through */
+ case 72 : /* fall through */
+ case 73 : /* fall through */
+ case 74 : /* fall through */
+ case 75 : /* fall through */
+ case 76 : /* fall through */
+ case 77 : /* fall through */
+ case 78 : /* fall through */
+ case 79 : itype = M32RXF_INSN_ADDI; goto extract_sfmt_addi;
+ case 80 : /* fall through */
+ case 81 : itype = M32RXF_INSN_SRLI; goto extract_sfmt_slli;
+ case 82 : /* fall through */
+ case 83 : itype = M32RXF_INSN_SRAI; goto extract_sfmt_slli;
+ case 84 : /* fall through */
+ case 85 : itype = M32RXF_INSN_SLLI; goto extract_sfmt_slli;
+ case 87 :
+ {
+ unsigned int val = (((insn >> 0) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : itype = M32RXF_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a;
+ case 1 : itype = M32RXF_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a;
+ default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 88 : itype = M32RXF_INSN_RACH_DSI; goto extract_sfmt_rac_dsi;
+ case 89 : itype = M32RXF_INSN_RAC_DSI; goto extract_sfmt_rac_dsi;
+ case 90 : itype = M32RXF_INSN_MULWU1; goto extract_sfmt_mulwu1;
+ case 91 : itype = M32RXF_INSN_MACWU1; goto extract_sfmt_macwu1;
+ case 92 : itype = M32RXF_INSN_MACLH1; goto extract_sfmt_macwu1;
+ case 93 : itype = M32RXF_INSN_MSBLO; goto extract_sfmt_msblo;
+ case 94 : itype = M32RXF_INSN_SADD; goto extract_sfmt_sadd;
+ case 95 :
+ {
+ unsigned int val = (((insn >> 0) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : itype = M32RXF_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a;
+ case 1 : itype = M32RXF_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a;
+ case 2 : itype = M32RXF_INSN_MVFACMI_A; goto extract_sfmt_mvfachi_a;
+ default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 96 : /* fall through */
+ case 97 : /* fall through */
+ case 98 : /* fall through */
+ case 99 : /* fall through */
+ case 100 : /* fall through */
+ case 101 : /* fall through */
+ case 102 : /* fall through */
+ case 103 : /* fall through */
+ case 104 : /* fall through */
+ case 105 : /* fall through */
+ case 106 : /* fall through */
+ case 107 : /* fall through */
+ case 108 : /* fall through */
+ case 109 : /* fall through */
+ case 110 : /* fall through */
+ case 111 : itype = M32RXF_INSN_LDI8; goto extract_sfmt_ldi8;
+ case 112 :
+ {
+ unsigned int val = (((insn >> 8) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = M32RXF_INSN_NOP; goto extract_sfmt_nop;
+ case 4 : itype = M32RXF_INSN_SC; goto extract_sfmt_sc;
+ case 5 : itype = M32RXF_INSN_SNC; goto extract_sfmt_sc;
+ case 8 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8;
+ case 9 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8;
+ case 12 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8;
+ case 13 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8;
+ case 14 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8;
+ case 15 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8;
+ default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 113 : /* fall through */
+ case 114 : /* fall through */
+ case 115 : /* fall through */
+ case 116 : /* fall through */
+ case 117 : /* fall through */
+ case 118 : /* fall through */
+ case 119 : /* fall through */
+ case 120 : /* fall through */
+ case 121 : /* fall through */
+ case 122 : /* fall through */
+ case 123 : /* fall through */
+ case 124 : /* fall through */
+ case 125 : /* fall through */
+ case 126 : /* fall through */
+ case 127 :
+ {
+ unsigned int val = (((insn >> 8) & (15 << 0)));
+ switch (val)
+ {
+ case 8 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8;
+ case 9 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8;
+ case 12 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8;
+ case 13 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8;
+ case 14 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8;
+ case 15 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8;
+ default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 132 : itype = M32RXF_INSN_CMPI; goto extract_sfmt_cmpi;
+ case 133 : itype = M32RXF_INSN_CMPUI; goto extract_sfmt_cmpi;
+ case 134 :
+ {
+ unsigned int val;
+ /* Must fetch more bits. */
+ insn = GETIMEMUHI (current_cpu, pc + 2);
+ val = (((insn >> 12) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ {
+ unsigned int val = (((insn >> 8) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = M32RXF_INSN_SAT; goto extract_sfmt_sat;
+ case 2 : itype = M32RXF_INSN_SATH; goto extract_sfmt_satb;
+ case 3 : itype = M32RXF_INSN_SATB; goto extract_sfmt_satb;
+ default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 136 : itype = M32RXF_INSN_ADDV3; goto extract_sfmt_addv3;
+ case 138 : itype = M32RXF_INSN_ADD3; goto extract_sfmt_add3;
+ case 140 : itype = M32RXF_INSN_AND3; goto extract_sfmt_and3;
+ case 141 : itype = M32RXF_INSN_XOR3; goto extract_sfmt_and3;
+ case 142 : itype = M32RXF_INSN_OR3; goto extract_sfmt_or3;
+ case 144 :
+ {
+ unsigned int val;
+ /* Must fetch more bits. */
+ insn = GETIMEMUHI (current_cpu, pc + 2);
+ val = (((insn >> 12) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ {
+ unsigned int val = (((insn >> 8) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ {
+ unsigned int val = (((insn >> 4) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = M32RXF_INSN_DIV; goto extract_sfmt_div;
+ case 1 : itype = M32RXF_INSN_DIVH; goto extract_sfmt_div;
+ default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 145 : itype = M32RXF_INSN_DIVU; goto extract_sfmt_div;
+ case 146 : itype = M32RXF_INSN_REM; goto extract_sfmt_div;
+ case 147 : itype = M32RXF_INSN_REMU; goto extract_sfmt_div;
+ case 152 : itype = M32RXF_INSN_SRL3; goto extract_sfmt_sll3;
+ case 154 : itype = M32RXF_INSN_SRA3; goto extract_sfmt_sll3;
+ case 156 : itype = M32RXF_INSN_SLL3; goto extract_sfmt_sll3;
+ case 159 : itype = M32RXF_INSN_LDI16; goto extract_sfmt_ldi16;
+ case 160 : itype = M32RXF_INSN_STB_D; goto extract_sfmt_stb_d;
+ case 162 : itype = M32RXF_INSN_STH_D; goto extract_sfmt_sth_d;
+ case 164 : itype = M32RXF_INSN_ST_D; goto extract_sfmt_st_d;
+ case 168 : itype = M32RXF_INSN_LDB_D; goto extract_sfmt_ld_d;
+ case 169 : itype = M32RXF_INSN_LDUB_D; goto extract_sfmt_ld_d;
+ case 170 : itype = M32RXF_INSN_LDH_D; goto extract_sfmt_ld_d;
+ case 171 : itype = M32RXF_INSN_LDUH_D; goto extract_sfmt_ld_d;
+ case 172 : itype = M32RXF_INSN_LD_D; goto extract_sfmt_ld_d;
+ case 176 : itype = M32RXF_INSN_BEQ; goto extract_sfmt_beq;
+ case 177 : itype = M32RXF_INSN_BNE; goto extract_sfmt_beq;
+ case 184 : itype = M32RXF_INSN_BEQZ; goto extract_sfmt_beqz;
+ case 185 : itype = M32RXF_INSN_BNEZ; goto extract_sfmt_beqz;
+ case 186 : itype = M32RXF_INSN_BLTZ; goto extract_sfmt_beqz;
+ case 187 : itype = M32RXF_INSN_BGEZ; goto extract_sfmt_beqz;
+ case 188 : itype = M32RXF_INSN_BLEZ; goto extract_sfmt_beqz;
+ case 189 : itype = M32RXF_INSN_BGTZ; goto extract_sfmt_beqz;
+ case 220 : itype = M32RXF_INSN_SETH; goto extract_sfmt_seth;
+ case 224 : /* fall through */
+ case 225 : /* fall through */
+ case 226 : /* fall through */
+ case 227 : /* fall through */
+ case 228 : /* fall through */
+ case 229 : /* fall through */
+ case 230 : /* fall through */
+ case 231 : /* fall through */
+ case 232 : /* fall through */
+ case 233 : /* fall through */
+ case 234 : /* fall through */
+ case 235 : /* fall through */
+ case 236 : /* fall through */
+ case 237 : /* fall through */
+ case 238 : /* fall through */
+ case 239 : itype = M32RXF_INSN_LD24; goto extract_sfmt_ld24;
+ case 240 : /* fall through */
+ case 241 : /* fall through */
+ case 242 : /* fall through */
+ case 243 : /* fall through */
+ case 244 : /* fall through */
+ case 245 : /* fall through */
+ case 246 : /* fall through */
+ case 247 : /* fall through */
+ case 248 : /* fall through */
+ case 249 : /* fall through */
+ case 250 : /* fall through */
+ case 251 : /* fall through */
+ case 252 : /* fall through */
+ case 253 : /* fall through */
+ case 254 : /* fall through */
+ case 255 :
+ {
+ unsigned int val = (((insn >> 8) & (15 << 0)));
+ switch (val)
+ {
+ case 8 : itype = M32RXF_INSN_BCL24; goto extract_sfmt_bcl24;
+ case 9 : itype = M32RXF_INSN_BNCL24; goto extract_sfmt_bcl24;
+ case 12 : itype = M32RXF_INSN_BC24; goto extract_sfmt_bc24;
+ case 13 : itype = M32RXF_INSN_BNC24; goto extract_sfmt_bc24;
+ case 14 : itype = M32RXF_INSN_BL24; goto extract_sfmt_bl24;
+ case 15 : itype = M32RXF_INSN_BRA24; goto extract_sfmt_bra24;
+ default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ }
+
+ /* The instruction has been decoded, now extract the fields. */
+
+ extract_sfmt_empty:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ FLD (i_sr) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_dr) = f_r1;
+ FLD (in_sr) = f_r2;
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add3:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add3.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+ f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_simm16) = f_simm16;
+ FLD (i_sr) = & CPU (h_gr)[f_r2];
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_sr) = f_r2;
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and3:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_and3.f
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_uimm16;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+ f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_uimm16) = f_uimm16;
+ FLD (i_sr) = & CPU (h_gr)[f_r2];
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_sr) = f_r2;
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_or3:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_and3.f
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_uimm16;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+ f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_uimm16) = f_uimm16;
+ FLD (i_sr) = & CPU (h_gr)[f_r2];
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_sr) = f_r2;
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addi:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addi.f
+ UINT f_r1;
+ INT f_simm8;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_simm8) = f_simm8;
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_dr) = f_r1;
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addv:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ FLD (i_sr) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_dr) = f_r1;
+ FLD (in_sr) = f_r2;
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addv3:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add3.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+ f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_simm16) = f_simm16;
+ FLD (i_sr) = & CPU (h_gr)[f_r2];
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_sr) = f_r2;
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addx:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ FLD (i_sr) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_dr) = f_r1;
+ FLD (in_sr) = f_r2;
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bc8:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl8.f
+ SI f_disp8;
+
+ f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_disp8) = f_disp8;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bc24:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl24.f
+ SI f_disp24;
+
+ f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_disp24) = f_disp24;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_beq:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_beq.f
+ UINT f_r1;
+ UINT f_r2;
+ SI f_disp16;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+ f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_disp16) = f_disp16;
+ FLD (i_src1) = & CPU (h_gr)[f_r1];
+ FLD (i_src2) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src1) = f_r1;
+ FLD (in_src2) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_beqz:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_beq.f
+ UINT f_r2;
+ SI f_disp16;
+
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+ f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_disp16) = f_disp16;
+ FLD (i_src2) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src2) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bl8:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl8.f
+ SI f_disp8;
+
+ f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_disp8) = f_disp8;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_h_gr_14) = 14;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bl24:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl24.f
+ SI f_disp24;
+
+ f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_disp24) = f_disp24;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_h_gr_14) = 14;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bcl8:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl8.f
+ SI f_disp8;
+
+ f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_disp8) = f_disp8;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_h_gr_14) = 14;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bcl24:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl24.f
+ SI f_disp24;
+
+ f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_disp24) = f_disp24;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_h_gr_14) = 14;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bra8:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl8.f
+ SI f_disp8;
+
+ f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_disp8) = f_disp8;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bra24:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl24.f
+ SI f_disp24;
+
+ f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_disp24) = f_disp24;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_src1) = & CPU (h_gr)[f_r1];
+ FLD (i_src2) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src1) = f_r1;
+ FLD (in_src2) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmpi:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_d.f
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+ f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_simm16) = f_simm16;
+ FLD (i_src2) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src2) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmpz:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ UINT f_r2;
+
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_src2) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src2) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_div:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ FLD (i_sr) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_dr) = f_r1;
+ FLD (in_sr) = f_r2;
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jc:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+ UINT f_r2;
+
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_sr) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_sr) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jl:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_jl.f
+ UINT f_r2;
+
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_sr) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_sr) = f_r2;
+ FLD (out_h_gr_14) = 14;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jmp:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+ UINT f_r2;
+
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_sr) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_sr) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_sr) = & CPU (h_gr)[f_r2];
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_sr) = f_r2;
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_d:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add3.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+ f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_simm16) = f_simm16;
+ FLD (i_sr) = & CPU (h_gr)[f_r2];
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_sr) = f_r2;
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld_plus:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_sr) = & CPU (h_gr)[f_r2];
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_sr) = f_r2;
+ FLD (out_dr) = f_r1;
+ FLD (out_sr) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ld24:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld24.f
+ UINT f_r1;
+ UINT f_uimm24;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_uimm24) = f_uimm24;
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldi8:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addi.f
+ UINT f_r1;
+ INT f_simm8;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_simm8) = f_simm8;
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldi16:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add3.f
+ UINT f_r1;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_simm16) = f_simm16;
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lock:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_sr) = & CPU (h_gr)[f_r2];
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_sr) = f_r2;
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_machi_a:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+ UINT f_r1;
+ UINT f_acc;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_acc) = f_acc;
+ FLD (i_src1) = & CPU (h_gr)[f_r1];
+ FLD (i_src2) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src1) = f_r1;
+ FLD (in_src2) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mulhi_a:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+ UINT f_r1;
+ UINT f_acc;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_acc) = f_acc;
+ FLD (i_src1) = & CPU (h_gr)[f_r1];
+ FLD (i_src2) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src1) = f_r1;
+ FLD (in_src2) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mv:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_sr) = & CPU (h_gr)[f_r2];
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_sr) = f_r2;
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mvfachi_a:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+ UINT f_r1;
+ UINT f_accs;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_accs) = f_accs;
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mvfc:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mvfc.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mvtachi_a:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
+ UINT f_r1;
+ UINT f_accs;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_accs) = f_accs;
+ FLD (i_src1) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "src1 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src1) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mvtc:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r1) = f_r1;
+ FLD (i_sr) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_sr) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_nop:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_rac_dsi:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_rac_dsi.f
+ UINT f_accd;
+ UINT f_accs;
+ SI f_imm1;
+
+ f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2);
+ f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
+ f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_accs) = f_accs;
+ FLD (f_imm1) = f_imm1;
+ FLD (f_accd) = f_accd;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_rte:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_seth:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_seth.f
+ UINT f_r1;
+ UINT f_hi16;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_hi16) = f_hi16;
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sll3:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add3.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+ f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_simm16) = f_simm16;
+ FLD (i_sr) = & CPU (h_gr)[f_r2];
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_sr) = f_r2;
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_slli:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_slli.f
+ UINT f_r1;
+ UINT f_uimm5;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_uimm5) = f_uimm5;
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_dr) = f_r1;
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_st:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_src1) = & CPU (h_gr)[f_r1];
+ FLD (i_src2) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src1) = f_r1;
+ FLD (in_src2) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_st_d:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_d.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+ f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_simm16) = f_simm16;
+ FLD (i_src1) = & CPU (h_gr)[f_r1];
+ FLD (i_src2) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src1) = f_r1;
+ FLD (in_src2) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stb:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_src1) = & CPU (h_gr)[f_r1];
+ FLD (i_src2) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src1) = f_r1;
+ FLD (in_src2) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stb_d:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_d.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+ f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_simm16) = f_simm16;
+ FLD (i_src1) = & CPU (h_gr)[f_r1];
+ FLD (i_src2) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src1) = f_r1;
+ FLD (in_src2) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sth:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_src1) = & CPU (h_gr)[f_r1];
+ FLD (i_src2) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src1) = f_r1;
+ FLD (in_src2) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sth_d:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_d.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+ f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_simm16) = f_simm16;
+ FLD (i_src1) = & CPU (h_gr)[f_r1];
+ FLD (i_src2) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src1) = f_r1;
+ FLD (in_src2) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_st_plus:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_src1) = & CPU (h_gr)[f_r1];
+ FLD (i_src2) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src1) = f_r1;
+ FLD (in_src2) = f_r2;
+ FLD (out_src2) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_trap:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_trap.f
+ UINT f_uimm4;
+
+ f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_uimm4) = f_uimm4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_unlock:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_src1) = & CPU (h_gr)[f_r1];
+ FLD (i_src2) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src1) = f_r1;
+ FLD (in_src2) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_satb:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_sr) = & CPU (h_gr)[f_r2];
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_sr) = f_r2;
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sat:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_sr) = & CPU (h_gr)[f_r2];
+ FLD (i_dr) = & CPU (h_gr)[f_r1];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_sr) = f_r2;
+ FLD (out_dr) = f_r1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sadd:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_macwu1:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_src1) = & CPU (h_gr)[f_r1];
+ FLD (i_src2) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src1) = f_r1;
+ FLD (in_src2) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_msblo:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_src1) = & CPU (h_gr)[f_r1];
+ FLD (i_src2) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src1) = f_r1;
+ FLD (in_src2) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mulwu1:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+ f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_src1) = & CPU (h_gr)[f_r1];
+ FLD (i_src2) = & CPU (h_gr)[f_r2];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src1) = f_r1;
+ FLD (in_src2) = f_r2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sc:
+ {
+ const IDESC *idesc = &m32rxf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+}
--- /dev/null
+/* Decode header for m32rxf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef M32RXF_DECODE_H
+#define M32RXF_DECODE_H
+
+extern const IDESC *m32rxf_decode (SIM_CPU *, IADDR,
+ CGEN_INSN_INT, CGEN_INSN_INT,
+ ARGBUF *);
+extern void m32rxf_init_idesc_table (SIM_CPU *);
+extern void m32rxf_sem_init_idesc_table (SIM_CPU *);
+extern void m32rxf_semf_init_idesc_table (SIM_CPU *);
+
+/* Enum declaration for instructions in cpu family m32rxf. */
+typedef enum m32rxf_insn_type {
+ M32RXF_INSN_X_INVALID, M32RXF_INSN_X_AFTER, M32RXF_INSN_X_BEFORE, M32RXF_INSN_X_CTI_CHAIN
+ , M32RXF_INSN_X_CHAIN, M32RXF_INSN_X_BEGIN, M32RXF_INSN_ADD, M32RXF_INSN_ADD3
+ , M32RXF_INSN_AND, M32RXF_INSN_AND3, M32RXF_INSN_OR, M32RXF_INSN_OR3
+ , M32RXF_INSN_XOR, M32RXF_INSN_XOR3, M32RXF_INSN_ADDI, M32RXF_INSN_ADDV
+ , M32RXF_INSN_ADDV3, M32RXF_INSN_ADDX, M32RXF_INSN_BC8, M32RXF_INSN_BC24
+ , M32RXF_INSN_BEQ, M32RXF_INSN_BEQZ, M32RXF_INSN_BGEZ, M32RXF_INSN_BGTZ
+ , M32RXF_INSN_BLEZ, M32RXF_INSN_BLTZ, M32RXF_INSN_BNEZ, M32RXF_INSN_BL8
+ , M32RXF_INSN_BL24, M32RXF_INSN_BCL8, M32RXF_INSN_BCL24, M32RXF_INSN_BNC8
+ , M32RXF_INSN_BNC24, M32RXF_INSN_BNE, M32RXF_INSN_BRA8, M32RXF_INSN_BRA24
+ , M32RXF_INSN_BNCL8, M32RXF_INSN_BNCL24, M32RXF_INSN_CMP, M32RXF_INSN_CMPI
+ , M32RXF_INSN_CMPU, M32RXF_INSN_CMPUI, M32RXF_INSN_CMPEQ, M32RXF_INSN_CMPZ
+ , M32RXF_INSN_DIV, M32RXF_INSN_DIVU, M32RXF_INSN_REM, M32RXF_INSN_REMU
+ , M32RXF_INSN_DIVH, M32RXF_INSN_JC, M32RXF_INSN_JNC, M32RXF_INSN_JL
+ , M32RXF_INSN_JMP, M32RXF_INSN_LD, M32RXF_INSN_LD_D, M32RXF_INSN_LDB
+ , M32RXF_INSN_LDB_D, M32RXF_INSN_LDH, M32RXF_INSN_LDH_D, M32RXF_INSN_LDUB
+ , M32RXF_INSN_LDUB_D, M32RXF_INSN_LDUH, M32RXF_INSN_LDUH_D, M32RXF_INSN_LD_PLUS
+ , M32RXF_INSN_LD24, M32RXF_INSN_LDI8, M32RXF_INSN_LDI16, M32RXF_INSN_LOCK
+ , M32RXF_INSN_MACHI_A, M32RXF_INSN_MACLO_A, M32RXF_INSN_MACWHI_A, M32RXF_INSN_MACWLO_A
+ , M32RXF_INSN_MUL, M32RXF_INSN_MULHI_A, M32RXF_INSN_MULLO_A, M32RXF_INSN_MULWHI_A
+ , M32RXF_INSN_MULWLO_A, M32RXF_INSN_MV, M32RXF_INSN_MVFACHI_A, M32RXF_INSN_MVFACLO_A
+ , M32RXF_INSN_MVFACMI_A, M32RXF_INSN_MVFC, M32RXF_INSN_MVTACHI_A, M32RXF_INSN_MVTACLO_A
+ , M32RXF_INSN_MVTC, M32RXF_INSN_NEG, M32RXF_INSN_NOP, M32RXF_INSN_NOT
+ , M32RXF_INSN_RAC_DSI, M32RXF_INSN_RACH_DSI, M32RXF_INSN_RTE, M32RXF_INSN_SETH
+ , M32RXF_INSN_SLL, M32RXF_INSN_SLL3, M32RXF_INSN_SLLI, M32RXF_INSN_SRA
+ , M32RXF_INSN_SRA3, M32RXF_INSN_SRAI, M32RXF_INSN_SRL, M32RXF_INSN_SRL3
+ , M32RXF_INSN_SRLI, M32RXF_INSN_ST, M32RXF_INSN_ST_D, M32RXF_INSN_STB
+ , M32RXF_INSN_STB_D, M32RXF_INSN_STH, M32RXF_INSN_STH_D, M32RXF_INSN_ST_PLUS
+ , M32RXF_INSN_ST_MINUS, M32RXF_INSN_SUB, M32RXF_INSN_SUBV, M32RXF_INSN_SUBX
+ , M32RXF_INSN_TRAP, M32RXF_INSN_UNLOCK, M32RXF_INSN_SATB, M32RXF_INSN_SATH
+ , M32RXF_INSN_SAT, M32RXF_INSN_PCMPBZ, M32RXF_INSN_SADD, M32RXF_INSN_MACWU1
+ , M32RXF_INSN_MSBLO, M32RXF_INSN_MULWU1, M32RXF_INSN_MACLH1, M32RXF_INSN_SC
+ , M32RXF_INSN_SNC, M32RXF_INSN_PAR_ADD, M32RXF_INSN_WRITE_ADD, M32RXF_INSN_PAR_AND
+ , M32RXF_INSN_WRITE_AND, M32RXF_INSN_PAR_OR, M32RXF_INSN_WRITE_OR, M32RXF_INSN_PAR_XOR
+ , M32RXF_INSN_WRITE_XOR, M32RXF_INSN_PAR_ADDI, M32RXF_INSN_WRITE_ADDI, M32RXF_INSN_PAR_ADDV
+ , M32RXF_INSN_WRITE_ADDV, M32RXF_INSN_PAR_ADDX, M32RXF_INSN_WRITE_ADDX, M32RXF_INSN_PAR_BC8
+ , M32RXF_INSN_WRITE_BC8, M32RXF_INSN_PAR_BL8, M32RXF_INSN_WRITE_BL8, M32RXF_INSN_PAR_BCL8
+ , M32RXF_INSN_WRITE_BCL8, M32RXF_INSN_PAR_BNC8, M32RXF_INSN_WRITE_BNC8, M32RXF_INSN_PAR_BRA8
+ , M32RXF_INSN_WRITE_BRA8, M32RXF_INSN_PAR_BNCL8, M32RXF_INSN_WRITE_BNCL8, M32RXF_INSN_PAR_CMP
+ , M32RXF_INSN_WRITE_CMP, M32RXF_INSN_PAR_CMPU, M32RXF_INSN_WRITE_CMPU, M32RXF_INSN_PAR_CMPEQ
+ , M32RXF_INSN_WRITE_CMPEQ, M32RXF_INSN_PAR_CMPZ, M32RXF_INSN_WRITE_CMPZ, M32RXF_INSN_PAR_JC
+ , M32RXF_INSN_WRITE_JC, M32RXF_INSN_PAR_JNC, M32RXF_INSN_WRITE_JNC, M32RXF_INSN_PAR_JL
+ , M32RXF_INSN_WRITE_JL, M32RXF_INSN_PAR_JMP, M32RXF_INSN_WRITE_JMP, M32RXF_INSN_PAR_LD
+ , M32RXF_INSN_WRITE_LD, M32RXF_INSN_PAR_LDB, M32RXF_INSN_WRITE_LDB, M32RXF_INSN_PAR_LDH
+ , M32RXF_INSN_WRITE_LDH, M32RXF_INSN_PAR_LDUB, M32RXF_INSN_WRITE_LDUB, M32RXF_INSN_PAR_LDUH
+ , M32RXF_INSN_WRITE_LDUH, M32RXF_INSN_PAR_LD_PLUS, M32RXF_INSN_WRITE_LD_PLUS, M32RXF_INSN_PAR_LDI8
+ , M32RXF_INSN_WRITE_LDI8, M32RXF_INSN_PAR_LOCK, M32RXF_INSN_WRITE_LOCK, M32RXF_INSN_PAR_MACHI_A
+ , M32RXF_INSN_WRITE_MACHI_A, M32RXF_INSN_PAR_MACLO_A, M32RXF_INSN_WRITE_MACLO_A, M32RXF_INSN_PAR_MACWHI_A
+ , M32RXF_INSN_WRITE_MACWHI_A, M32RXF_INSN_PAR_MACWLO_A, M32RXF_INSN_WRITE_MACWLO_A, M32RXF_INSN_PAR_MUL
+ , M32RXF_INSN_WRITE_MUL, M32RXF_INSN_PAR_MULHI_A, M32RXF_INSN_WRITE_MULHI_A, M32RXF_INSN_PAR_MULLO_A
+ , M32RXF_INSN_WRITE_MULLO_A, M32RXF_INSN_PAR_MULWHI_A, M32RXF_INSN_WRITE_MULWHI_A, M32RXF_INSN_PAR_MULWLO_A
+ , M32RXF_INSN_WRITE_MULWLO_A, M32RXF_INSN_PAR_MV, M32RXF_INSN_WRITE_MV, M32RXF_INSN_PAR_MVFACHI_A
+ , M32RXF_INSN_WRITE_MVFACHI_A, M32RXF_INSN_PAR_MVFACLO_A, M32RXF_INSN_WRITE_MVFACLO_A, M32RXF_INSN_PAR_MVFACMI_A
+ , M32RXF_INSN_WRITE_MVFACMI_A, M32RXF_INSN_PAR_MVFC, M32RXF_INSN_WRITE_MVFC, M32RXF_INSN_PAR_MVTACHI_A
+ , M32RXF_INSN_WRITE_MVTACHI_A, M32RXF_INSN_PAR_MVTACLO_A, M32RXF_INSN_WRITE_MVTACLO_A, M32RXF_INSN_PAR_MVTC
+ , M32RXF_INSN_WRITE_MVTC, M32RXF_INSN_PAR_NEG, M32RXF_INSN_WRITE_NEG, M32RXF_INSN_PAR_NOP
+ , M32RXF_INSN_WRITE_NOP, M32RXF_INSN_PAR_NOT, M32RXF_INSN_WRITE_NOT, M32RXF_INSN_PAR_RAC_DSI
+ , M32RXF_INSN_WRITE_RAC_DSI, M32RXF_INSN_PAR_RACH_DSI, M32RXF_INSN_WRITE_RACH_DSI, M32RXF_INSN_PAR_RTE
+ , M32RXF_INSN_WRITE_RTE, M32RXF_INSN_PAR_SLL, M32RXF_INSN_WRITE_SLL, M32RXF_INSN_PAR_SLLI
+ , M32RXF_INSN_WRITE_SLLI, M32RXF_INSN_PAR_SRA, M32RXF_INSN_WRITE_SRA, M32RXF_INSN_PAR_SRAI
+ , M32RXF_INSN_WRITE_SRAI, M32RXF_INSN_PAR_SRL, M32RXF_INSN_WRITE_SRL, M32RXF_INSN_PAR_SRLI
+ , M32RXF_INSN_WRITE_SRLI, M32RXF_INSN_PAR_ST, M32RXF_INSN_WRITE_ST, M32RXF_INSN_PAR_STB
+ , M32RXF_INSN_WRITE_STB, M32RXF_INSN_PAR_STH, M32RXF_INSN_WRITE_STH, M32RXF_INSN_PAR_ST_PLUS
+ , M32RXF_INSN_WRITE_ST_PLUS, M32RXF_INSN_PAR_ST_MINUS, M32RXF_INSN_WRITE_ST_MINUS, M32RXF_INSN_PAR_SUB
+ , M32RXF_INSN_WRITE_SUB, M32RXF_INSN_PAR_SUBV, M32RXF_INSN_WRITE_SUBV, M32RXF_INSN_PAR_SUBX
+ , M32RXF_INSN_WRITE_SUBX, M32RXF_INSN_PAR_TRAP, M32RXF_INSN_WRITE_TRAP, M32RXF_INSN_PAR_UNLOCK
+ , M32RXF_INSN_WRITE_UNLOCK, M32RXF_INSN_PAR_PCMPBZ, M32RXF_INSN_WRITE_PCMPBZ, M32RXF_INSN_PAR_SADD
+ , M32RXF_INSN_WRITE_SADD, M32RXF_INSN_PAR_MACWU1, M32RXF_INSN_WRITE_MACWU1, M32RXF_INSN_PAR_MSBLO
+ , M32RXF_INSN_WRITE_MSBLO, M32RXF_INSN_PAR_MULWU1, M32RXF_INSN_WRITE_MULWU1, M32RXF_INSN_PAR_MACLH1
+ , M32RXF_INSN_WRITE_MACLH1, M32RXF_INSN_PAR_SC, M32RXF_INSN_WRITE_SC, M32RXF_INSN_PAR_SNC
+ , M32RXF_INSN_WRITE_SNC, M32RXF_INSN_MAX
+} M32RXF_INSN_TYPE;
+
+/* Enum declaration for semantic formats in cpu family m32rxf. */
+typedef enum m32rxf_sfmt_type {
+ M32RXF_SFMT_EMPTY, M32RXF_SFMT_ADD, M32RXF_SFMT_ADD3, M32RXF_SFMT_AND3
+ , M32RXF_SFMT_OR3, M32RXF_SFMT_ADDI, M32RXF_SFMT_ADDV, M32RXF_SFMT_ADDV3
+ , M32RXF_SFMT_ADDX, M32RXF_SFMT_BC8, M32RXF_SFMT_BC24, M32RXF_SFMT_BEQ
+ , M32RXF_SFMT_BEQZ, M32RXF_SFMT_BL8, M32RXF_SFMT_BL24, M32RXF_SFMT_BCL8
+ , M32RXF_SFMT_BCL24, M32RXF_SFMT_BRA8, M32RXF_SFMT_BRA24, M32RXF_SFMT_CMP
+ , M32RXF_SFMT_CMPI, M32RXF_SFMT_CMPZ, M32RXF_SFMT_DIV, M32RXF_SFMT_JC
+ , M32RXF_SFMT_JL, M32RXF_SFMT_JMP, M32RXF_SFMT_LD, M32RXF_SFMT_LD_D
+ , M32RXF_SFMT_LD_PLUS, M32RXF_SFMT_LD24, M32RXF_SFMT_LDI8, M32RXF_SFMT_LDI16
+ , M32RXF_SFMT_LOCK, M32RXF_SFMT_MACHI_A, M32RXF_SFMT_MULHI_A, M32RXF_SFMT_MV
+ , M32RXF_SFMT_MVFACHI_A, M32RXF_SFMT_MVFC, M32RXF_SFMT_MVTACHI_A, M32RXF_SFMT_MVTC
+ , M32RXF_SFMT_NOP, M32RXF_SFMT_RAC_DSI, M32RXF_SFMT_RTE, M32RXF_SFMT_SETH
+ , M32RXF_SFMT_SLL3, M32RXF_SFMT_SLLI, M32RXF_SFMT_ST, M32RXF_SFMT_ST_D
+ , M32RXF_SFMT_STB, M32RXF_SFMT_STB_D, M32RXF_SFMT_STH, M32RXF_SFMT_STH_D
+ , M32RXF_SFMT_ST_PLUS, M32RXF_SFMT_TRAP, M32RXF_SFMT_UNLOCK, M32RXF_SFMT_SATB
+ , M32RXF_SFMT_SAT, M32RXF_SFMT_SADD, M32RXF_SFMT_MACWU1, M32RXF_SFMT_MSBLO
+ , M32RXF_SFMT_MULWU1, M32RXF_SFMT_SC
+} M32RXF_SFMT_TYPE;
+
+/* Function unit handlers (user written). */
+
+extern int m32rxf_model_m32rx_u_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
+extern int m32rxf_model_m32rx_u_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/);
+extern int m32rxf_model_m32rx_u_cti (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/);
+extern int m32rxf_model_m32rx_u_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
+extern int m32rxf_model_m32rx_u_cmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
+extern int m32rxf_model_m32rx_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/, INT /*dr*/);
+
+/* Profiling before/after handlers (user written) */
+
+extern void m32rxf_model_insn_before (SIM_CPU *, int /*first_p*/);
+extern void m32rxf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
+
+#endif /* M32RXF_DECODE_H */
extern DI m32rbf_h_accum_get_handler (SIM_CPU *);
extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
+extern USI m32rxf_h_cr_get_handler (SIM_CPU *, UINT);
+extern void m32rxf_h_cr_set_handler (SIM_CPU *, UINT, USI);
+extern UQI m32rxf_h_psw_get_handler (SIM_CPU *);
+extern void m32rxf_h_psw_set_handler (SIM_CPU *, UQI);
+extern DI m32rxf_h_accum_get_handler (SIM_CPU *);
+extern void m32rxf_h_accum_set_handler (SIM_CPU *, DI);
+
+extern DI m32rxf_h_accums_get_handler (SIM_CPU *, UINT);
+extern void m32rxf_h_accums_set_handler (SIM_CPU *, UINT, DI);
\f
/* Misc. profile data. */
\f
/* Additional execution support. */
+/* Result of semantic function is one of
+ - next address, branch only
+ - NEW_PC_SKIP, sc/snc insn
+ - NEW_PC_2, 2 byte non-branch non-sc/snc insn
+ - NEW_PC_4, 4 byte non-branch insn
+ The special values have bit 1 set so it's cheap to distinguish them.
+ This works because all cti's are defined to zero the bottom two bits
+ Note that the m32rx no longer doesn't implement its semantics with
+ functions, so this isn't used. It's kept around should it be needed
+ again. */
+/* FIXME: replace 0xffff0001 with 1? */
+#define NEW_PC_BASE 0xffff0001
+#define NEW_PC_SKIP NEW_PC_BASE
+#define NEW_PC_2 (NEW_PC_BASE + 2)
+#define NEW_PC_4 (NEW_PC_BASE + 4)
+#define NEW_PC_BRANCH_P(addr) (((addr) & 1) == 0)
+
+/* Modify "next pc" support to handle parallel execution.
+ This is for the non-pbb case. The m32rx no longer implements this.
+ It's kept around should it be needed again. */
+#if defined (WANT_CPU_M32RXF) && ! WITH_SCACHE_PBB_M32RXF
+#undef SEM_NEXT_VPC
+#define SEM_NEXT_VPC(abuf, len) (NEW_PC_BASE + (len))
+#undef SEM_SKIP_INSN
+#define SEM_SKIP_INSN(cpu, sc, vpcvar, yes) FIXME
+#endif
\f
/* Hardware/device support.
??? Will eventually want to move device stuff to config files. */
--- /dev/null
+/* m32rx simulator support code
+ Copyright (C) 1997, 1998 Free Software Foundation, Inc.
+ Contributed by Cygnus Support.
+
+This file is part of GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#define WANT_CPU m32rxf
+#define WANT_CPU_M32RXF
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+/* The contents of BUF are in target byte order. */
+
+int
+m32rxf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
+{
+ return m32rbf_fetch_register (current_cpu, rn, buf, len);
+}
+
+/* The contents of BUF are in target byte order. */
+
+int
+m32rxf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
+{
+ return m32rbf_store_register (current_cpu, rn, buf, len);
+}
+\f
+/* Cover fns to get/set the control registers.
+ FIXME: Duplicated from m32r.c. The issue is structure offsets. */
+
+USI
+m32rxf_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
+{
+ switch (cr)
+ {
+ case H_CR_PSW : /* psw */
+ return (((CPU (h_bpsw) & 0xc1) << 8)
+ | ((CPU (h_psw) & 0xc0) << 0)
+ | GET_H_COND ());
+ case H_CR_BBPSW : /* backup backup psw */
+ return CPU (h_bbpsw) & 0xc1;
+ case H_CR_CBR : /* condition bit */
+ return GET_H_COND ();
+ case H_CR_SPI : /* interrupt stack pointer */
+ if (! GET_H_SM ())
+ return CPU (h_gr[H_GR_SP]);
+ else
+ return CPU (h_cr[H_CR_SPI]);
+ case H_CR_SPU : /* user stack pointer */
+ if (GET_H_SM ())
+ return CPU (h_gr[H_GR_SP]);
+ else
+ return CPU (h_cr[H_CR_SPU]);
+ case H_CR_BPC : /* backup pc */
+ return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
+ case H_CR_BBPC : /* backup backup pc */
+ return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
+ case 4 : /* ??? unspecified, but apparently available */
+ case 5 : /* ??? unspecified, but apparently available */
+ return CPU (h_cr[cr]);
+ default :
+ return 0;
+ }
+}
+
+void
+m32rxf_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
+{
+ switch (cr)
+ {
+ case H_CR_PSW : /* psw */
+ {
+ int old_sm = (CPU (h_psw) & 0x80) != 0;
+ int new_sm = (newval & 0x80) != 0;
+ CPU (h_bpsw) = (newval >> 8) & 0xff;
+ CPU (h_psw) = newval & 0xff;
+ SET_H_COND (newval & 1);
+ /* When switching stack modes, update the registers. */
+ if (old_sm != new_sm)
+ {
+ if (old_sm)
+ {
+ /* Switching user -> system. */
+ CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
+ CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
+ }
+ else
+ {
+ /* Switching system -> user. */
+ CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
+ CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
+ }
+ }
+ break;
+ }
+ case H_CR_BBPSW : /* backup backup psw */
+ CPU (h_bbpsw) = newval & 0xff;
+ break;
+ case H_CR_CBR : /* condition bit */
+ SET_H_COND (newval & 1);
+ break;
+ case H_CR_SPI : /* interrupt stack pointer */
+ if (! GET_H_SM ())
+ CPU (h_gr[H_GR_SP]) = newval;
+ else
+ CPU (h_cr[H_CR_SPI]) = newval;
+ break;
+ case H_CR_SPU : /* user stack pointer */
+ if (GET_H_SM ())
+ CPU (h_gr[H_GR_SP]) = newval;
+ else
+ CPU (h_cr[H_CR_SPU]) = newval;
+ break;
+ case H_CR_BPC : /* backup pc */
+ CPU (h_cr[H_CR_BPC]) = newval;
+ break;
+ case H_CR_BBPC : /* backup backup pc */
+ CPU (h_cr[H_CR_BBPC]) = newval;
+ break;
+ case 4 : /* ??? unspecified, but apparently available */
+ case 5 : /* ??? unspecified, but apparently available */
+ CPU (h_cr[cr]) = newval;
+ break;
+ default :
+ /* ignore */
+ break;
+ }
+}
+
+/* Cover fns to access h-psw. */
+
+UQI
+m32rxf_h_psw_get_handler (SIM_CPU *current_cpu)
+{
+ return (CPU (h_psw) & 0xfe) | (CPU (h_cond) & 1);
+}
+
+void
+m32rxf_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
+{
+ CPU (h_psw) = newval;
+ CPU (h_cond) = newval & 1;
+}
+
+/* Cover fns to access h-accum. */
+
+DI
+m32rxf_h_accum_get_handler (SIM_CPU *current_cpu)
+{
+ /* Sign extend the top 8 bits. */
+ DI r;
+ r = ANDDI (CPU (h_accum), MAKEDI (0xffffff, 0xffffffff));
+ r = XORDI (r, MAKEDI (0x800000, 0));
+ r = SUBDI (r, MAKEDI (0x800000, 0));
+ return r;
+}
+
+void
+m32rxf_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
+{
+ CPU (h_accum) = newval;
+}
+
+/* Cover fns to access h-accums. */
+
+DI
+m32rxf_h_accums_get_handler (SIM_CPU *current_cpu, UINT regno)
+{
+ /* FIXME: Yes, this is just a quick hack. */
+ DI r;
+ if (regno == 0)
+ r = CPU (h_accum);
+ else
+ r = CPU (h_accums[1]);
+ /* Sign extend the top 8 bits. */
+ r = ANDDI (r, MAKEDI (0xffffff, 0xffffffff));
+ r = XORDI (r, MAKEDI (0x800000, 0));
+ r = SUBDI (r, MAKEDI (0x800000, 0));
+ return r;
+}
+
+void
+m32rxf_h_accums_set_handler (SIM_CPU *current_cpu, UINT regno, DI newval)
+{
+ /* FIXME: Yes, this is just a quick hack. */
+ if (regno == 0)
+ CPU (h_accum) = newval;
+ else
+ CPU (h_accums[1]) = newval;
+}
+\f
+#if WITH_PROFILE_MODEL_P
+
+/* Initialize cycle counting for an insn.
+ FIRST_P is non-zero if this is the first insn in a set of parallel
+ insns. */
+
+void
+m32rxf_model_insn_before (SIM_CPU *cpu, int first_p)
+{
+ m32rbf_model_insn_before (cpu, first_p);
+}
+
+/* Record the cycles computed for an insn.
+ LAST_P is non-zero if this is the last insn in a set of parallel insns,
+ and we update the total cycle count.
+ CYCLES is the cycle count of the insn. */
+
+void
+m32rxf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
+{
+ m32rbf_model_insn_after (cpu, last_p, cycles);
+}
+
+static INLINE void
+check_load_stall (SIM_CPU *cpu, int regno)
+{
+ UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
+
+ if (regno != -1
+ && (h_gr & (1 << regno)) != 0)
+ {
+ CPU_M32R_MISC_PROFILE (cpu)->load_stall += 2;
+ if (TRACE_INSN_P (cpu))
+ cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
+ }
+}
+
+int
+m32rxf_model_m32rx_u_exec (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT sr, INT sr2, INT dr)
+{
+ check_load_stall (cpu, sr);
+ check_load_stall (cpu, sr2);
+ return idesc->timing->units[unit_num].done;
+}
+
+int
+m32rxf_model_m32rx_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT src1, INT src2)
+{
+ check_load_stall (cpu, src1);
+ check_load_stall (cpu, src2);
+ return idesc->timing->units[unit_num].done;
+}
+
+int
+m32rxf_model_m32rx_u_mac (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT src1, INT src2)
+{
+ check_load_stall (cpu, src1);
+ check_load_stall (cpu, src2);
+ return idesc->timing->units[unit_num].done;
+}
+
+int
+m32rxf_model_m32rx_u_cti (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT sr)
+{
+ PROFILE_DATA *profile = CPU_PROFILE_DATA (cpu);
+ int taken_p = (referenced & (1 << 1)) != 0;
+
+ check_load_stall (cpu, sr);
+ if (taken_p)
+ {
+ CPU_M32R_MISC_PROFILE (cpu)->cti_stall += 2;
+ PROFILE_MODEL_TAKEN_COUNT (profile) += 1;
+ }
+ else
+ PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1;
+ return idesc->timing->units[unit_num].done;
+}
+
+int
+m32rxf_model_m32rx_u_load (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT sr, INT dr)
+{
+ CPU_M32R_MISC_PROFILE (cpu)->load_regs_pending |= (1 << dr);
+ return idesc->timing->units[unit_num].done;
+}
+
+int
+m32rxf_model_m32rx_u_store (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT src1, INT src2)
+{
+ return idesc->timing->units[unit_num].done;
+}
+
+#endif /* WITH_PROFILE_MODEL_P */
--- /dev/null
+# Simulator main loop for m32rx. -*- C -*-
+# Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Simulators.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+# Syntax:
+# /bin/sh mainloop.in command
+#
+# Command is one of:
+#
+# init
+# support
+# extract-{simple,scache,pbb}
+# {full,fast}-exec-{simple,scache,pbb}
+#
+# A target need only provide a "full" version of one of simple,scache,pbb.
+# If the target wants it can also provide a fast version of same, or if
+# the slow (full featured) version is `simple', then the fast version can be
+# one of scache/pbb.
+# A target can't provide more than this.
+
+# ??? After a few more ports are done, revisit.
+# Will eventually need to machine generate a lot of this.
+
+case "x$1" in
+
+xsupport)
+
+cat <<EOF
+
+/* Emit insns to write back the results of insns executed in parallel.
+ SC points to a sufficient number of scache entries for the writeback
+ handlers.
+ SC1/ID1 is the first insn (left slot, lower address).
+ SC2/ID2 is the second insn (right slot, higher address). */
+
+static INLINE void
+emit_par_finish (SIM_CPU *current_cpu, PCADDR pc, SCACHE *sc,
+ SCACHE *sc1, const IDESC *id1, SCACHE *sc2, const IDESC *id2)
+{
+ ARGBUF *abuf;
+
+ abuf = &sc->argbuf;
+ id1 = id1->par_idesc;
+ abuf->fields.write.abuf = &sc1->argbuf;
+ @cpu@_fill_argbuf (current_cpu, abuf, id1, pc, 0);
+ /* no need to set trace_p,profile_p */
+#if 0 /* not currently needed for id2 since results written directly */
+ abuf = &sc[1].argbuf;
+ id2 = id2->par_idesc;
+ abuf->fields.write.abuf = &sc2->argbuf;
+ @cpu@_fill_argbuf (current_cpu, abuf, id2, pc + 2, 0);
+ /* no need to set trace_p,profile_p */
+#endif
+}
+
+static INLINE const IDESC *
+emit_16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
+ SCACHE *sc, int fast_p, int parallel_p)
+{
+ ARGBUF *abuf = &sc->argbuf;
+ const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf);
+
+ if (parallel_p)
+ id = id->par_idesc;
+ @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
+ return id;
+}
+
+static INLINE const IDESC *
+emit_full16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *sc,
+ int trace_p, int profile_p)
+{
+ const IDESC *id;
+
+ @cpu@_emit_before (current_cpu, sc, pc, 1);
+ id = emit_16 (current_cpu, pc, insn, sc + 1, 0, 0);
+ @cpu@_emit_after (current_cpu, sc + 2, pc);
+ sc[1].argbuf.trace_p = trace_p;
+ sc[1].argbuf.profile_p = profile_p;
+ return id;
+}
+
+static INLINE const IDESC *
+emit_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
+ SCACHE *sc, int fast_p)
+{
+ const IDESC *id,*id2;
+
+ /* Emit both insns, then emit a finisher-upper.
+ We speed things up by handling the second insn serially
+ [not parallelly]. Then the writeback only has to deal
+ with the first insn. */
+ /* ??? Revisit to handle exceptions right. */
+
+ /* FIXME: No need to handle this parallely if second is nop. */
+ id = emit_16 (current_cpu, pc, insn >> 16, sc, fast_p, 1);
+
+ /* Note that this can never be a cti. No cti's go in the S pipeline. */
+ id2 = emit_16 (current_cpu, pc + 2, insn & 0x7fff, sc + 1, fast_p, 0);
+
+ /* Set sc/snc insns notion of where to skip to. */
+ if (IDESC_SKIP_P (id))
+ SEM_SKIP_COMPILE (current_cpu, sc, 1);
+
+ /* Emit code to finish executing the semantics
+ (write back the results). */
+ emit_par_finish (current_cpu, pc, sc + 2, sc, id, sc + 1, id2);
+
+ return id;
+}
+
+static INLINE const IDESC *
+emit_full_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
+ SCACHE *sc, int trace_p, int profile_p)
+{
+ const IDESC *id,*id2;
+
+ /* Emit both insns, then emit a finisher-upper.
+ We speed things up by handling the second insn serially
+ [not parallelly]. Then the writeback only has to deal
+ with the first insn. */
+ /* ??? Revisit to handle exceptions right. */
+
+ @cpu@_emit_before (current_cpu, sc, pc, 1);
+
+ /* FIXME: No need to handle this parallelly if second is nop. */
+ id = emit_16 (current_cpu, pc, insn >> 16, sc + 1, 0, 1);
+ sc[1].argbuf.trace_p = trace_p;
+ sc[1].argbuf.profile_p = profile_p;
+
+ @cpu@_emit_before (current_cpu, sc + 2, pc, 0);
+
+ /* Note that this can never be a cti. No cti's go in the S pipeline. */
+ id2 = emit_16 (current_cpu, pc + 2, insn & 0x7fff, sc + 3, 0, 0);
+ sc[3].argbuf.trace_p = trace_p;
+ sc[3].argbuf.profile_p = profile_p;
+
+ /* Set sc/snc insns notion of where to skip to. */
+ if (IDESC_SKIP_P (id))
+ SEM_SKIP_COMPILE (current_cpu, sc, 4);
+
+ /* Emit code to finish executing the semantics
+ (write back the results). */
+ emit_par_finish (current_cpu, pc, sc + 4, sc + 1, id, sc + 3, id2);
+
+ @cpu@_emit_after (current_cpu, sc + 5, pc);
+
+ return id;
+}
+
+static INLINE const IDESC *
+emit_32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
+ SCACHE *sc, int fast_p)
+{
+ ARGBUF *abuf = &sc->argbuf;
+ const IDESC *id = @cpu@_decode (current_cpu, pc,
+ (USI) insn >> 16, insn, abuf);
+
+ @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
+ return id;
+}
+
+static INLINE const IDESC *
+emit_full32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *sc,
+ int trace_p, int profile_p)
+{
+ const IDESC *id;
+
+ @cpu@_emit_before (current_cpu, sc, pc, 1);
+ id = emit_32 (current_cpu, pc, insn, sc + 1, 0);
+ @cpu@_emit_after (current_cpu, sc + 2, pc);
+ sc[1].argbuf.trace_p = trace_p;
+ sc[1].argbuf.profile_p = profile_p;
+ return id;
+}
+
+EOF
+
+;;
+
+xinit)
+
+# Nothing needed.
+
+;;
+
+xextract-pbb)
+
+# Inputs: current_cpu, pc, sc, max_insns, FAST_P
+# Outputs: sc, pc
+# sc must be left pointing past the last created entry.
+# pc must be left pointing past the last created entry.
+# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
+# to record the vpc of the cti insn.
+# SET_INSN_COUNT(n) must be called to record number of real insns.
+
+cat <<EOF
+{
+ const IDESC *idesc;
+ int icount = 0;
+
+ if ((pc & 3) != 0)
+ {
+ /* This occurs when single stepping and when compiling the not-taken
+ part of conditional branches. */
+ UHI insn = GETIMEMUHI (current_cpu, pc);
+ int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
+ int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
+ SCACHE *cti_sc; /* ??? tmp hack */
+
+ /* A parallel insn isn't allowed here, but we don't mind nops.
+ ??? We need to wait until the insn is executed before signalling
+ the error, for situations where such signalling is wanted. */
+#if 0
+ if ((insn & 0x8000) != 0
+ && (insn & 0x7fff) != 0x7000) /* parallel nops are ok */
+ sim_engine_invalid_insn (current_cpu, pc, 0);
+#endif
+
+ /* Only emit before/after handlers if necessary. */
+ if (FAST_P || (! trace_p && ! profile_p))
+ {
+ idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, FAST_P, 0);
+ cti_sc = sc;
+ ++sc;
+ --max_insns;
+ }
+ else
+ {
+ idesc = emit_full16 (current_cpu, pc, insn & 0x7fff, sc,
+ trace_p, profile_p);
+ cti_sc = sc + 1;
+ sc += 3;
+ max_insns -= 3;
+ }
+ ++icount;
+ pc += 2;
+ if (IDESC_CTI_P (idesc))
+ {
+ SET_CTI_VPC (cti_sc);
+ goto Finish;
+ }
+ }
+
+ /* There are two copies of the compiler: full(!fast) and fast.
+ The "full" case emits before/after handlers for each insn.
+ Having two copies of this code is a tradeoff, having one copy
+ seemed a bit more difficult to read (due to constantly testing
+ FAST_P). ??? On the other hand, with address ranges we'll want to
+ omit before/after handlers for unwanted insns. Having separate loops
+ for FAST/!FAST avoids constantly doing the test in the loop, but
+ typically FAST_P is a constant and such tests will get optimized out. */
+
+ if (FAST_P)
+ {
+ while (max_insns > 0)
+ {
+ USI insn = GETIMEMUSI (current_cpu, pc);
+ if ((SI) insn < 0)
+ {
+ /* 32 bit insn */
+ idesc = emit_32 (current_cpu, pc, insn, sc, 1);
+ ++sc;
+ --max_insns;
+ ++icount;
+ pc += 4;
+ if (IDESC_CTI_P (idesc))
+ {
+ SET_CTI_VPC (sc - 1);
+ break;
+ }
+ }
+ else
+ {
+ if ((insn & 0x8000) != 0) /* parallel? */
+ {
+ /* Yep. Here's the "interesting" [sic] part. */
+ idesc = emit_parallel (current_cpu, pc, insn, sc, 1);
+ sc += 3;
+ max_insns -= 3;
+ icount += 2;
+ pc += 4;
+ if (IDESC_CTI_P (idesc))
+ {
+ SET_CTI_VPC (sc - 3);
+ break;
+ }
+ }
+ else /* 2 serial 16 bit insns */
+ {
+ idesc = emit_16 (current_cpu, pc, insn >> 16, sc, 1, 0);
+ ++sc;
+ --max_insns;
+ ++icount;
+ pc += 2;
+ if (IDESC_CTI_P (idesc))
+ {
+ SET_CTI_VPC (sc - 1);
+ break;
+ }
+ /* While we're guaranteed that there's room to extract the
+ insn, when single stepping we can't; the pbb must stop
+ after the first insn. */
+ if (max_insns == 0)
+ break;
+ idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, 1, 0);
+ ++sc;
+ --max_insns;
+ ++icount;
+ pc += 2;
+ if (IDESC_CTI_P (idesc))
+ {
+ SET_CTI_VPC (sc - 1);
+ break;
+ }
+ }
+ }
+ }
+ }
+ else /* ! FAST_P */
+ {
+ while (max_insns > 0)
+ {
+ USI insn = GETIMEMUSI (current_cpu, pc);
+ int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
+ int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
+ SCACHE *cti_sc; /* ??? tmp hack */
+ if ((SI) insn < 0)
+ {
+ /* 32 bit insn
+ Only emit before/after handlers if necessary. */
+ if (trace_p || profile_p)
+ {
+ idesc = emit_full32 (current_cpu, pc, insn, sc,
+ trace_p, profile_p);
+ cti_sc = sc + 1;
+ sc += 3;
+ max_insns -= 3;
+ }
+ else
+ {
+ idesc = emit_32 (current_cpu, pc, insn, sc, 0);
+ cti_sc = sc;
+ ++sc;
+ --max_insns;
+ }
+ ++icount;
+ pc += 4;
+ if (IDESC_CTI_P (idesc))
+ {
+ SET_CTI_VPC (cti_sc);
+ break;
+ }
+ }
+ else
+ {
+ if ((insn & 0x8000) != 0) /* parallel? */
+ {
+ /* Yep. Here's the "interesting" [sic] part.
+ Only emit before/after handlers if necessary. */
+ if (trace_p || profile_p)
+ {
+ idesc = emit_full_parallel (current_cpu, pc, insn, sc,
+ trace_p, profile_p);
+ cti_sc = sc + 1;
+ sc += 6;
+ max_insns -= 6;
+ }
+ else
+ {
+ idesc = emit_parallel (current_cpu, pc, insn, sc, 0);
+ cti_sc = sc;
+ sc += 3;
+ max_insns -= 3;
+ }
+ icount += 2;
+ pc += 4;
+ if (IDESC_CTI_P (idesc))
+ {
+ SET_CTI_VPC (cti_sc);
+ break;
+ }
+ }
+ else /* 2 serial 16 bit insns */
+ {
+ /* Only emit before/after handlers if necessary. */
+ if (trace_p || profile_p)
+ {
+ idesc = emit_full16 (current_cpu, pc, insn >> 16, sc,
+ trace_p, profile_p);
+ cti_sc = sc + 1;
+ sc += 3;
+ max_insns -= 3;
+ }
+ else
+ {
+ idesc = emit_16 (current_cpu, pc, insn >> 16, sc, 0, 0);
+ cti_sc = sc;
+ ++sc;
+ --max_insns;
+ }
+ ++icount;
+ pc += 2;
+ if (IDESC_CTI_P (idesc))
+ {
+ SET_CTI_VPC (cti_sc);
+ break;
+ }
+ /* While we're guaranteed that there's room to extract the
+ insn, when single stepping we can't; the pbb must stop
+ after the first insn. */
+ if (max_insns <= 0)
+ break;
+ /* Use the same trace/profile address for the 2nd insn.
+ Saves us having to compute it and they come in pairs
+ anyway (e.g. can never branch to the 2nd insn). */
+ if (trace_p || profile_p)
+ {
+ idesc = emit_full16 (current_cpu, pc, insn & 0x7fff, sc,
+ trace_p, profile_p);
+ cti_sc = sc + 1;
+ sc += 3;
+ max_insns -= 3;
+ }
+ else
+ {
+ idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, 0, 0);
+ cti_sc = sc;
+ ++sc;
+ --max_insns;
+ }
+ ++icount;
+ pc += 2;
+ if (IDESC_CTI_P (idesc))
+ {
+ SET_CTI_VPC (cti_sc);
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ Finish:
+ SET_INSN_COUNT (icount);
+}
+EOF
+
+;;
+
+xfull-exec-pbb)
+
+# Inputs: current_cpu, vpc, FAST_P
+# Outputs: vpc
+# vpc is the virtual program counter.
+
+cat <<EOF
+#define DEFINE_SWITCH
+#include "semx-switch.c"
+EOF
+
+;;
+
+*)
+ echo "Invalid argument to mainloop.in: $1" >&2
+ exit 1
+ ;;
+
+esac
--- /dev/null
+/* Simulator model support for m32rxf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU m32rxf
+#define WANT_CPU_M32RXF
+
+#include "sim-main.h"
+
+/* The profiling data is recorded here, but is accessed via the profiling
+ mechanism. After all, this is information for profiling. */
+
+#if WITH_PROFILE_MODEL_P
+
+/* Model handlers for each insn. */
+
+static int
+model_m32rx_add (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_add3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_and (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_and3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_and3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_or (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_or3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_and3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_xor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_xor3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_and3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_addi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_addv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_addv3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_addx (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_bc8 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl8.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_bc24 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl24.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_beq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_beqz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_bgez (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_bgtz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_blez (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_bltz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_bnez (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_bl8 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl8.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_bl24 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl24.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_bcl8 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl8.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_bcl24 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl24.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl8.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl24.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_bne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_bra8 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl8.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_bra24 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl24.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_bncl8 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl8.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_bncl24 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl24.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_cmp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_cmpi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_d.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_cmpu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_cmpui (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_d.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_cmpeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_cmpz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_div (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_divu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_rem (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_remu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_divh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_jc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ in_sr = FLD (in_sr);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_jnc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ in_sr = FLD (in_sr);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_jl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ in_sr = FLD (in_sr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_jmp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ in_sr = FLD (in_sr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_ld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = 0;
+ INT out_dr = 0;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_ld_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = 0;
+ INT out_dr = 0;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_ldb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = 0;
+ INT out_dr = 0;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = 0;
+ INT out_dr = 0;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_ldh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = 0;
+ INT out_dr = 0;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = 0;
+ INT out_dr = 0;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_ldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = 0;
+ INT out_dr = 0;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = 0;
+ INT out_dr = 0;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_lduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = 0;
+ INT out_dr = 0;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = 0;
+ INT out_dr = 0;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = 0;
+ INT out_dr = 0;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_dr = FLD (in_sr);
+ out_dr = FLD (out_sr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_ld24 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld24.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_lock (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = 0;
+ INT out_dr = 0;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_machi_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_maclo_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_macwhi_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_macwlo_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_mul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_mulhi_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_mullo_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_mulwhi_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_mulwlo_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_mv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_mvfachi_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_mvfaclo_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_mvfacmi_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_mvfc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mvfc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_mvtachi_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_src1);
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_mvtaclo_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_src1);
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_mvtc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ referenced |= 1 << 0;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_neg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_nop (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_not (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_rac_dsi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_rac_dsi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_rach_dsi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_rac_dsi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_rte (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_seth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_seth.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_sll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_sll3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_slli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_sra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_sra3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_srai (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_srl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_srl3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_srli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_st (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = 0;
+ INT in_src2 = 0;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_st_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_d.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = 0;
+ INT in_src2 = 0;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_stb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = 0;
+ INT in_src2 = 0;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_stb_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_d.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = 0;
+ INT in_src2 = 0;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_sth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = 0;
+ INT in_src2 = 0;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_sth_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_d.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = 0;
+ INT in_src2 = 0;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_st_plus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = 0;
+ INT in_src2 = 0;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_dr = FLD (in_src2);
+ out_dr = FLD (out_src2);
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_st_minus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = 0;
+ INT in_src2 = 0;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_dr = FLD (in_src2);
+ out_dr = FLD (out_src2);
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_sub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_subv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_subx (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ in_dr = FLD (in_dr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_trap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_trap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_unlock (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = 0;
+ INT out_dr = 0;
+ cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_satb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_sath (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_sat (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ in_sr = FLD (in_sr);
+ out_dr = FLD (out_dr);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_pcmpbz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_sadd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_macwu1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_msblo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_mulwu1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_maclh1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_src1 = -1;
+ INT in_src2 = -1;
+ in_src1 = FLD (in_src1);
+ in_src2 = FLD (in_src2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_sc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_m32rx_snc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_sr = -1;
+ INT in_dr = -1;
+ INT out_dr = -1;
+ cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+ }
+ return cycles;
+#undef FLD
+}
+
+/* We assume UNIT_NONE == 0 because the tables don't always terminate
+ entries with it. */
+
+/* Model timing data for `m32rx'. */
+
+static const INSN_TIMING m32rx_timing[] = {
+ { M32RXF_INSN_X_INVALID, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_X_AFTER, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_X_BEFORE, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_X_CHAIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_X_BEGIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_ADD, model_m32rx_add, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_ADD3, model_m32rx_add3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_AND, model_m32rx_and, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_AND3, model_m32rx_and3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_OR, model_m32rx_or, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_OR3, model_m32rx_or3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_XOR, model_m32rx_xor, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_XOR3, model_m32rx_xor3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_ADDI, model_m32rx_addi, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_ADDV, model_m32rx_addv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_ADDV3, model_m32rx_addv3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_ADDX, model_m32rx_addx, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_BC8, model_m32rx_bc8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
+ { M32RXF_INSN_BC24, model_m32rx_bc24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
+ { M32RXF_INSN_BEQ, model_m32rx_beq, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
+ { M32RXF_INSN_BEQZ, model_m32rx_beqz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
+ { M32RXF_INSN_BGEZ, model_m32rx_bgez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
+ { M32RXF_INSN_BGTZ, model_m32rx_bgtz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
+ { M32RXF_INSN_BLEZ, model_m32rx_blez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
+ { M32RXF_INSN_BLTZ, model_m32rx_bltz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
+ { M32RXF_INSN_BNEZ, model_m32rx_bnez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
+ { M32RXF_INSN_BL8, model_m32rx_bl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
+ { M32RXF_INSN_BL24, model_m32rx_bl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
+ { M32RXF_INSN_BCL8, model_m32rx_bcl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
+ { M32RXF_INSN_BCL24, model_m32rx_bcl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
+ { M32RXF_INSN_BNC8, model_m32rx_bnc8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
+ { M32RXF_INSN_BNC24, model_m32rx_bnc24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
+ { M32RXF_INSN_BNE, model_m32rx_bne, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
+ { M32RXF_INSN_BRA8, model_m32rx_bra8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
+ { M32RXF_INSN_BRA24, model_m32rx_bra24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
+ { M32RXF_INSN_BNCL8, model_m32rx_bncl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
+ { M32RXF_INSN_BNCL24, model_m32rx_bncl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
+ { M32RXF_INSN_CMP, model_m32rx_cmp, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
+ { M32RXF_INSN_CMPI, model_m32rx_cmpi, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
+ { M32RXF_INSN_CMPU, model_m32rx_cmpu, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
+ { M32RXF_INSN_CMPUI, model_m32rx_cmpui, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
+ { M32RXF_INSN_CMPEQ, model_m32rx_cmpeq, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
+ { M32RXF_INSN_CMPZ, model_m32rx_cmpz, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
+ { M32RXF_INSN_DIV, model_m32rx_div, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
+ { M32RXF_INSN_DIVU, model_m32rx_divu, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
+ { M32RXF_INSN_REM, model_m32rx_rem, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
+ { M32RXF_INSN_REMU, model_m32rx_remu, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
+ { M32RXF_INSN_DIVH, model_m32rx_divh, { { (int) UNIT_M32RX_U_EXEC, 1, 21 } } },
+ { M32RXF_INSN_JC, model_m32rx_jc, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
+ { M32RXF_INSN_JNC, model_m32rx_jnc, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
+ { M32RXF_INSN_JL, model_m32rx_jl, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
+ { M32RXF_INSN_JMP, model_m32rx_jmp, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
+ { M32RXF_INSN_LD, model_m32rx_ld, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
+ { M32RXF_INSN_LD_D, model_m32rx_ld_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
+ { M32RXF_INSN_LDB, model_m32rx_ldb, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
+ { M32RXF_INSN_LDB_D, model_m32rx_ldb_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
+ { M32RXF_INSN_LDH, model_m32rx_ldh, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
+ { M32RXF_INSN_LDH_D, model_m32rx_ldh_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
+ { M32RXF_INSN_LDUB, model_m32rx_ldub, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
+ { M32RXF_INSN_LDUB_D, model_m32rx_ldub_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
+ { M32RXF_INSN_LDUH, model_m32rx_lduh, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
+ { M32RXF_INSN_LDUH_D, model_m32rx_lduh_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
+ { M32RXF_INSN_LD_PLUS, model_m32rx_ld_plus, { { (int) UNIT_M32RX_U_LOAD, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
+ { M32RXF_INSN_LD24, model_m32rx_ld24, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_LDI8, model_m32rx_ldi8, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_LDI16, model_m32rx_ldi16, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_LOCK, model_m32rx_lock, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
+ { M32RXF_INSN_MACHI_A, model_m32rx_machi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
+ { M32RXF_INSN_MACLO_A, model_m32rx_maclo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
+ { M32RXF_INSN_MACWHI_A, model_m32rx_macwhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
+ { M32RXF_INSN_MACWLO_A, model_m32rx_macwlo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
+ { M32RXF_INSN_MUL, model_m32rx_mul, { { (int) UNIT_M32RX_U_EXEC, 1, 4 } } },
+ { M32RXF_INSN_MULHI_A, model_m32rx_mulhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
+ { M32RXF_INSN_MULLO_A, model_m32rx_mullo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
+ { M32RXF_INSN_MULWHI_A, model_m32rx_mulwhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
+ { M32RXF_INSN_MULWLO_A, model_m32rx_mulwlo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
+ { M32RXF_INSN_MV, model_m32rx_mv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_MVFACHI_A, model_m32rx_mvfachi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
+ { M32RXF_INSN_MVFACLO_A, model_m32rx_mvfaclo_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
+ { M32RXF_INSN_MVFACMI_A, model_m32rx_mvfacmi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
+ { M32RXF_INSN_MVFC, model_m32rx_mvfc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_MVTACHI_A, model_m32rx_mvtachi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_MVTACLO_A, model_m32rx_mvtaclo_a, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_MVTC, model_m32rx_mvtc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_NEG, model_m32rx_neg, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_NOP, model_m32rx_nop, { { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
+ { M32RXF_INSN_NOT, model_m32rx_not, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_RAC_DSI, model_m32rx_rac_dsi, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
+ { M32RXF_INSN_RACH_DSI, model_m32rx_rach_dsi, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
+ { M32RXF_INSN_RTE, model_m32rx_rte, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_SETH, model_m32rx_seth, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_SLL, model_m32rx_sll, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_SLL3, model_m32rx_sll3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_SLLI, model_m32rx_slli, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_SRA, model_m32rx_sra, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_SRA3, model_m32rx_sra3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_SRAI, model_m32rx_srai, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_SRL, model_m32rx_srl, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_SRL3, model_m32rx_srl3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_SRLI, model_m32rx_srli, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_ST, model_m32rx_st, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
+ { M32RXF_INSN_ST_D, model_m32rx_st_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
+ { M32RXF_INSN_STB, model_m32rx_stb, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
+ { M32RXF_INSN_STB_D, model_m32rx_stb_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
+ { M32RXF_INSN_STH, model_m32rx_sth, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
+ { M32RXF_INSN_STH_D, model_m32rx_sth_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
+ { M32RXF_INSN_ST_PLUS, model_m32rx_st_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
+ { M32RXF_INSN_ST_MINUS, model_m32rx_st_minus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
+ { M32RXF_INSN_SUB, model_m32rx_sub, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_SUBV, model_m32rx_subv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_SUBX, model_m32rx_subx, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_TRAP, model_m32rx_trap, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_UNLOCK, model_m32rx_unlock, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
+ { M32RXF_INSN_SATB, model_m32rx_satb, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_SATH, model_m32rx_sath, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_SAT, model_m32rx_sat, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_PCMPBZ, model_m32rx_pcmpbz, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
+ { M32RXF_INSN_SADD, model_m32rx_sadd, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
+ { M32RXF_INSN_MACWU1, model_m32rx_macwu1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
+ { M32RXF_INSN_MSBLO, model_m32rx_msblo, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
+ { M32RXF_INSN_MULWU1, model_m32rx_mulwu1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
+ { M32RXF_INSN_MACLH1, model_m32rx_maclh1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
+ { M32RXF_INSN_SC, model_m32rx_sc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+ { M32RXF_INSN_SNC, model_m32rx_snc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
+};
+
+#endif /* WITH_PROFILE_MODEL_P */
+
+static void
+m32rx_model_init (SIM_CPU *cpu)
+{
+ CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_M32RX_DATA));
+}
+
+#if WITH_PROFILE_MODEL_P
+#define TIMING_DATA(td) td
+#else
+#define TIMING_DATA(td) 0
+#endif
+
+static const MODEL m32rx_models[] =
+{
+ { "m32rx", & m32rx_mach, MODEL_M32RX, TIMING_DATA (& m32rx_timing[0]), m32rx_model_init },
+ { 0 }
+};
+
+/* The properties of this cpu's implementation. */
+
+static const MACH_IMP_PROPERTIES m32rxf_imp_properties =
+{
+ sizeof (SIM_CPU),
+#if WITH_SCACHE
+ sizeof (SCACHE)
+#else
+ 0
+#endif
+};
+
+
+static void
+m32rxf_prepare_run (SIM_CPU *cpu)
+{
+ if (CPU_IDESC (cpu) == NULL)
+ m32rxf_init_idesc_table (cpu);
+}
+
+static const CGEN_INSN *
+m32rxf_get_idata (SIM_CPU *cpu, int inum)
+{
+ return CPU_IDESC (cpu) [inum].idata;
+}
+
+static void
+m32rx_init_cpu (SIM_CPU *cpu)
+{
+ CPU_REG_FETCH (cpu) = m32rxf_fetch_register;
+ CPU_REG_STORE (cpu) = m32rxf_store_register;
+ CPU_PC_FETCH (cpu) = m32rxf_h_pc_get;
+ CPU_PC_STORE (cpu) = m32rxf_h_pc_set;
+ CPU_GET_IDATA (cpu) = m32rxf_get_idata;
+ CPU_MAX_INSNS (cpu) = M32RXF_INSN_MAX;
+ CPU_INSN_NAME (cpu) = cgen_insn_name;
+ CPU_FULL_ENGINE_FN (cpu) = m32rxf_engine_run_full;
+#if WITH_FAST
+ CPU_FAST_ENGINE_FN (cpu) = m32rxf_engine_run_fast;
+#else
+ CPU_FAST_ENGINE_FN (cpu) = m32rxf_engine_run_full;
+#endif
+}
+
+const MACH m32rx_mach =
+{
+ "m32rx", "m32rx", MACH_M32RX,
+ 32, 32, & m32rx_models[0], & m32rxf_imp_properties,
+ m32rx_init_cpu,
+ m32rxf_prepare_run
+};
+
--- /dev/null
+/* Simulator instruction semantics for m32rxf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifdef DEFINE_LABELS
+
+ /* The labels have the case they have because the enum of insn types
+ is all uppercase and in the non-stdc case the insn symbol is built
+ into the enum name. */
+
+ static struct {
+ int index;
+ void *label;
+ } labels[] = {
+ { M32RXF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
+ { M32RXF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
+ { M32RXF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
+ { M32RXF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
+ { M32RXF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
+ { M32RXF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
+ { M32RXF_INSN_ADD, && case_sem_INSN_ADD },
+ { M32RXF_INSN_ADD3, && case_sem_INSN_ADD3 },
+ { M32RXF_INSN_AND, && case_sem_INSN_AND },
+ { M32RXF_INSN_AND3, && case_sem_INSN_AND3 },
+ { M32RXF_INSN_OR, && case_sem_INSN_OR },
+ { M32RXF_INSN_OR3, && case_sem_INSN_OR3 },
+ { M32RXF_INSN_XOR, && case_sem_INSN_XOR },
+ { M32RXF_INSN_XOR3, && case_sem_INSN_XOR3 },
+ { M32RXF_INSN_ADDI, && case_sem_INSN_ADDI },
+ { M32RXF_INSN_ADDV, && case_sem_INSN_ADDV },
+ { M32RXF_INSN_ADDV3, && case_sem_INSN_ADDV3 },
+ { M32RXF_INSN_ADDX, && case_sem_INSN_ADDX },
+ { M32RXF_INSN_BC8, && case_sem_INSN_BC8 },
+ { M32RXF_INSN_BC24, && case_sem_INSN_BC24 },
+ { M32RXF_INSN_BEQ, && case_sem_INSN_BEQ },
+ { M32RXF_INSN_BEQZ, && case_sem_INSN_BEQZ },
+ { M32RXF_INSN_BGEZ, && case_sem_INSN_BGEZ },
+ { M32RXF_INSN_BGTZ, && case_sem_INSN_BGTZ },
+ { M32RXF_INSN_BLEZ, && case_sem_INSN_BLEZ },
+ { M32RXF_INSN_BLTZ, && case_sem_INSN_BLTZ },
+ { M32RXF_INSN_BNEZ, && case_sem_INSN_BNEZ },
+ { M32RXF_INSN_BL8, && case_sem_INSN_BL8 },
+ { M32RXF_INSN_BL24, && case_sem_INSN_BL24 },
+ { M32RXF_INSN_BCL8, && case_sem_INSN_BCL8 },
+ { M32RXF_INSN_BCL24, && case_sem_INSN_BCL24 },
+ { M32RXF_INSN_BNC8, && case_sem_INSN_BNC8 },
+ { M32RXF_INSN_BNC24, && case_sem_INSN_BNC24 },
+ { M32RXF_INSN_BNE, && case_sem_INSN_BNE },
+ { M32RXF_INSN_BRA8, && case_sem_INSN_BRA8 },
+ { M32RXF_INSN_BRA24, && case_sem_INSN_BRA24 },
+ { M32RXF_INSN_BNCL8, && case_sem_INSN_BNCL8 },
+ { M32RXF_INSN_BNCL24, && case_sem_INSN_BNCL24 },
+ { M32RXF_INSN_CMP, && case_sem_INSN_CMP },
+ { M32RXF_INSN_CMPI, && case_sem_INSN_CMPI },
+ { M32RXF_INSN_CMPU, && case_sem_INSN_CMPU },
+ { M32RXF_INSN_CMPUI, && case_sem_INSN_CMPUI },
+ { M32RXF_INSN_CMPEQ, && case_sem_INSN_CMPEQ },
+ { M32RXF_INSN_CMPZ, && case_sem_INSN_CMPZ },
+ { M32RXF_INSN_DIV, && case_sem_INSN_DIV },
+ { M32RXF_INSN_DIVU, && case_sem_INSN_DIVU },
+ { M32RXF_INSN_REM, && case_sem_INSN_REM },
+ { M32RXF_INSN_REMU, && case_sem_INSN_REMU },
+ { M32RXF_INSN_DIVH, && case_sem_INSN_DIVH },
+ { M32RXF_INSN_JC, && case_sem_INSN_JC },
+ { M32RXF_INSN_JNC, && case_sem_INSN_JNC },
+ { M32RXF_INSN_JL, && case_sem_INSN_JL },
+ { M32RXF_INSN_JMP, && case_sem_INSN_JMP },
+ { M32RXF_INSN_LD, && case_sem_INSN_LD },
+ { M32RXF_INSN_LD_D, && case_sem_INSN_LD_D },
+ { M32RXF_INSN_LDB, && case_sem_INSN_LDB },
+ { M32RXF_INSN_LDB_D, && case_sem_INSN_LDB_D },
+ { M32RXF_INSN_LDH, && case_sem_INSN_LDH },
+ { M32RXF_INSN_LDH_D, && case_sem_INSN_LDH_D },
+ { M32RXF_INSN_LDUB, && case_sem_INSN_LDUB },
+ { M32RXF_INSN_LDUB_D, && case_sem_INSN_LDUB_D },
+ { M32RXF_INSN_LDUH, && case_sem_INSN_LDUH },
+ { M32RXF_INSN_LDUH_D, && case_sem_INSN_LDUH_D },
+ { M32RXF_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS },
+ { M32RXF_INSN_LD24, && case_sem_INSN_LD24 },
+ { M32RXF_INSN_LDI8, && case_sem_INSN_LDI8 },
+ { M32RXF_INSN_LDI16, && case_sem_INSN_LDI16 },
+ { M32RXF_INSN_LOCK, && case_sem_INSN_LOCK },
+ { M32RXF_INSN_MACHI_A, && case_sem_INSN_MACHI_A },
+ { M32RXF_INSN_MACLO_A, && case_sem_INSN_MACLO_A },
+ { M32RXF_INSN_MACWHI_A, && case_sem_INSN_MACWHI_A },
+ { M32RXF_INSN_MACWLO_A, && case_sem_INSN_MACWLO_A },
+ { M32RXF_INSN_MUL, && case_sem_INSN_MUL },
+ { M32RXF_INSN_MULHI_A, && case_sem_INSN_MULHI_A },
+ { M32RXF_INSN_MULLO_A, && case_sem_INSN_MULLO_A },
+ { M32RXF_INSN_MULWHI_A, && case_sem_INSN_MULWHI_A },
+ { M32RXF_INSN_MULWLO_A, && case_sem_INSN_MULWLO_A },
+ { M32RXF_INSN_MV, && case_sem_INSN_MV },
+ { M32RXF_INSN_MVFACHI_A, && case_sem_INSN_MVFACHI_A },
+ { M32RXF_INSN_MVFACLO_A, && case_sem_INSN_MVFACLO_A },
+ { M32RXF_INSN_MVFACMI_A, && case_sem_INSN_MVFACMI_A },
+ { M32RXF_INSN_MVFC, && case_sem_INSN_MVFC },
+ { M32RXF_INSN_MVTACHI_A, && case_sem_INSN_MVTACHI_A },
+ { M32RXF_INSN_MVTACLO_A, && case_sem_INSN_MVTACLO_A },
+ { M32RXF_INSN_MVTC, && case_sem_INSN_MVTC },
+ { M32RXF_INSN_NEG, && case_sem_INSN_NEG },
+ { M32RXF_INSN_NOP, && case_sem_INSN_NOP },
+ { M32RXF_INSN_NOT, && case_sem_INSN_NOT },
+ { M32RXF_INSN_RAC_DSI, && case_sem_INSN_RAC_DSI },
+ { M32RXF_INSN_RACH_DSI, && case_sem_INSN_RACH_DSI },
+ { M32RXF_INSN_RTE, && case_sem_INSN_RTE },
+ { M32RXF_INSN_SETH, && case_sem_INSN_SETH },
+ { M32RXF_INSN_SLL, && case_sem_INSN_SLL },
+ { M32RXF_INSN_SLL3, && case_sem_INSN_SLL3 },
+ { M32RXF_INSN_SLLI, && case_sem_INSN_SLLI },
+ { M32RXF_INSN_SRA, && case_sem_INSN_SRA },
+ { M32RXF_INSN_SRA3, && case_sem_INSN_SRA3 },
+ { M32RXF_INSN_SRAI, && case_sem_INSN_SRAI },
+ { M32RXF_INSN_SRL, && case_sem_INSN_SRL },
+ { M32RXF_INSN_SRL3, && case_sem_INSN_SRL3 },
+ { M32RXF_INSN_SRLI, && case_sem_INSN_SRLI },
+ { M32RXF_INSN_ST, && case_sem_INSN_ST },
+ { M32RXF_INSN_ST_D, && case_sem_INSN_ST_D },
+ { M32RXF_INSN_STB, && case_sem_INSN_STB },
+ { M32RXF_INSN_STB_D, && case_sem_INSN_STB_D },
+ { M32RXF_INSN_STH, && case_sem_INSN_STH },
+ { M32RXF_INSN_STH_D, && case_sem_INSN_STH_D },
+ { M32RXF_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS },
+ { M32RXF_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS },
+ { M32RXF_INSN_SUB, && case_sem_INSN_SUB },
+ { M32RXF_INSN_SUBV, && case_sem_INSN_SUBV },
+ { M32RXF_INSN_SUBX, && case_sem_INSN_SUBX },
+ { M32RXF_INSN_TRAP, && case_sem_INSN_TRAP },
+ { M32RXF_INSN_UNLOCK, && case_sem_INSN_UNLOCK },
+ { M32RXF_INSN_SATB, && case_sem_INSN_SATB },
+ { M32RXF_INSN_SATH, && case_sem_INSN_SATH },
+ { M32RXF_INSN_SAT, && case_sem_INSN_SAT },
+ { M32RXF_INSN_PCMPBZ, && case_sem_INSN_PCMPBZ },
+ { M32RXF_INSN_SADD, && case_sem_INSN_SADD },
+ { M32RXF_INSN_MACWU1, && case_sem_INSN_MACWU1 },
+ { M32RXF_INSN_MSBLO, && case_sem_INSN_MSBLO },
+ { M32RXF_INSN_MULWU1, && case_sem_INSN_MULWU1 },
+ { M32RXF_INSN_MACLH1, && case_sem_INSN_MACLH1 },
+ { M32RXF_INSN_SC, && case_sem_INSN_SC },
+ { M32RXF_INSN_SNC, && case_sem_INSN_SNC },
+ { M32RXF_INSN_PAR_ADD, && case_sem_INSN_PAR_ADD },
+ { M32RXF_INSN_WRITE_ADD, && case_sem_INSN_WRITE_ADD },
+ { M32RXF_INSN_PAR_AND, && case_sem_INSN_PAR_AND },
+ { M32RXF_INSN_WRITE_AND, && case_sem_INSN_WRITE_AND },
+ { M32RXF_INSN_PAR_OR, && case_sem_INSN_PAR_OR },
+ { M32RXF_INSN_WRITE_OR, && case_sem_INSN_WRITE_OR },
+ { M32RXF_INSN_PAR_XOR, && case_sem_INSN_PAR_XOR },
+ { M32RXF_INSN_WRITE_XOR, && case_sem_INSN_WRITE_XOR },
+ { M32RXF_INSN_PAR_ADDI, && case_sem_INSN_PAR_ADDI },
+ { M32RXF_INSN_WRITE_ADDI, && case_sem_INSN_WRITE_ADDI },
+ { M32RXF_INSN_PAR_ADDV, && case_sem_INSN_PAR_ADDV },
+ { M32RXF_INSN_WRITE_ADDV, && case_sem_INSN_WRITE_ADDV },
+ { M32RXF_INSN_PAR_ADDX, && case_sem_INSN_PAR_ADDX },
+ { M32RXF_INSN_WRITE_ADDX, && case_sem_INSN_WRITE_ADDX },
+ { M32RXF_INSN_PAR_BC8, && case_sem_INSN_PAR_BC8 },
+ { M32RXF_INSN_WRITE_BC8, && case_sem_INSN_WRITE_BC8 },
+ { M32RXF_INSN_PAR_BL8, && case_sem_INSN_PAR_BL8 },
+ { M32RXF_INSN_WRITE_BL8, && case_sem_INSN_WRITE_BL8 },
+ { M32RXF_INSN_PAR_BCL8, && case_sem_INSN_PAR_BCL8 },
+ { M32RXF_INSN_WRITE_BCL8, && case_sem_INSN_WRITE_BCL8 },
+ { M32RXF_INSN_PAR_BNC8, && case_sem_INSN_PAR_BNC8 },
+ { M32RXF_INSN_WRITE_BNC8, && case_sem_INSN_WRITE_BNC8 },
+ { M32RXF_INSN_PAR_BRA8, && case_sem_INSN_PAR_BRA8 },
+ { M32RXF_INSN_WRITE_BRA8, && case_sem_INSN_WRITE_BRA8 },
+ { M32RXF_INSN_PAR_BNCL8, && case_sem_INSN_PAR_BNCL8 },
+ { M32RXF_INSN_WRITE_BNCL8, && case_sem_INSN_WRITE_BNCL8 },
+ { M32RXF_INSN_PAR_CMP, && case_sem_INSN_PAR_CMP },
+ { M32RXF_INSN_WRITE_CMP, && case_sem_INSN_WRITE_CMP },
+ { M32RXF_INSN_PAR_CMPU, && case_sem_INSN_PAR_CMPU },
+ { M32RXF_INSN_WRITE_CMPU, && case_sem_INSN_WRITE_CMPU },
+ { M32RXF_INSN_PAR_CMPEQ, && case_sem_INSN_PAR_CMPEQ },
+ { M32RXF_INSN_WRITE_CMPEQ, && case_sem_INSN_WRITE_CMPEQ },
+ { M32RXF_INSN_PAR_CMPZ, && case_sem_INSN_PAR_CMPZ },
+ { M32RXF_INSN_WRITE_CMPZ, && case_sem_INSN_WRITE_CMPZ },
+ { M32RXF_INSN_PAR_JC, && case_sem_INSN_PAR_JC },
+ { M32RXF_INSN_WRITE_JC, && case_sem_INSN_WRITE_JC },
+ { M32RXF_INSN_PAR_JNC, && case_sem_INSN_PAR_JNC },
+ { M32RXF_INSN_WRITE_JNC, && case_sem_INSN_WRITE_JNC },
+ { M32RXF_INSN_PAR_JL, && case_sem_INSN_PAR_JL },
+ { M32RXF_INSN_WRITE_JL, && case_sem_INSN_WRITE_JL },
+ { M32RXF_INSN_PAR_JMP, && case_sem_INSN_PAR_JMP },
+ { M32RXF_INSN_WRITE_JMP, && case_sem_INSN_WRITE_JMP },
+ { M32RXF_INSN_PAR_LD, && case_sem_INSN_PAR_LD },
+ { M32RXF_INSN_WRITE_LD, && case_sem_INSN_WRITE_LD },
+ { M32RXF_INSN_PAR_LDB, && case_sem_INSN_PAR_LDB },
+ { M32RXF_INSN_WRITE_LDB, && case_sem_INSN_WRITE_LDB },
+ { M32RXF_INSN_PAR_LDH, && case_sem_INSN_PAR_LDH },
+ { M32RXF_INSN_WRITE_LDH, && case_sem_INSN_WRITE_LDH },
+ { M32RXF_INSN_PAR_LDUB, && case_sem_INSN_PAR_LDUB },
+ { M32RXF_INSN_WRITE_LDUB, && case_sem_INSN_WRITE_LDUB },
+ { M32RXF_INSN_PAR_LDUH, && case_sem_INSN_PAR_LDUH },
+ { M32RXF_INSN_WRITE_LDUH, && case_sem_INSN_WRITE_LDUH },
+ { M32RXF_INSN_PAR_LD_PLUS, && case_sem_INSN_PAR_LD_PLUS },
+ { M32RXF_INSN_WRITE_LD_PLUS, && case_sem_INSN_WRITE_LD_PLUS },
+ { M32RXF_INSN_PAR_LDI8, && case_sem_INSN_PAR_LDI8 },
+ { M32RXF_INSN_WRITE_LDI8, && case_sem_INSN_WRITE_LDI8 },
+ { M32RXF_INSN_PAR_LOCK, && case_sem_INSN_PAR_LOCK },
+ { M32RXF_INSN_WRITE_LOCK, && case_sem_INSN_WRITE_LOCK },
+ { M32RXF_INSN_PAR_MACHI_A, && case_sem_INSN_PAR_MACHI_A },
+ { M32RXF_INSN_WRITE_MACHI_A, && case_sem_INSN_WRITE_MACHI_A },
+ { M32RXF_INSN_PAR_MACLO_A, && case_sem_INSN_PAR_MACLO_A },
+ { M32RXF_INSN_WRITE_MACLO_A, && case_sem_INSN_WRITE_MACLO_A },
+ { M32RXF_INSN_PAR_MACWHI_A, && case_sem_INSN_PAR_MACWHI_A },
+ { M32RXF_INSN_WRITE_MACWHI_A, && case_sem_INSN_WRITE_MACWHI_A },
+ { M32RXF_INSN_PAR_MACWLO_A, && case_sem_INSN_PAR_MACWLO_A },
+ { M32RXF_INSN_WRITE_MACWLO_A, && case_sem_INSN_WRITE_MACWLO_A },
+ { M32RXF_INSN_PAR_MUL, && case_sem_INSN_PAR_MUL },
+ { M32RXF_INSN_WRITE_MUL, && case_sem_INSN_WRITE_MUL },
+ { M32RXF_INSN_PAR_MULHI_A, && case_sem_INSN_PAR_MULHI_A },
+ { M32RXF_INSN_WRITE_MULHI_A, && case_sem_INSN_WRITE_MULHI_A },
+ { M32RXF_INSN_PAR_MULLO_A, && case_sem_INSN_PAR_MULLO_A },
+ { M32RXF_INSN_WRITE_MULLO_A, && case_sem_INSN_WRITE_MULLO_A },
+ { M32RXF_INSN_PAR_MULWHI_A, && case_sem_INSN_PAR_MULWHI_A },
+ { M32RXF_INSN_WRITE_MULWHI_A, && case_sem_INSN_WRITE_MULWHI_A },
+ { M32RXF_INSN_PAR_MULWLO_A, && case_sem_INSN_PAR_MULWLO_A },
+ { M32RXF_INSN_WRITE_MULWLO_A, && case_sem_INSN_WRITE_MULWLO_A },
+ { M32RXF_INSN_PAR_MV, && case_sem_INSN_PAR_MV },
+ { M32RXF_INSN_WRITE_MV, && case_sem_INSN_WRITE_MV },
+ { M32RXF_INSN_PAR_MVFACHI_A, && case_sem_INSN_PAR_MVFACHI_A },
+ { M32RXF_INSN_WRITE_MVFACHI_A, && case_sem_INSN_WRITE_MVFACHI_A },
+ { M32RXF_INSN_PAR_MVFACLO_A, && case_sem_INSN_PAR_MVFACLO_A },
+ { M32RXF_INSN_WRITE_MVFACLO_A, && case_sem_INSN_WRITE_MVFACLO_A },
+ { M32RXF_INSN_PAR_MVFACMI_A, && case_sem_INSN_PAR_MVFACMI_A },
+ { M32RXF_INSN_WRITE_MVFACMI_A, && case_sem_INSN_WRITE_MVFACMI_A },
+ { M32RXF_INSN_PAR_MVFC, && case_sem_INSN_PAR_MVFC },
+ { M32RXF_INSN_WRITE_MVFC, && case_sem_INSN_WRITE_MVFC },
+ { M32RXF_INSN_PAR_MVTACHI_A, && case_sem_INSN_PAR_MVTACHI_A },
+ { M32RXF_INSN_WRITE_MVTACHI_A, && case_sem_INSN_WRITE_MVTACHI_A },
+ { M32RXF_INSN_PAR_MVTACLO_A, && case_sem_INSN_PAR_MVTACLO_A },
+ { M32RXF_INSN_WRITE_MVTACLO_A, && case_sem_INSN_WRITE_MVTACLO_A },
+ { M32RXF_INSN_PAR_MVTC, && case_sem_INSN_PAR_MVTC },
+ { M32RXF_INSN_WRITE_MVTC, && case_sem_INSN_WRITE_MVTC },
+ { M32RXF_INSN_PAR_NEG, && case_sem_INSN_PAR_NEG },
+ { M32RXF_INSN_WRITE_NEG, && case_sem_INSN_WRITE_NEG },
+ { M32RXF_INSN_PAR_NOP, && case_sem_INSN_PAR_NOP },
+ { M32RXF_INSN_WRITE_NOP, && case_sem_INSN_WRITE_NOP },
+ { M32RXF_INSN_PAR_NOT, && case_sem_INSN_PAR_NOT },
+ { M32RXF_INSN_WRITE_NOT, && case_sem_INSN_WRITE_NOT },
+ { M32RXF_INSN_PAR_RAC_DSI, && case_sem_INSN_PAR_RAC_DSI },
+ { M32RXF_INSN_WRITE_RAC_DSI, && case_sem_INSN_WRITE_RAC_DSI },
+ { M32RXF_INSN_PAR_RACH_DSI, && case_sem_INSN_PAR_RACH_DSI },
+ { M32RXF_INSN_WRITE_RACH_DSI, && case_sem_INSN_WRITE_RACH_DSI },
+ { M32RXF_INSN_PAR_RTE, && case_sem_INSN_PAR_RTE },
+ { M32RXF_INSN_WRITE_RTE, && case_sem_INSN_WRITE_RTE },
+ { M32RXF_INSN_PAR_SLL, && case_sem_INSN_PAR_SLL },
+ { M32RXF_INSN_WRITE_SLL, && case_sem_INSN_WRITE_SLL },
+ { M32RXF_INSN_PAR_SLLI, && case_sem_INSN_PAR_SLLI },
+ { M32RXF_INSN_WRITE_SLLI, && case_sem_INSN_WRITE_SLLI },
+ { M32RXF_INSN_PAR_SRA, && case_sem_INSN_PAR_SRA },
+ { M32RXF_INSN_WRITE_SRA, && case_sem_INSN_WRITE_SRA },
+ { M32RXF_INSN_PAR_SRAI, && case_sem_INSN_PAR_SRAI },
+ { M32RXF_INSN_WRITE_SRAI, && case_sem_INSN_WRITE_SRAI },
+ { M32RXF_INSN_PAR_SRL, && case_sem_INSN_PAR_SRL },
+ { M32RXF_INSN_WRITE_SRL, && case_sem_INSN_WRITE_SRL },
+ { M32RXF_INSN_PAR_SRLI, && case_sem_INSN_PAR_SRLI },
+ { M32RXF_INSN_WRITE_SRLI, && case_sem_INSN_WRITE_SRLI },
+ { M32RXF_INSN_PAR_ST, && case_sem_INSN_PAR_ST },
+ { M32RXF_INSN_WRITE_ST, && case_sem_INSN_WRITE_ST },
+ { M32RXF_INSN_PAR_STB, && case_sem_INSN_PAR_STB },
+ { M32RXF_INSN_WRITE_STB, && case_sem_INSN_WRITE_STB },
+ { M32RXF_INSN_PAR_STH, && case_sem_INSN_PAR_STH },
+ { M32RXF_INSN_WRITE_STH, && case_sem_INSN_WRITE_STH },
+ { M32RXF_INSN_PAR_ST_PLUS, && case_sem_INSN_PAR_ST_PLUS },
+ { M32RXF_INSN_WRITE_ST_PLUS, && case_sem_INSN_WRITE_ST_PLUS },
+ { M32RXF_INSN_PAR_ST_MINUS, && case_sem_INSN_PAR_ST_MINUS },
+ { M32RXF_INSN_WRITE_ST_MINUS, && case_sem_INSN_WRITE_ST_MINUS },
+ { M32RXF_INSN_PAR_SUB, && case_sem_INSN_PAR_SUB },
+ { M32RXF_INSN_WRITE_SUB, && case_sem_INSN_WRITE_SUB },
+ { M32RXF_INSN_PAR_SUBV, && case_sem_INSN_PAR_SUBV },
+ { M32RXF_INSN_WRITE_SUBV, && case_sem_INSN_WRITE_SUBV },
+ { M32RXF_INSN_PAR_SUBX, && case_sem_INSN_PAR_SUBX },
+ { M32RXF_INSN_WRITE_SUBX, && case_sem_INSN_WRITE_SUBX },
+ { M32RXF_INSN_PAR_TRAP, && case_sem_INSN_PAR_TRAP },
+ { M32RXF_INSN_WRITE_TRAP, && case_sem_INSN_WRITE_TRAP },
+ { M32RXF_INSN_PAR_UNLOCK, && case_sem_INSN_PAR_UNLOCK },
+ { M32RXF_INSN_WRITE_UNLOCK, && case_sem_INSN_WRITE_UNLOCK },
+ { M32RXF_INSN_PAR_PCMPBZ, && case_sem_INSN_PAR_PCMPBZ },
+ { M32RXF_INSN_WRITE_PCMPBZ, && case_sem_INSN_WRITE_PCMPBZ },
+ { M32RXF_INSN_PAR_SADD, && case_sem_INSN_PAR_SADD },
+ { M32RXF_INSN_WRITE_SADD, && case_sem_INSN_WRITE_SADD },
+ { M32RXF_INSN_PAR_MACWU1, && case_sem_INSN_PAR_MACWU1 },
+ { M32RXF_INSN_WRITE_MACWU1, && case_sem_INSN_WRITE_MACWU1 },
+ { M32RXF_INSN_PAR_MSBLO, && case_sem_INSN_PAR_MSBLO },
+ { M32RXF_INSN_WRITE_MSBLO, && case_sem_INSN_WRITE_MSBLO },
+ { M32RXF_INSN_PAR_MULWU1, && case_sem_INSN_PAR_MULWU1 },
+ { M32RXF_INSN_WRITE_MULWU1, && case_sem_INSN_WRITE_MULWU1 },
+ { M32RXF_INSN_PAR_MACLH1, && case_sem_INSN_PAR_MACLH1 },
+ { M32RXF_INSN_WRITE_MACLH1, && case_sem_INSN_WRITE_MACLH1 },
+ { M32RXF_INSN_PAR_SC, && case_sem_INSN_PAR_SC },
+ { M32RXF_INSN_WRITE_SC, && case_sem_INSN_WRITE_SC },
+ { M32RXF_INSN_PAR_SNC, && case_sem_INSN_PAR_SNC },
+ { M32RXF_INSN_WRITE_SNC, && case_sem_INSN_WRITE_SNC },
+ { 0, 0 }
+ };
+ int i;
+
+ for (i = 0; labels[i].label != 0; ++i)
+ {
+#if FAST_P
+ CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
+#else
+ CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
+#endif
+ }
+
+#undef DEFINE_LABELS
+#endif /* DEFINE_LABELS */
+
+#ifdef DEFINE_SWITCH
+
+/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
+ off frills like tracing and profiling. */
+/* FIXME: A better way would be to have TRACE_RESULT check for something
+ that can cause it to be optimized out. Another way would be to emit
+ special handlers into the instruction "stream". */
+
+#if FAST_P
+#undef TRACE_RESULT
+#define TRACE_RESULT(cpu, abuf, name, type, val)
+#endif
+
+#undef GET_ATTR
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+
+{
+
+#if WITH_SCACHE_PBB
+
+/* Branch to next handler without going around main loop. */
+#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
+SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
+
+#else /* ! WITH_SCACHE_PBB */
+
+#define NEXT(vpc) BREAK (sem)
+#ifdef __GNUC__
+#if FAST_P
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
+#else
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
+#endif
+#else
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
+#endif
+
+#endif /* ! WITH_SCACHE_PBB */
+
+ {
+
+ CASE (sem, INSN_X_INVALID) : /* --invalid-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+ /* Update the recorded pc in the cpu state struct.
+ Only necessary for WITH_SCACHE case, but to avoid the
+ conditional compilation .... */
+ SET_H_PC (pc);
+ /* Virtual insns have zero size. Overwrite vpc with address of next insn
+ using the default-insn-bitsize spec. When executing insns in parallel
+ we may want to queue the fault and continue execution. */
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+ vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_AFTER) : /* --after-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_M32RXF
+ m32rxf_pbb_after (current_cpu, sem_arg);
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_BEFORE) : /* --before-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_M32RXF
+ m32rxf_pbb_before (current_cpu, sem_arg);
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_M32RXF
+#ifdef DEFINE_SWITCH
+ vpc = m32rxf_pbb_cti_chain (current_cpu, sem_arg,
+ pbb_br_type, pbb_br_npc);
+ BREAK (sem);
+#else
+ /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
+ vpc = m32rxf_pbb_cti_chain (current_cpu, sem_arg,
+ CPU_PBB_BR_TYPE (current_cpu),
+ CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_CHAIN) : /* --chain-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_M32RXF
+ vpc = m32rxf_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+ BREAK (sem);
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_BEGIN) : /* --begin-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_M32RXF
+#ifdef DEFINE_SWITCH
+ /* In the switch case FAST_P is a constant, allowing several optimizations
+ in any called inline functions. */
+ vpc = m32rxf_pbb_begin (current_cpu, FAST_P);
+#else
+ vpc = m32rxf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD) : /* add $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND) : /* and $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_and3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR) : /* or $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_and3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR) : /* xor $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_and3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDV) : /* addv $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI temp0;BI temp1;
+ temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
+ temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
+ {
+ SI opval = temp0;
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+ {
+ BI opval = temp1;
+ CPU (h_cond) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI temp0;BI temp1;
+ temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
+ temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
+ {
+ SI opval = temp0;
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+ {
+ BI opval = temp1;
+ CPU (h_cond) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDX) : /* addx $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI temp0;BI temp1;
+ temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+ temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+ {
+ SI opval = temp0;
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+ {
+ BI opval = temp1;
+ CPU (h_cond) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BC8) : /* bc.s $disp8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cond)) {
+ {
+ USI opval = FLD (i_disp8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BC24) : /* bc.l $disp24 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl24.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (CPU (h_cond)) {
+ {
+ USI opval = FLD (i_disp24);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
+ {
+ USI opval = FLD (i_disp16);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (* FLD (i_src2), 0)) {
+ {
+ USI opval = FLD (i_disp16);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GESI (* FLD (i_src2), 0)) {
+ {
+ USI opval = FLD (i_disp16);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GTSI (* FLD (i_src2), 0)) {
+ {
+ USI opval = FLD (i_disp16);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LESI (* FLD (i_src2), 0)) {
+ {
+ USI opval = FLD (i_disp16);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LTSI (* FLD (i_src2), 0)) {
+ {
+ USI opval = FLD (i_disp16);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_src2), 0)) {
+ {
+ USI opval = FLD (i_disp16);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BL8) : /* bl.s $disp8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), 4);
+ CPU (h_gr[((UINT) 14)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_disp8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BL24) : /* bl.l $disp24 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl24.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ CPU (h_gr[((UINT) 14)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_disp24);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCL8) : /* bcl.s $disp8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cond)) {
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), 4);
+ CPU (h_gr[((UINT) 14)]) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_disp8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCL24) : /* bcl.l $disp24 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl24.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (CPU (h_cond)) {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ CPU (h_gr[((UINT) 14)]) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_disp24);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cond))) {
+ {
+ USI opval = FLD (i_disp8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl24.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (CPU (h_cond))) {
+ {
+ USI opval = FLD (i_disp24);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_src1), * FLD (i_src2))) {
+ {
+ USI opval = FLD (i_disp16);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRA8) : /* bra.s $disp8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ USI opval = FLD (i_disp8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRA24) : /* bra.l $disp24 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl24.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = FLD (i_disp24);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BNCL8) : /* bncl.s $disp8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cond))) {
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), 4);
+ CPU (h_gr[((UINT) 14)]) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_disp8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BNCL24) : /* bncl.l $disp24 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl24.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (CPU (h_cond))) {
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ CPU (h_gr[((UINT) 14)]) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_disp24);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
+ CPU (h_cond) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_d.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = LTSI (* FLD (i_src2), FLD (f_simm16));
+ CPU (h_cond) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
+ CPU (h_cond) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_d.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16));
+ CPU (h_cond) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPEQ) : /* cmpeq $src1,$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = EQSI (* FLD (i_src1), * FLD (i_src2));
+ CPU (h_cond) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPZ) : /* cmpz $src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = EQSI (* FLD (i_src2), 0);
+ CPU (h_cond) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIV) : /* div $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+ {
+ SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr));
+ * FLD (i_dr) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIVU) : /* divu $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+ {
+ SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
+ * FLD (i_dr) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_REM) : /* rem $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+ {
+ SI opval = MODSI (* FLD (i_dr), * FLD (i_sr));
+ * FLD (i_dr) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_REMU) : /* remu $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+ {
+ SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
+ * FLD (i_dr) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIVH) : /* divh $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+ {
+ SI opval = DIVSI (EXTHISI (TRUNCSIHI (* FLD (i_dr))), * FLD (i_sr));
+ * FLD (i_dr) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JC) : /* jc $sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cond)) {
+ {
+ USI opval = ANDSI (* FLD (i_sr), -4);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JNC) : /* jnc $sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cond))) {
+ {
+ USI opval = ANDSI (* FLD (i_sr), -4);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JL) : /* jl $sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_jl.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI temp0;USI temp1;
+ temp0 = ADDSI (ANDSI (pc, -4), 4);
+ temp1 = ANDSI (* FLD (i_sr), -4);
+ {
+ SI opval = temp0;
+ CPU (h_gr[((UINT) 14)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
+ }
+ {
+ USI opval = temp1;
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JMP) : /* jmp $sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ USI opval = ANDSI (* FLD (i_sr), -4);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD) : /* ld $dr,@$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI temp0;SI temp1;
+ temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
+ temp1 = ADDSI (* FLD (i_sr), 4);
+ {
+ SI opval = temp0;
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+ {
+ SI opval = temp1;
+ * FLD (i_sr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld24.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = FLD (i_uimm24);
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = FLD (f_simm8);
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = FLD (f_simm16);
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ BI opval = 1;
+ CPU (h_lock) = opval;
+ TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
+ }
+ {
+ SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACHI_A) : /* machi $src1,$src2,$acc */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
+ SET_H_ACCUMS (FLD (f_acc), opval);
+ TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACLO_A) : /* maclo $src1,$src2,$acc */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
+ SET_H_ACCUMS (FLD (f_acc), opval);
+ TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACWHI_A) : /* macwhi $src1,$src2,$acc */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))));
+ SET_H_ACCUMS (FLD (f_acc), opval);
+ TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACWLO_A) : /* macwlo $src1,$src2,$acc */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))));
+ SET_H_ACCUMS (FLD (f_acc), opval);
+ TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MUL) : /* mul $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULHI_A) : /* mulhi $src1,$src2,$acc */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
+ SET_H_ACCUMS (FLD (f_acc), opval);
+ TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULLO_A) : /* mullo $src1,$src2,$acc */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
+ SET_H_ACCUMS (FLD (f_acc), opval);
+ TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))));
+ SET_H_ACCUMS (FLD (f_acc), opval);
+ TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))));
+ SET_H_ACCUMS (FLD (f_acc), opval);
+ TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MV) : /* mv $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = * FLD (i_sr);
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MVFACHI_A) : /* mvfachi $dr,$accs */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 32));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MVFACLO_A) : /* mvfaclo $dr,$accs */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = TRUNCDISI (GET_H_ACCUMS (FLD (f_accs)));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MVFACMI_A) : /* mvfacmi $dr,$accs */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 16));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvfc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_CR (FLD (f_r2));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MVTACHI_A) : /* mvtachi $src1,$accs */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
+ SET_H_ACCUMS (FLD (f_accs), opval);
+ TRACE_RESULT (current_cpu, abuf, "accs", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MVTACLO_A) : /* mvtaclo $src1,$accs */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
+ SET_H_ACCUMS (FLD (f_accs), opval);
+ TRACE_RESULT (current_cpu, abuf, "accs", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ USI opval = * FLD (i_sr);
+ SET_H_CR (FLD (f_r1), opval);
+ TRACE_RESULT (current_cpu, abuf, "dcr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEG) : /* neg $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = NEGSI (* FLD (i_sr));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NOP) : /* nop */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NOT) : /* not $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = INVSI (* FLD (i_sr));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RAC_DSI) : /* rac $accd,$accs,$imm1 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_rac_dsi.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_tmp1;
+ tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
+ tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
+ {
+ DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
+ SET_H_ACCUMS (FLD (f_accd), opval);
+ TRACE_RESULT (current_cpu, abuf, "accd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RACH_DSI) : /* rach $accd,$accs,$imm1 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_rac_dsi.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_tmp1;
+ tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
+ tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000));
+ {
+ DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0)));
+ SET_H_ACCUMS (FLD (f_accd), opval);
+ TRACE_RESULT (current_cpu, abuf, "accd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RTE) : /* rte */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ USI opval = GET_H_CR (((UINT) 14));
+ SET_H_CR (((UINT) 6), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval);
+ }
+ {
+ UQI opval = CPU (h_bpsw);
+ SET_H_PSW (opval);
+ TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
+ }
+ {
+ UQI opval = CPU (h_bbpsw);
+ CPU (h_bpsw) = opval;
+ TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_seth.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = SLLSI (FLD (f_hi16), 16);
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SLL) : /* sll $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SRA) : /* sra $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SRL) : /* srl $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST) : /* st $src1,@$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = * FLD (i_src1);
+ SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_d.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = * FLD (i_src1);
+ SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB) : /* stb $src1,@$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ QI opval = * FLD (i_src1);
+ SETMEMQI (current_cpu, pc, * FLD (i_src2), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_d.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ QI opval = * FLD (i_src1);
+ SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STH) : /* sth $src1,@$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ HI opval = * FLD (i_src1);
+ SETMEMHI (current_cpu, pc, * FLD (i_src2), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_d.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ HI opval = * FLD (i_src1);
+ SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_new_src2;
+ tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
+ {
+ SI opval = * FLD (i_src1);
+ SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_new_src2;
+ * FLD (i_src2) = opval;
+ TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_new_src2;
+ tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
+ {
+ SI opval = * FLD (i_src1);
+ SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_new_src2;
+ * FLD (i_src2) = opval;
+ TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB) : /* sub $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBV) : /* subv $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI temp0;BI temp1;
+ temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
+ temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
+ {
+ SI opval = temp0;
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+ {
+ BI opval = temp1;
+ CPU (h_cond) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBX) : /* subx $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI temp0;BI temp1;
+ temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+ temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+ {
+ SI opval = temp0;
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+ {
+ BI opval = temp1;
+ CPU (h_cond) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TRAP) : /* trap $uimm4 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_trap.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ USI opval = GET_H_CR (((UINT) 6));
+ SET_H_CR (((UINT) 14), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr-14", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (pc, 4);
+ SET_H_CR (((UINT) 6), opval);
+ TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval);
+ }
+ {
+ UQI opval = CPU (h_bpsw);
+ CPU (h_bbpsw) = opval;
+ TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
+ }
+ {
+ UQI opval = GET_H_PSW ();
+ CPU (h_bpsw) = opval;
+ TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
+ }
+ {
+ UQI opval = ANDQI (GET_H_PSW (), 128);
+ SET_H_PSW (opval);
+ TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
+ }
+ {
+ SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+if (CPU (h_lock)) {
+ {
+ SI opval = * FLD (i_src1);
+ SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_lock) = opval;
+ TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SATB) : /* satb $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = (GESI (* FLD (i_sr), 127)) ? (127) : (LESI (* FLD (i_sr), -128)) ? (-128) : (* FLD (i_sr));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SATH) : /* sath $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = (GESI (* FLD (i_sr), 32767)) ? (32767) : (LESI (* FLD (i_sr), -32768)) ? (-32768) : (* FLD (i_sr));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SAT) : /* sat $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = ((CPU (h_cond)) ? (((LTSI (* FLD (i_sr), 0)) ? (2147483647) : (0x80000000))) : (* FLD (i_sr)));
+ * FLD (i_dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_PCMPBZ) : /* pcmpbz $src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = (EQSI (ANDSI (* FLD (i_src2), 255), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 65280), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 0xff000000), 0)) ? (1) : (0);
+ CPU (h_cond) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SADD) : /* sadd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS (((UINT) 0)));
+ SET_H_ACCUMS (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "accums-0", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACWU1) : /* macwu1 $src1,$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8);
+ SET_H_ACCUMS (((UINT) 1), opval);
+ TRACE_RESULT (current_cpu, abuf, "accums-1", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSBLO) : /* msblo $src1,$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = SRADI (SLLDI (SUBDI (GET_H_ACCUM (), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8);
+ SET_H_ACCUM (opval);
+ TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULWU1) : /* mulwu1 $src1,$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535))), 16), 16);
+ SET_H_ACCUMS (((UINT) 1), opval);
+ TRACE_RESULT (current_cpu, abuf, "accums-1", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACLH1) : /* maclh1 $src1,$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8);
+ SET_H_ACCUMS (((UINT) 1), opval);
+ TRACE_RESULT (current_cpu, abuf, "accums-1", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SC) : /* sc */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (ZEXTBISI (CPU (h_cond)))
+ SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SNC) : /* snc */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (ZEXTBISI (NOTBI (CPU (h_cond))))
+ SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_ADD) : /* add $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_ADD) : /* add $dr,$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_AND) : /* and $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_AND) : /* and $dr,$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_OR) : /* or $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_OR) : /* or $dr,$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_XOR) : /* xor $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_XOR) : /* xor $dr,$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_ADDI) : /* addi $dr,$simm8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi.f
+#define OPRND(f) par_exec->operands.sfmt_addi.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_ADDI) : /* addi $dr,$simm8 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_addi.f
+#define OPRND(f) par_exec->operands.sfmt_addi.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_ADDV) : /* addv $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_addv.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI temp0;BI temp1;
+ temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
+ temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
+ {
+ SI opval = temp0;
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+ {
+ BI opval = temp1;
+ OPRND (condbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+}
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_ADDV) : /* addv $dr,$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_addv.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ CPU (h_cond) = OPRND (condbit);
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_ADDX) : /* addx $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_addx.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI temp0;BI temp1;
+ temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+ temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+ {
+ SI opval = temp0;
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+ {
+ BI opval = temp1;
+ OPRND (condbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+}
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_ADDX) : /* addx $dr,$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_addx.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ CPU (h_cond) = OPRND (condbit);
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_BC8) : /* bc.s $disp8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bc8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cond)) {
+ {
+ USI opval = FLD (i_disp8);
+ OPRND (pc) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_BC8) : /* bc.s $disp8 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bc8.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ if (written & (1 << 2))
+ {
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_BL8) : /* bl.s $disp8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bl8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), 4);
+ OPRND (h_gr_14) = opval;
+ TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_disp8);
+ OPRND (pc) = opval;
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_BL8) : /* bl.s $disp8 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bl8.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_14);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+
+ SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_BCL8) : /* bcl.s $disp8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bcl8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cond)) {
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), 4);
+ OPRND (h_gr_14) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_disp8);
+ OPRND (pc) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_BCL8) : /* bcl.s $disp8 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bcl8.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ if (written & (1 << 3))
+ {
+ CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_14);
+ }
+ if (written & (1 << 4))
+ {
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_BNC8) : /* bnc.s $disp8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bc8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cond))) {
+ {
+ USI opval = FLD (i_disp8);
+ OPRND (pc) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_BNC8) : /* bnc.s $disp8 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bc8.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ if (written & (1 << 2))
+ {
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_BRA8) : /* bra.s $disp8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bra8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ USI opval = FLD (i_disp8);
+ OPRND (pc) = opval;
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_BRA8) : /* bra.s $disp8 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bra8.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+
+ SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_BNCL8) : /* bncl.s $disp8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bcl8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cond))) {
+{
+ {
+ SI opval = ADDSI (ANDSI (pc, -4), 4);
+ OPRND (h_gr_14) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_disp8);
+ OPRND (pc) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_BNCL8) : /* bncl.s $disp8 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bcl8.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ if (written & (1 << 3))
+ {
+ CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_14);
+ }
+ if (written & (1 << 4))
+ {
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_CMP) : /* cmp $src1,$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_cmp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
+ OPRND (condbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_CMP) : /* cmp $src1,$src2 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_cmp.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ CPU (h_cond) = OPRND (condbit);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_CMPU) : /* cmpu $src1,$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_cmp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
+ OPRND (condbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_CMPU) : /* cmpu $src1,$src2 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_cmp.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ CPU (h_cond) = OPRND (condbit);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_CMPEQ) : /* cmpeq $src1,$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_cmp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = EQSI (* FLD (i_src1), * FLD (i_src2));
+ OPRND (condbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_CMPEQ) : /* cmpeq $src1,$src2 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_cmp.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ CPU (h_cond) = OPRND (condbit);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_CMPZ) : /* cmpz $src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_cmpz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = EQSI (* FLD (i_src2), 0);
+ OPRND (condbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_CMPZ) : /* cmpz $src2 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_cmpz.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ CPU (h_cond) = OPRND (condbit);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_JC) : /* jc $sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+#define OPRND(f) par_exec->operands.sfmt_jc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cond)) {
+ {
+ USI opval = ANDSI (* FLD (i_sr), -4);
+ OPRND (pc) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_JC) : /* jc $sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+#define OPRND(f) par_exec->operands.sfmt_jc.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ if (written & (1 << 2))
+ {
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_JNC) : /* jnc $sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+#define OPRND(f) par_exec->operands.sfmt_jc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cond))) {
+ {
+ USI opval = ANDSI (* FLD (i_sr), -4);
+ OPRND (pc) = opval;
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_JNC) : /* jnc $sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+#define OPRND(f) par_exec->operands.sfmt_jc.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ if (written & (1 << 2))
+ {
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_JL) : /* jl $sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_jl.f
+#define OPRND(f) par_exec->operands.sfmt_jl.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI temp0;USI temp1;
+ temp0 = ADDSI (ANDSI (pc, -4), 4);
+ temp1 = ANDSI (* FLD (i_sr), -4);
+ {
+ SI opval = temp0;
+ OPRND (h_gr_14) = opval;
+ TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
+ }
+ {
+ USI opval = temp1;
+ OPRND (pc) = opval;
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_JL) : /* jl $sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_jl.f
+#define OPRND(f) par_exec->operands.sfmt_jl.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_14);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+
+ SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_JMP) : /* jmp $sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+#define OPRND(f) par_exec->operands.sfmt_jmp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ USI opval = ANDSI (* FLD (i_sr), -4);
+ OPRND (pc) = opval;
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_JMP) : /* jmp $sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+#define OPRND(f) par_exec->operands.sfmt_jmp.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+
+ SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_LD) : /* ld $dr,@$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ld.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_LD) : /* ld $dr,@$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ld.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_LDB) : /* ldb $dr,@$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ld.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_LDB) : /* ldb $dr,@$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ld.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_LDH) : /* ldh $dr,@$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ld.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_LDH) : /* ldh $dr,@$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ld.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_LDUB) : /* ldub $dr,@$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ld.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_LDUB) : /* ldub $dr,@$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ld.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_LDUH) : /* lduh $dr,@$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ld.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_LDUH) : /* lduh $dr,@$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ld.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_LD_PLUS) : /* ld $dr,@$sr+ */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ld_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI temp0;SI temp1;
+ temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
+ temp1 = ADDSI (* FLD (i_sr), 4);
+ {
+ SI opval = temp0;
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+ {
+ SI opval = temp1;
+ OPRND (sr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+}
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_LD_PLUS) : /* ld $dr,@$sr+ */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ld_plus.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+ * FLD (i_sr) = OPRND (sr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_LDI8) : /* ldi8 $dr,$simm8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi.f
+#define OPRND(f) par_exec->operands.sfmt_ldi8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = FLD (f_simm8);
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_LDI8) : /* ldi8 $dr,$simm8 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_addi.f
+#define OPRND(f) par_exec->operands.sfmt_ldi8.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_LOCK) : /* lock $dr,@$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_lock.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ BI opval = 1;
+ OPRND (h_lock) = opval;
+ TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
+ }
+ {
+ SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+}
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_LOCK) : /* lock $dr,@$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_lock.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+ CPU (h_lock) = OPRND (h_lock);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MACHI_A) : /* machi $src1,$src2,$acc */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_machi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
+ OPRND (acc) = opval;
+ TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MACHI_A) : /* machi $src1,$src2,$acc */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_machi_a.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MACLO_A) : /* maclo $src1,$src2,$acc */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_machi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
+ OPRND (acc) = opval;
+ TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MACLO_A) : /* maclo $src1,$src2,$acc */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_machi_a.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MACWHI_A) : /* macwhi $src1,$src2,$acc */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_machi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))));
+ OPRND (acc) = opval;
+ TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MACWHI_A) : /* macwhi $src1,$src2,$acc */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_machi_a.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MACWLO_A) : /* macwlo $src1,$src2,$acc */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_machi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))));
+ OPRND (acc) = opval;
+ TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MACWLO_A) : /* macwlo $src1,$src2,$acc */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_machi_a.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MUL) : /* mul $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MUL) : /* mul $dr,$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MULHI_A) : /* mulhi $src1,$src2,$acc */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
+ OPRND (acc) = opval;
+ TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MULHI_A) : /* mulhi $src1,$src2,$acc */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MULLO_A) : /* mullo $src1,$src2,$acc */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
+ OPRND (acc) = opval;
+ TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MULLO_A) : /* mullo $src1,$src2,$acc */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))));
+ OPRND (acc) = opval;
+ TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))));
+ OPRND (acc) = opval;
+ TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MV) : /* mv $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_mv.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = * FLD (i_sr);
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MV) : /* mv $dr,$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_mv.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MVFACHI_A) : /* mvfachi $dr,$accs */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 32));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MVFACHI_A) : /* mvfachi $dr,$accs */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MVFACLO_A) : /* mvfaclo $dr,$accs */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = TRUNCDISI (GET_H_ACCUMS (FLD (f_accs)));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MVFACLO_A) : /* mvfaclo $dr,$accs */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MVFACMI_A) : /* mvfacmi $dr,$accs */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 16));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MVFACMI_A) : /* mvfacmi $dr,$accs */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MVFC) : /* mvfc $dr,$scr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvfc.f
+#define OPRND(f) par_exec->operands.sfmt_mvfc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_CR (FLD (f_r2));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MVFC) : /* mvfc $dr,$scr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_mvfc.f
+#define OPRND(f) par_exec->operands.sfmt_mvfc.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MVTACHI_A) : /* mvtachi $src1,$accs */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
+ OPRND (accs) = opval;
+ TRACE_RESULT (current_cpu, abuf, "accs", 'D', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MVTACHI_A) : /* mvtachi $src1,$accs */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SET_H_ACCUMS (FLD (f_accs), OPRND (accs));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MVTACLO_A) : /* mvtaclo $src1,$accs */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
+ OPRND (accs) = opval;
+ TRACE_RESULT (current_cpu, abuf, "accs", 'D', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MVTACLO_A) : /* mvtaclo $src1,$accs */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SET_H_ACCUMS (FLD (f_accs), OPRND (accs));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MVTC) : /* mvtc $sr,$dcr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+#define OPRND(f) par_exec->operands.sfmt_mvtc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ USI opval = * FLD (i_sr);
+ OPRND (dcr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dcr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MVTC) : /* mvtc $sr,$dcr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+#define OPRND(f) par_exec->operands.sfmt_mvtc.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SET_H_CR (FLD (f_r1), OPRND (dcr));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_NEG) : /* neg $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_mv.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = NEGSI (* FLD (i_sr));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_NEG) : /* neg $dr,$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_mv.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_NOP) : /* nop */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+#define OPRND(f) par_exec->operands.sfmt_nop.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_NOP) : /* nop */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_empty.f
+#define OPRND(f) par_exec->operands.sfmt_nop.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_NOT) : /* not $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_mv.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = INVSI (* FLD (i_sr));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_NOT) : /* not $dr,$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_mv.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_RAC_DSI) : /* rac $accd,$accs,$imm1 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_rac_dsi.f
+#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_tmp1;
+ tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
+ tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
+ {
+ DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
+ OPRND (accd) = opval;
+ TRACE_RESULT (current_cpu, abuf, "accd", 'D', opval);
+ }
+}
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_RAC_DSI) : /* rac $accd,$accs,$imm1 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_rac_dsi.f
+#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SET_H_ACCUMS (FLD (f_accd), OPRND (accd));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_RACH_DSI) : /* rach $accd,$accs,$imm1 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_rac_dsi.f
+#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_tmp1;
+ tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
+ tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000));
+ {
+ DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0)));
+ OPRND (accd) = opval;
+ TRACE_RESULT (current_cpu, abuf, "accd", 'D', opval);
+ }
+}
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_RACH_DSI) : /* rach $accd,$accs,$imm1 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_rac_dsi.f
+#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SET_H_ACCUMS (FLD (f_accd), OPRND (accd));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_RTE) : /* rte */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+#define OPRND(f) par_exec->operands.sfmt_rte.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
+ OPRND (pc) = opval;
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ {
+ USI opval = GET_H_CR (((UINT) 14));
+ OPRND (h_cr_6) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval);
+ }
+ {
+ UQI opval = CPU (h_bpsw);
+ OPRND (h_psw) = opval;
+ TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
+ }
+ {
+ UQI opval = CPU (h_bbpsw);
+ OPRND (h_bpsw) = opval;
+ TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
+ }
+}
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_RTE) : /* rte */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_empty.f
+#define OPRND(f) par_exec->operands.sfmt_rte.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ CPU (h_bpsw) = OPRND (h_bpsw);
+ SET_H_CR (((UINT) 6), OPRND (h_cr_6));
+ SET_H_PSW (OPRND (h_psw));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+
+ SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_SLL) : /* sll $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SLL) : /* sll $dr,$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_SLLI) : /* slli $dr,$uimm5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_slli.f
+#define OPRND(f) par_exec->operands.sfmt_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SLLI) : /* slli $dr,$uimm5 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_slli.f
+#define OPRND(f) par_exec->operands.sfmt_slli.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_SRA) : /* sra $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SRA) : /* sra $dr,$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_SRAI) : /* srai $dr,$uimm5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_slli.f
+#define OPRND(f) par_exec->operands.sfmt_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SRAI) : /* srai $dr,$uimm5 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_slli.f
+#define OPRND(f) par_exec->operands.sfmt_slli.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_SRL) : /* srl $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SRL) : /* srl $dr,$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_SRLI) : /* srli $dr,$uimm5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_slli.f
+#define OPRND(f) par_exec->operands.sfmt_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SRLI) : /* srli $dr,$uimm5 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_slli.f
+#define OPRND(f) par_exec->operands.sfmt_slli.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_ST) : /* st $src1,@$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_st.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = * FLD (i_src1);
+ OPRND (h_memory_src2_idx) = * FLD (i_src2);
+ OPRND (h_memory_src2) = opval;
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_ST) : /* st $src1,@$src2 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_st.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SETMEMSI (current_cpu, pc, OPRND (h_memory_src2_idx), OPRND (h_memory_src2));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_STB) : /* stb $src1,@$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_stb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ QI opval = * FLD (i_src1);
+ OPRND (h_memory_src2_idx) = * FLD (i_src2);
+ OPRND (h_memory_src2) = opval;
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_STB) : /* stb $src1,@$src2 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_stb.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SETMEMQI (current_cpu, pc, OPRND (h_memory_src2_idx), OPRND (h_memory_src2));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_STH) : /* sth $src1,@$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_sth.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ HI opval = * FLD (i_src1);
+ OPRND (h_memory_src2_idx) = * FLD (i_src2);
+ OPRND (h_memory_src2) = opval;
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_STH) : /* sth $src1,@$src2 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_sth.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SETMEMHI (current_cpu, pc, OPRND (h_memory_src2_idx), OPRND (h_memory_src2));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_ST_PLUS) : /* st $src1,@+$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_st_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_new_src2;
+ tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
+ {
+ SI opval = * FLD (i_src1);
+ OPRND (h_memory_new_src2_idx) = tmp_new_src2;
+ OPRND (h_memory_new_src2) = opval;
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_new_src2;
+ OPRND (src2) = opval;
+ TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
+ }
+}
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_ST_PLUS) : /* st $src1,@+$src2 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_st_plus.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SETMEMSI (current_cpu, pc, OPRND (h_memory_new_src2_idx), OPRND (h_memory_new_src2));
+ * FLD (i_src2) = OPRND (src2);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_ST_MINUS) : /* st $src1,@-$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_st_plus.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_new_src2;
+ tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
+ {
+ SI opval = * FLD (i_src1);
+ OPRND (h_memory_new_src2_idx) = tmp_new_src2;
+ OPRND (h_memory_new_src2) = opval;
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_new_src2;
+ OPRND (src2) = opval;
+ TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
+ }
+}
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_ST_MINUS) : /* st $src1,@-$src2 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_st_plus.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SETMEMSI (current_cpu, pc, OPRND (h_memory_new_src2_idx), OPRND (h_memory_new_src2));
+ * FLD (i_src2) = OPRND (src2);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_SUB) : /* sub $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SUB) : /* sub $dr,$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_SUBV) : /* subv $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_addv.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI temp0;BI temp1;
+ temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
+ temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
+ {
+ SI opval = temp0;
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+ {
+ BI opval = temp1;
+ OPRND (condbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+}
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SUBV) : /* subv $dr,$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_addv.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ CPU (h_cond) = OPRND (condbit);
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_SUBX) : /* subx $dr,$sr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_addx.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI temp0;BI temp1;
+ temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+ temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+ {
+ SI opval = temp0;
+ OPRND (dr) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
+ }
+ {
+ BI opval = temp1;
+ OPRND (condbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+}
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SUBX) : /* subx $dr,$sr */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_addx.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ CPU (h_cond) = OPRND (condbit);
+ * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_TRAP) : /* trap $uimm4 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_trap.f
+#define OPRND(f) par_exec->operands.sfmt_trap.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ USI opval = GET_H_CR (((UINT) 6));
+ OPRND (h_cr_14) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cr-14", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (pc, 4);
+ OPRND (h_cr_6) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval);
+ }
+ {
+ UQI opval = CPU (h_bpsw);
+ OPRND (h_bbpsw) = opval;
+ TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
+ }
+ {
+ UQI opval = GET_H_PSW ();
+ OPRND (h_bpsw) = opval;
+ TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
+ }
+ {
+ UQI opval = ANDQI (GET_H_PSW (), 128);
+ OPRND (h_psw) = opval;
+ TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
+ }
+ {
+ SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
+ OPRND (pc) = opval;
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_TRAP) : /* trap $uimm4 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_trap.f
+#define OPRND(f) par_exec->operands.sfmt_trap.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ CPU (h_bbpsw) = OPRND (h_bbpsw);
+ CPU (h_bpsw) = OPRND (h_bpsw);
+ SET_H_CR (((UINT) 14), OPRND (h_cr_14));
+ SET_H_CR (((UINT) 6), OPRND (h_cr_6));
+ SET_H_PSW (OPRND (h_psw));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+
+ SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_UNLOCK) : /* unlock $src1,@$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_unlock.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+if (CPU (h_lock)) {
+ {
+ SI opval = * FLD (i_src1);
+ OPRND (h_memory_src2_idx) = * FLD (i_src2);
+ OPRND (h_memory_src2) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ OPRND (h_lock) = opval;
+ TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_UNLOCK) : /* unlock $src1,@$src2 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_unlock.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ CPU (h_lock) = OPRND (h_lock);
+ if (written & (1 << 4))
+ {
+ SETMEMSI (current_cpu, pc, OPRND (h_memory_src2_idx), OPRND (h_memory_src2));
+ }
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_PCMPBZ) : /* pcmpbz $src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_cmpz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = (EQSI (ANDSI (* FLD (i_src2), 255), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 65280), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 0xff000000), 0)) ? (1) : (0);
+ OPRND (condbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_PCMPBZ) : /* pcmpbz $src2 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_cmpz.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ CPU (h_cond) = OPRND (condbit);
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_SADD) : /* sadd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+#define OPRND(f) par_exec->operands.sfmt_sadd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS (((UINT) 0)));
+ OPRND (h_accums_0) = opval;
+ TRACE_RESULT (current_cpu, abuf, "accums-0", 'D', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SADD) : /* sadd */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_empty.f
+#define OPRND(f) par_exec->operands.sfmt_sadd.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SET_H_ACCUMS (((UINT) 0), OPRND (h_accums_0));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MACWU1) : /* macwu1 $src1,$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_macwu1.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8);
+ OPRND (h_accums_1) = opval;
+ TRACE_RESULT (current_cpu, abuf, "accums-1", 'D', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MACWU1) : /* macwu1 $src1,$src2 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_macwu1.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_1));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MSBLO) : /* msblo $src1,$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_msblo.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = SRADI (SLLDI (SUBDI (GET_H_ACCUM (), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8);
+ OPRND (accum) = opval;
+ TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MSBLO) : /* msblo $src1,$src2 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_msblo.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SET_H_ACCUM (OPRND (accum));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MULWU1) : /* mulwu1 $src1,$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_mulwu1.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535))), 16), 16);
+ OPRND (h_accums_1) = opval;
+ TRACE_RESULT (current_cpu, abuf, "accums-1", 'D', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MULWU1) : /* mulwu1 $src1,$src2 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_mulwu1.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_1));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_MACLH1) : /* maclh1 $src1,$src2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_macwu1.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8);
+ OPRND (h_accums_1) = opval;
+ TRACE_RESULT (current_cpu, abuf, "accums-1", 'D', opval);
+ }
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MACLH1) : /* maclh1 $src1,$src2 */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_macwu1.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_1));
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_SC) : /* sc */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+#define OPRND(f) par_exec->operands.sfmt_sc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (ZEXTBISI (CPU (h_cond)))
+ SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SC) : /* sc */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_empty.f
+#define OPRND(f) par_exec->operands.sfmt_sc.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+ CASE (sem, INSN_PAR_SNC) : /* snc */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+#define OPRND(f) par_exec->operands.sfmt_sc.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (ZEXTBISI (NOTBI (CPU (h_cond))))
+ SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
+
+#undef OPRND
+#undef FLD
+}
+ NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SNC) : /* snc */
+ {
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_empty.f
+#define OPRND(f) par_exec->operands.sfmt_sc.f
+ int UNUSED written = abuf->written;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+
+#undef OPRND
+#undef FLD
+ }
+ NEXT (vpc);
+
+
+ }
+ ENDSWITCH (sem) /* End of semantic switch. */
+
+ /* At this point `vpc' contains the next insn to execute. */
+}
+
+#undef DEFINE_SWITCH
+#endif /* DEFINE_SWITCH */
PROFILE_LABEL_WIDTH, "Fill nops:",
sim_add_commas (buf, sizeof (buf),
CPU_M32R_MISC_PROFILE (cpu)->fillnop_count));
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32rx)
+ sim_io_printf (sd, " %-*s %s\n\n",
+ PROFILE_LABEL_WIDTH, "Parallel insns:",
+ sim_add_commas (buf, sizeof (buf),
+ CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
}
}
+
/* Main header for the m32r. */
#ifndef SIM_MAIN_H
go after here. Oh for a better language. */
#if defined (WANT_CPU_M32RBF)
M32RBF_CPU_DATA cpu_data;
+#elif defined (WANT_CPU_M32RXF)
+ M32RXF_CPU_DATA cpu_data;
#endif
};
\f
projects / binutils-gdb.git / commitdiff