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raw | patch | inline | side by side (parent: d591711)
ffmsubs number of operands reduced to match ffmadds
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 30 Apr 2023 19:00:53 +0000 (20:00 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 30 Apr 2023 19:01:01 +0000 (20:01 +0100)
openpower/isa/svfparith.mdwn patch | blob | history
openpower/isatables/minor_59.csv patch | blob | history

diff --git a/openpower/isa/svfparith.mdwn b/openpower/isa/svfparith.mdwn
index 49b43f4f495a20b782334f326dd0aa46039f5682..6579042be0c60775c74304f0045d6a00267bc565 100644 (file)
--- a/openpower/isa/svfparith.mdwn
+++ b/openpower/isa/svfparith.mdwn
@@ -203,13 +203,14 @@ Special Registers Altered:
 
 A-Form
 
-* ffmsubs FRT,FRA,FRC,FRB (Rc=0)
-* ffmsubs. FRT,FRA,FRC,FRB (Rc=1)
+* ffmsubs FRT,FRA,FRB (Rc=0)
+* ffmsubs. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
-    FRT <- FPMULADD32(FRA, FRC, FRB, 1, -1)
-    FRS <- FPMULADD32(FRA, FRC, FRB, -1, -1)
+    tmp <- FRT
+    FRT <- FPMULADD32(tmp, FRA, FRB, 1, -1)
+    FRS <- FPMULADD32(tmp, FRA, FRB, -1, -1)
 
 Special Registers Altered:
 
diff --git a/openpower/isatables/minor_59.csv b/openpower/isatables/minor_59.csv
index cf8622f8c96fcb1445b12b8b4c48c286f0301891..615b2b97915b4eb2a3f7809c8eb2af903fa48140 100644 (file)
--- a/openpower/isatables/minor_59.csv
+++ b/openpower/isatables/minor_59.csv
@@ -14,7 +14,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 -----11101,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmadds,A,,,
 -----11110,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fnmsubs,A,,,
 -----11111,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fnmadds,A,,,
------00100,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffmsubs,A,,1,3-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg
+-----00100,FPU,OP_FP_MADD,FRT,FRB,FRA,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffmsubs,A,,1,3-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg
 -----00101,FPU,OP_FP_MADD,FRT,FRB,FRA,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffmadds,A,,1,3-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg
 -----00110,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffnmsubs,A,,1,3-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg
 -----00111,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffnmadds,A,,1,3-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg