fhdl/verilog: sort clock domains by name

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 8993300e8be00c597b76a895b55b5b06b8217e80..d0cbecf8f9dc64c50f9d5c07f6b48d17d3595355 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -1,4 +1,5 @@
 from functools import partial
+from operator import itemgetter
 
 from migen.fhdl.structure import *
 from migen.fhdl.structure import _Operator, _Slice, _Assign
@@ -171,7 +172,7 @@ def _printcomb(f, ns, display_run):
 
 def _printsync(f, ns, clock_domains):
        r = ""
-       for k, v in f.sync.items():
+       for k, v in sorted(f.sync.items(), key=itemgetter(0)):
                r += "always @(posedge " + ns.get_name(clock_domains[k].clk) + ") begin\n"
                r += _printnode(ns, _AT_SIGNAL, 1, insert_reset(clock_domains[k].rst, v))
                r += "end\n\n"