/**
* Number of swapBuffers operations that have been *completed*.
*/
- u_int64_t swap_count;
+ uint64_t swap_count;
/**
* Unadjusted system time of the last buffer swap. This is the time
* swap, it has missed its deadline. If swap_interval is 0, then the
* swap deadline is 1 frame after the previous swap.
*/
- u_int64_t swap_missed_count;
+ uint64_t swap_missed_count;
/**
* Amount of time used by the last swap that missed its deadline. This
#if defined( __powerpc__ )
-static __inline__ u_int32_t
+static __inline__ uint32_t
read_MMIO_LE32( volatile void * base, unsigned long offset )
{
- u_int32_t val;
+ uint32_t val;
__asm__ __volatile__( "lwbrx %0, %1, %2 ; eieio"
: "=r" (val)
#else
-static __inline__ u_int32_t
+static __inline__ uint32_t
read_MMIO_LE32( volatile void * base, unsigned long offset )
{
- volatile u_int32_t * p = (volatile u_int32_t *) (((volatile char *) base) + offset);
+ volatile uint32_t * p = (volatile uint32_t *) (((volatile char *) base) + offset);
return LE32_TO_CPU( p[0] );
}
GLboolean
driFillInModes( __GLcontextModes ** ptr_to_modes,
GLenum fb_format, GLenum fb_type,
- const u_int8_t * depth_bits, const u_int8_t * stencil_bits,
+ const uint8_t * depth_bits, const uint8_t * stencil_bits,
unsigned num_depth_stencil_bits,
const GLenum * db_modes, unsigned num_db_modes,
int visType )
{
- static const u_int8_t bits_table[3][4] = {
+ static const uint8_t bits_table[3][4] = {
/* R G B A */
{ 5, 6, 5, 0 }, /* Any GL_UNSIGNED_SHORT_5_6_5 */
{ 8, 8, 8, 0 }, /* Any RGB with any GL_UNSIGNED_INT_8_8_8_8 */
* Given the four supported fb_type values, this results in valid array
* indices of 3, 4, 5, and 7.
*/
- static const u_int32_t masks_table_rgb[8][4] = {
+ static const uint32_t masks_table_rgb[8][4] = {
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
{ 0x000000FF, 0x0000FF00, 0x00FF0000, 0x00000000 } /* 8_8_8_8_REV */
};
- static const u_int32_t masks_table_rgba[8][4] = {
+ static const uint32_t masks_table_rgba[8][4] = {
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
{ 0x000000FF, 0x0000FF00, 0x00FF0000, 0xFF000000 }, /* 8_8_8_8_REV */
};
- static const u_int32_t masks_table_bgr[8][4] = {
+ static const uint32_t masks_table_bgr[8][4] = {
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
{ 0x00FF0000, 0x0000FF00, 0x000000FF, 0x00000000 }, /* 8_8_8_8_REV */
};
- static const u_int32_t masks_table_bgra[8][4] = {
+ static const uint32_t masks_table_bgra[8][4] = {
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
{ 0x00FF0000, 0x0000FF00, 0x000000FF, 0xFF000000 }, /* 8_8_8_8_REV */
};
- static const u_int8_t bytes_per_pixel[8] = {
+ static const uint8_t bytes_per_pixel[8] = {
0, 0, 0, 2, 2, 4, 0, 4
};
- const u_int8_t * bits;
- const u_int32_t * masks;
+ const uint8_t * bits;
+ const uint32_t * masks;
const int index = fb_type & 0x07;
__GLcontextModes * modes = *ptr_to_modes;
unsigned i;
extern GLboolean driFillInModes( __GLcontextModes ** modes,
GLenum fb_format, GLenum fb_type,
- const u_int8_t * depth_bits, const u_int8_t * stencil_bits,
+ const uint8_t * depth_bits, const uint8_t * stencil_bits,
unsigned num_depth_stencil_bits,
const GLenum * db_modes, unsigned num_db_modes, int visType );
GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
};
- u_int8_t depth_bits_array[2];
- u_int8_t stencil_bits_array[2];
+ uint8_t depth_bits_array[2];
+ uint8_t stencil_bits_array[2];
depth_bits_array[0] = depth_bits;
GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
};
- u_int8_t depth_bits_array[2];
- u_int8_t stencil_bits_array[2];
+ uint8_t depth_bits_array[2];
+ uint8_t stencil_bits_array[2];
depth_bits_array[0] = 0;
depth_bits_array[1] = depth_bits;
GLX_NONE, GLX_SWAP_UNDEFINED_OML, GLX_SWAP_COPY_OML
};
- u_int8_t depth_bits_array[3];
- u_int8_t stencil_bits_array[3];
+ uint8_t depth_bits_array[3];
+ uint8_t stencil_bits_array[3];
depth_bits_array[0] = 0;
int internalFormat;
} image[GAMMA_TEX_MAXLEVELS];
- u_int32_t TextureBaseAddr[GAMMA_TEX_MAXLEVELS];
- u_int32_t TextureAddressMode;
- u_int32_t TextureColorMode;
- u_int32_t TextureFilterMode;
- u_int32_t TextureFormat;
- u_int32_t TextureReadMode;
- u_int32_t TextureBorderColor;
+ uint32_t TextureBaseAddr[GAMMA_TEX_MAXLEVELS];
+ uint32_t TextureAddressMode;
+ uint32_t TextureColorMode;
+ uint32_t TextureFilterMode;
+ uint32_t TextureFormat;
+ uint32_t TextureReadMode;
+ uint32_t TextureBorderColor;
};
#define GAMMA_NO_PALETTE 0x0
unsigned int lastStamp;
- u_int32_t ClearColor;
- u_int32_t Color;
- u_int32_t DitherMode;
- u_int32_t ClearDepth;
- u_int32_t FogMode;
- u_int32_t AreaStippleMode;
- u_int32_t LBReadFormat;
- u_int32_t LBWriteFormat;
- u_int32_t LineMode;
- u_int32_t PointMode;
- u_int32_t TriangleMode;
- u_int32_t AntialiasMode;
+ uint32_t ClearColor;
+ uint32_t Color;
+ uint32_t DitherMode;
+ uint32_t ClearDepth;
+ uint32_t FogMode;
+ uint32_t AreaStippleMode;
+ uint32_t LBReadFormat;
+ uint32_t LBWriteFormat;
+ uint32_t LineMode;
+ uint32_t PointMode;
+ uint32_t TriangleMode;
+ uint32_t AntialiasMode;
GLfloat ViewportScaleX;
GLfloat ViewportScaleY;
GLfloat ViewportScaleZ;
WRITEF(gmesa->buf, Tr4, tc0[i][2]);
WRITEF(gmesa->buf, Tt4, tc0[i][0]);
WRITEF(gmesa->buf, Ts4, tc0[i][1]);
- WRITE(gmesa->buf, PackedColor4, *(u_int32_t*)col[i]);
+ WRITE(gmesa->buf, PackedColor4, *(uint32_t*)col[i]);
WRITEF(gmesa->buf, Vw, coord[i][3]);
WRITEF(gmesa->buf, Vz, coord[i][2]);
WRITEF(gmesa->buf, Vy, coord[i][1]);
CHECK_DMA_BUFFER(gmesa, 7);
WRITEF(gmesa->buf, Tt2, tc0[i][0]);
WRITEF(gmesa->buf, Ts2, tc0[i][1]);
- WRITE(gmesa->buf, PackedColor4, *(u_int32_t*)col[i]);
+ WRITE(gmesa->buf, PackedColor4, *(uint32_t*)col[i]);
WRITEF(gmesa->buf, Vw, coord[i][3]);
WRITEF(gmesa->buf, Vz, coord[i][2]);
WRITEF(gmesa->buf, Vy, coord[i][1]);
} else {
for (i=start; i < end; i++) {
CHECK_DMA_BUFFER(gmesa, 4);
- WRITE(gmesa->buf, PackedColor4, *(u_int32_t*)col[i]);
+ WRITE(gmesa->buf, PackedColor4, *(uint32_t*)col[i]);
WRITEF(gmesa->buf, Vz, coord[i][2]);
WRITEF(gmesa->buf, Vy, coord[i][1]);
WRITEF(gmesa->buf, Vx3, coord[i][0]);
{
gammaContextPtr gmesa = GAMMA_CONTEXT(ctx);
gammaScreenPtr gammascrn = gmesa->gammaScreen;
- u_int32_t dwords1, dwords2, i = 0;
+ uint32_t dwords1, dwords2, i = 0;
char *src = (char *)rgba[0];
GLuint read = n * gammascrn->cpp; /* Number of bytes we are expecting */
- u_int32_t data;
+ uint32_t data;
FLUSH_DMA_BUFFER(gmesa);
CHECK_DMA_BUFFER(gmesa, 16);
moredata:
- dwords1 = *(volatile u_int32_t*)(void *)(((u_int8_t*)gammascrn->regions[0].map) + (GlintOutFIFOWords));
- dwords2 = *(volatile u_int32_t*)(void *)(((u_int8_t*)gammascrn->regions[2].map) + (GlintOutFIFOWords));
+ dwords1 = *(volatile uint32_t*)(void *)(((uint8_t*)gammascrn->regions[0].map) + (GlintOutFIFOWords));
+ dwords2 = *(volatile uint32_t*)(void *)(((uint8_t*)gammascrn->regions[2].map) + (GlintOutFIFOWords));
if (dwords1) {
memcpy(src, (char*)gammascrn->regions[1].map + 0x1000, dwords1 << 2);
static void gammaUpdateAlphaMode( GLcontext *ctx )
{
gammaContextPtr gmesa = GAMMA_CONTEXT(ctx);
- u_int32_t a = gmesa->AlphaTestMode;
- u_int32_t b = gmesa->AlphaBlendMode;
- u_int32_t f = gmesa->AB_FBReadMode_Save = 0;
+ uint32_t a = gmesa->AlphaTestMode;
+ uint32_t b = gmesa->AlphaBlendMode;
+ uint32_t f = gmesa->AB_FBReadMode_Save = 0;
GLubyte refByte = (GLint) (ctx->Color.AlphaRef * 255.0);
a &= ~(AT_CompareMask | AT_RefValueMask);
static void gammaUpdateZMode( GLcontext *ctx )
{
gammaContextPtr gmesa = GAMMA_CONTEXT(ctx);
- u_int32_t z = gmesa->DepthMode;
- u_int32_t delta = gmesa->DeltaMode;
- u_int32_t window = gmesa->Window;
- u_int32_t lbread = gmesa->LBReadMode;
+ uint32_t z = gmesa->DepthMode;
+ uint32_t delta = gmesa->DeltaMode;
+ uint32_t window = gmesa->Window;
+ uint32_t lbread = gmesa->LBReadMode;
z &= ~DM_CompareMask;
static void gammaUpdateFogAttrib( GLcontext *ctx )
{
gammaContextPtr gmesa = GAMMA_CONTEXT(ctx);
- u_int32_t f = gmesa->FogMode;
- u_int32_t g = gmesa->GeometryMode;
- u_int32_t d = gmesa->DeltaMode;
+ uint32_t f = gmesa->FogMode;
+ uint32_t g = gmesa->GeometryMode;
+ uint32_t d = gmesa->DeltaMode;
if (ctx->Fog.Enabled) {
f |= FogModeEnable;
static void gammaUpdatePolygon( GLcontext *ctx )
{
gammaContextPtr gmesa = GAMMA_CONTEXT(ctx);
- u_int32_t g = gmesa->GeometryMode;
+ uint32_t g = gmesa->GeometryMode;
g &= ~(GM_PolyOffsetFillEnable | GM_PolyOffsetPointEnable |
GM_PolyOffsetLineEnable);
static void gammaUpdateCull( GLcontext *ctx )
{
gammaContextPtr gmesa = GAMMA_CONTEXT(ctx);
- u_int32_t g = gmesa->GeometryMode;
+ uint32_t g = gmesa->GeometryMode;
g &= ~(GM_PolyCullMask | GM_FFMask);
static void gammaDDShadeModel( GLcontext *ctx, GLenum mode )
{
gammaContextPtr gmesa = GAMMA_CONTEXT(ctx);
- u_int32_t g = gmesa->GeometryMode;
- u_int32_t c = gmesa->ColorDDAMode;
+ uint32_t g = gmesa->GeometryMode;
+ uint32_t c = gmesa->ColorDDAMode;
g &= ~GM_ShadingMask;
c &= ~ColorDDAShadingMask;
case GL_DITHER:
do {
- u_int32_t d = gmesa->DitherMode;
+ uint32_t d = gmesa->DitherMode;
FLUSH_BATCH( gmesa );
if ( state ) {
#if ENABLELIGHTING
case GL_LIGHTING:
do {
- u_int32_t l = gmesa->LightingMode;
+ uint32_t l = gmesa->LightingMode;
FLUSH_BATCH( gmesa );
if ( state ) {
case GL_COLOR_MATERIAL:
do {
- u_int32_t m = gmesa->MaterialMode;
+ uint32_t m = gmesa->MaterialMode;
FLUSH_BATCH( gmesa );
if ( state ) {
static void gammaSetTexWrapping(gammaTextureObjectPtr t,
GLenum wraps, GLenum wrapt)
{
- u_int32_t t1 = t->TextureAddressMode;
- u_int32_t t2 = t->TextureReadMode;
+ uint32_t t1 = t->TextureAddressMode;
+ uint32_t t2 = t->TextureReadMode;
t1 &= ~(TAM_SWrap_Mask | TAM_TWrap_Mask);
t2 &= ~(TRM_UWrap_Mask | TRM_VWrap_Mask);
GLenum minf, GLenum magf,
GLfloat bias)
{
- u_int32_t t1 = t->TextureAddressMode;
- u_int32_t t2 = t->TextureReadMode;
+ uint32_t t1 = t->TextureAddressMode;
+ uint32_t t2 = t->TextureReadMode;
t2 &= ~(TRM_Mag_Mask | TRM_Min_Mask);
static void TAG(gamma_point)( gammaContextPtr gmesa,
const gammaVertex *v0 )
{
- u_int32_t vColor;
- u_int32_t vBegin;
+ uint32_t vColor;
+ uint32_t vBegin;
vBegin = gmesa->Begin | B_PrimType_Points;
const gammaVertex *v0,
const gammaVertex *v1 )
{
- u_int32_t vColor;
- u_int32_t vBegin;
+ uint32_t vColor;
+ uint32_t vBegin;
vBegin = gmesa->Begin | B_PrimType_Lines;
const gammaVertex *v1,
const gammaVertex *v2 )
{
- u_int32_t vColor;
- u_int32_t vBegin;
+ uint32_t vColor;
+ uint32_t vBegin;
vBegin = gmesa->Begin | B_PrimType_Triangles;
const gammaVertex *v2,
const gammaVertex *v3 )
{
- u_int32_t vColor;
- u_int32_t vBegin;
+ uint32_t vColor;
+ uint32_t vBegin;
vBegin = gmesa->Begin | B_PrimType_Quads;
unsigned num_db_modes,
int visType )
{
- static const u_int8_t bits[1][4] = {
+ static const uint8_t bits[1][4] = {
{ 5, 6, 5, 0 }
};
- static const u_int32_t masks[1][4] = {
+ static const uint32_t masks[1][4] = {
{ 0x0000F800, 0x000007E0, 0x0000001F, 0x00000000 }
};
#include "intel_batchbuffer.h"
#include "drm.h"
-u_int32_t intelGetLastFrame (intelContextPtr intel)
+uint32_t intelGetLastFrame (intelContextPtr intel)
{
int ret;
- u_int32_t frame;
+ uint32_t frame;
drm_i915_getparam_t gp;
gp.param = I915_PARAM_LAST_DISPATCH;
extern GLuint intelAgpOffsetFromVirtual( intelContextPtr intel, const GLvoid *p );
extern void intelWaitIrq( intelContextPtr intel, int seq );
-extern u_int32_t intelGetLastFrame (intelContextPtr intel);
+extern uint32_t intelGetLastFrame (intelContextPtr intel);
extern int intelEmitIrqLocked( intelContextPtr intel );
#endif
GLX_NONE, GLX_SWAP_UNDEFINED_OML, GLX_SWAP_COPY_OML
};
- u_int8_t depth_bits_array[3];
- u_int8_t stencil_bits_array[3];
+ uint8_t depth_bits_array[3];
+ uint8_t stencil_bits_array[3];
depth_bits_array[0] = 0;
GLX_NONE, GLX_SWAP_UNDEFINED_OML, GLX_SWAP_COPY_OML
};
- u_int8_t depth_bits_array[3];
- u_int8_t stencil_bits_array[3];
+ uint8_t depth_bits_array[3];
+ uint8_t stencil_bits_array[3];
depth_bits_array[0] = 0;
unsigned num_db_modes,
int visType )
{
- static const u_int8_t bits[2][4] = {
+ static const uint8_t bits[2][4] = {
{ 5, 6, 5, 0 },
{ 8, 8, 8, 0 }
};
- static const u_int32_t masks[2][4] = {
+ static const uint32_t masks[2][4] = {
{ 0x0000F800, 0x000007E0, 0x0000001F, 0x00000000 },
{ 0x00FF0000, 0x0000FF00, 0x000000FF, 0x00000000 }
};
GLX_NONE, GLX_SWAP_UNDEFINED_OML, GLX_SWAP_COPY_OML
};
- u_int8_t depth_bits_array[3];
- u_int8_t stencil_bits_array[3];
+ uint8_t depth_bits_array[3];
+ uint8_t stencil_bits_array[3];
depth_bits_array[0] = 0;
#define MGA_BASE( reg ) ((unsigned long)(mmesa->mgaScreen->mmio.map))
#define MGA_ADDR( reg ) (MGA_BASE(reg) + reg)
-#define MGA_DEREF( reg ) *(volatile u_int32_t *)MGA_ADDR( reg )
+#define MGA_DEREF( reg ) *(volatile uint32_t *)MGA_ADDR( reg )
#define MGA_READ( reg ) MGA_DEREF( reg )
#endif
typedef struct nouveau_fifo_t{
int channel;
- u_int32_t* buffer;
- u_int32_t* mmio;
- u_int32_t put_base;
- u_int32_t current;
- u_int32_t put;
- u_int32_t free;
- u_int32_t max;
+ uint32_t* buffer;
+ uint32_t* mmio;
+ uint32_t put_base;
+ uint32_t current;
+ uint32_t put;
+ uint32_t free;
+ uint32_t max;
}
nouveau_fifo;
#define RING_SKIPS 8
-void WAIT_RING(nouveauContextPtr nmesa,u_int32_t size)
+void WAIT_RING(nouveauContextPtr nmesa,uint32_t size)
{
#ifdef NOUVEAU_RING_DEBUG
return;
#endif
- u_int32_t fifo_get;
+ uint32_t fifo_get;
while(nmesa->fifo.free < size+1) {
fifo_get = NV_FIFO_READ_GET();
#define NOUVEAU_RING_TRACE 1
#endif
-#define NV_READ(reg) *(volatile u_int32_t *)(nmesa->mmio + (reg))
+#define NV_READ(reg) *(volatile uint32_t *)(nmesa->mmio + (reg))
-#define NV_FIFO_READ(reg) *(volatile u_int32_t *)(nmesa->fifo.mmio + (reg/4))
-#define NV_FIFO_WRITE(reg,value) *(volatile u_int32_t *)(nmesa->fifo.mmio + (reg/4)) = value;
+#define NV_FIFO_READ(reg) *(volatile uint32_t *)(nmesa->fifo.mmio + (reg/4))
+#define NV_FIFO_WRITE(reg,value) *(volatile uint32_t *)(nmesa->fifo.mmio + (reg/4)) = value;
#define NV_FIFO_READ_GET() ((NV_FIFO_READ(NV03_FIFO_REGS_DMAGET) - nmesa->fifo.put_base) >> 2)
#define NV_FIFO_WRITE_PUT(val) do { \
if (NOUVEAU_RING_TRACE) {\
#endif
-extern void WAIT_RING(nouveauContextPtr nmesa,u_int32_t size);
+extern void WAIT_RING(nouveauContextPtr nmesa,uint32_t size);
extern void nouveau_state_cache_flush(nouveauContextPtr nmesa);
extern void nouveau_state_cache_init(nouveauContextPtr nmesa);
GLX_NONE, GLX_SWAP_UNDEFINED_OML, GLX_SWAP_COPY_OML
};
- u_int8_t depth_bits_array[4] = { 0, 16, 24, 24 };
- u_int8_t stencil_bits_array[4] = { 0, 0, 0, 8 };
+ uint8_t depth_bits_array[4] = { 0, 16, 24, 24 };
+ uint8_t stencil_bits_array[4] = { 0, 0, 0, 8 };
depth_buffer_factor = 4;
back_buffer_factor = (have_back_buffer) ? 3 : 1;
typedef struct {
nouveau_card* card;
- u_int32_t bus_type;
- u_int32_t agp_mode;
+ uint32_t bus_type;
+ uint32_t agp_mode;
GLint fbFormat;
GLfloat hw_viewport[16];
GLfloat depth_scale;
- u_int32_t ClearColor; /* Color used to clear color buffer */
- u_int32_t ClearDepth; /* Value used to clear depth buffer */
- u_int32_t ClearStencil; /* Value used to clear stencil */
+ uint32_t ClearColor; /* Color used to clear color buffer */
+ uint32_t ClearDepth; /* Value used to clear depth buffer */
+ uint32_t ClearStencil; /* Value used to clear stencil */
/* Map GL texture units onto hardware
*/
int wait = 0;
while ( 1 ) {
- u_int32_t frame = read_MMIO_LE32( R128MMIO, R128_LAST_FRAME_REG );
+ uint32_t frame = read_MMIO_LE32( R128MMIO, R128_LAST_FRAME_REG );
if ( rmesa->sarea->last_frame - frame <= R128_MAX_OUTSTANDING ) {
break;
#include "r128_reg.h"
#include "r128_lock.h"
-#define R128_BUFFER_MAX_DWORDS (R128_BUFFER_SIZE / sizeof(u_int32_t))
+#define R128_BUFFER_MAX_DWORDS (R128_BUFFER_SIZE / sizeof(uint32_t))
extern drmBufPtr r128GetBufferLocked( r128ContextPtr rmesa );
static __inline void *r128AllocDmaLow( r128ContextPtr rmesa, int count,
int vert_size )
{
- u_int32_t *head;
+ uint32_t *head;
int bytes = count * vert_size;
if ( !rmesa->vert_buf ) {
UNLOCK_HARDWARE( rmesa );
}
- head = (u_int32_t *)((char *)rmesa->vert_buf->address + rmesa->vert_buf->used);
+ head = (uint32_t *)((char *)rmesa->vert_buf->address + rmesa->vert_buf->used);
rmesa->vert_buf->used += bytes;
rmesa->num_verts += count;
GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
};
- u_int8_t depth_bits_array[2];
- u_int8_t stencil_bits_array[2];
+ uint8_t depth_bits_array[2];
+ uint8_t stencil_bits_array[2];
depth_bits_array[0] = depth_bits;
case GL_TEXTURE_LOD_BIAS:
{
- u_int32_t t = rmesa->setup.tex_cntl_c;
+ uint32_t t = rmesa->setup.tex_cntl_c;
GLint bias;
- u_int32_t b;
+ uint32_t b;
/* GTH: This isn't exactly correct, but gives good results up to a
* certain point. It is better than completely ignoring the LOD
bias = 127;
}
- b = (u_int32_t)bias & 0xff;
+ b = (uint32_t)bias & 0xff;
t &= ~R128_LOD_BIAS_MASK;
t |= (b << R128_LOD_BIAS_SHIFT);
#define R128PACKCOLOR4444( r, g, b, a ) \
((((a) & 0xf0) << 8) | (((r) & 0xf0) << 4) | ((g) & 0xf0) | ((b) >> 4))
-static __inline__ u_int32_t r128PackColor( GLuint cpp,
+static __inline__ uint32_t r128PackColor( GLuint cpp,
GLubyte r, GLubyte g,
GLubyte b, GLubyte a )
{
int imageWidth, imageHeight;
int remaining, rows;
int format, dwords;
- u_int32_t pitch, offset;
+ uint32_t pitch, offset;
int i;
/* Ensure we have a valid texture to upload */
remaining > 0 ;
remaining -= rows, y += rows, i++ )
{
- u_int32_t *dst;
+ uint32_t *dst;
drmBufPtr buffer;
assert(image->Data);
LOCK_HARDWARE( rmesa );
buffer = r128GetBufferLocked( rmesa );
- dst = (u_int32_t *)((char *)buffer->address + R128_HOSTDATA_BLIT_OFFSET);
+ dst = (uint32_t *)((char *)buffer->address + R128_HOSTDATA_BLIT_OFFSET);
/* Copy the next chunck of the texture image into the blit buffer */
{
struct r128_tex_obj {
driTextureObject base;
- u_int32_t bufAddr; /* Offset to start of locally
+ uint32_t bufAddr; /* Offset to start of locally
shared texture block */
GLuint age;
r128TexImage image[R128_MAX_TEXTURE_LEVELS]; /* Image data for all
mipmap levels */
- u_int32_t textureFormat; /* Actual hardware format */
+ uint32_t textureFormat; /* Actual hardware format */
drm_r128_texture_regs_t setup; /* Setup regs for texture */
};
typedef struct {
/* Common registers */
- u_int32_t ovr_clr;
- u_int32_t ovr_wid_left_right;
- u_int32_t ovr_wid_top_bottom;
- u_int32_t ov0_scale_cntl;
- u_int32_t mpp_tb_config;
- u_int32_t mpp_gp_config;
- u_int32_t subpic_cntl;
- u_int32_t viph_control;
- u_int32_t i2c_cntl_1;
- u_int32_t gen_int_cntl;
- u_int32_t cap0_trig_cntl;
- u_int32_t cap1_trig_cntl;
- u_int32_t bus_cntl;
- u_int32_t config_cntl;
+ uint32_t ovr_clr;
+ uint32_t ovr_wid_left_right;
+ uint32_t ovr_wid_top_bottom;
+ uint32_t ov0_scale_cntl;
+ uint32_t mpp_tb_config;
+ uint32_t mpp_gp_config;
+ uint32_t subpic_cntl;
+ uint32_t viph_control;
+ uint32_t i2c_cntl_1;
+ uint32_t gen_int_cntl;
+ uint32_t cap0_trig_cntl;
+ uint32_t cap1_trig_cntl;
+ uint32_t bus_cntl;
+ uint32_t config_cntl;
/* Other registers to save for VT switches */
- u_int32_t dp_datatype;
- u_int32_t gen_reset_cntl;
- u_int32_t clock_cntl_index;
- u_int32_t amcgpio_en_reg;
- u_int32_t amcgpio_mask;
+ uint32_t dp_datatype;
+ uint32_t gen_reset_cntl;
+ uint32_t clock_cntl_index;
+ uint32_t amcgpio_en_reg;
+ uint32_t amcgpio_mask;
/* CRTC registers */
- u_int32_t crtc_gen_cntl;
- u_int32_t crtc_ext_cntl;
- u_int32_t dac_cntl;
- u_int32_t crtc_h_total_disp;
- u_int32_t crtc_h_sync_strt_wid;
- u_int32_t crtc_v_total_disp;
- u_int32_t crtc_v_sync_strt_wid;
- u_int32_t crtc_offset;
- u_int32_t crtc_offset_cntl;
- u_int32_t crtc_pitch;
+ uint32_t crtc_gen_cntl;
+ uint32_t crtc_ext_cntl;
+ uint32_t dac_cntl;
+ uint32_t crtc_h_total_disp;
+ uint32_t crtc_h_sync_strt_wid;
+ uint32_t crtc_v_total_disp;
+ uint32_t crtc_v_sync_strt_wid;
+ uint32_t crtc_offset;
+ uint32_t crtc_offset_cntl;
+ uint32_t crtc_pitch;
/* CRTC2 registers */
- u_int32_t crtc2_gen_cntl;
+ uint32_t crtc2_gen_cntl;
/* Flat panel registers */
- u_int32_t fp_crtc_h_total_disp;
- u_int32_t fp_crtc_v_total_disp;
- u_int32_t fp_gen_cntl;
- u_int32_t fp_h_sync_strt_wid;
- u_int32_t fp_horz_stretch;
- u_int32_t fp_panel_cntl;
- u_int32_t fp_v_sync_strt_wid;
- u_int32_t fp_vert_stretch;
- u_int32_t lvds_gen_cntl;
- u_int32_t tmds_crc;
- u_int32_t tmds_transmitter_cntl;
+ uint32_t fp_crtc_h_total_disp;
+ uint32_t fp_crtc_v_total_disp;
+ uint32_t fp_gen_cntl;
+ uint32_t fp_h_sync_strt_wid;
+ uint32_t fp_horz_stretch;
+ uint32_t fp_panel_cntl;
+ uint32_t fp_v_sync_strt_wid;
+ uint32_t fp_vert_stretch;
+ uint32_t lvds_gen_cntl;
+ uint32_t tmds_crc;
+ uint32_t tmds_transmitter_cntl;
/* Computed values for PLL */
- u_int32_t dot_clock_freq;
- u_int32_t pll_output_freq;
+ uint32_t dot_clock_freq;
+ uint32_t pll_output_freq;
int feedback_div;
int post_div;
/* PLL registers */
- u_int32_t ppll_ref_div;
- u_int32_t ppll_div_3;
- u_int32_t htotal_cntl;
+ uint32_t ppll_ref_div;
+ uint32_t ppll_div_3;
+ uint32_t htotal_cntl;
/* DDA register */
- u_int32_t dda_config;
- u_int32_t dda_on_off;
+ uint32_t dda_config;
+ uint32_t dda_on_off;
/* Pallet */
GLboolean palette_valid;
- u_int32_t palette[256];
+ uint32_t palette[256];
} R128SaveRec, *R128SavePtr;
typedef struct {
unsigned char *MMIO; /* Map of MMIO region */
unsigned char *FB; /* Map of frame buffer */
- u_int32_t MemCntl;
- u_int32_t BusCntl;
+ uint32_t MemCntl;
+ uint32_t BusCntl;
unsigned long FbMapSize; /* Size of frame buffer, in bytes */
int Flags; /* Saved copy of mode flags */
/* Computed values for Rage 128 */
int pitch;
int datatype;
- u_int32_t dp_gui_master_cntl;
+ uint32_t dp_gui_master_cntl;
/* Saved values for ScreenToScreenCopy */
int xdir;
int log2TexGran;
/* Saved scissor values */
- u_int32_t sc_left;
- u_int32_t sc_right;
- u_int32_t sc_top;
- u_int32_t sc_bottom;
+ uint32_t sc_left;
+ uint32_t sc_right;
+ uint32_t sc_top;
+ uint32_t sc_bottom;
- u_int32_t re_top_left;
- u_int32_t re_width_height;
+ uint32_t re_top_left;
+ uint32_t re_width_height;
- u_int32_t aux_sc_cntl;
+ uint32_t aux_sc_cntl;
int irq;
- u_int32_t gen_int_cntl;
+ uint32_t gen_int_cntl;
GLboolean DMAForXv;
#define R128_VERBOSE 0
-#define RING_LOCALS u_int32_t *__head; int __count;
+#define RING_LOCALS uint32_t *__head; int __count;
#define R128CCE_REFRESH(pScrn, info) \
do { \
fprintf(stderr, \
"ADVANCE_RING() used: %d+%d=%d/%d\n", \
info->indirectBuffer->used - info->indirectStart, \
- __count * sizeof(u_int32_t), \
+ __count * sizeof(uint32_t), \
info->indirectBuffer->used - info->indirectStart + \
- __count * sizeof(u_int32_t), \
+ __count * sizeof(uint32_t), \
info->indirectBuffer->total - info->indirectStart ); \
} \
- info->indirectBuffer->used += __count * (int)sizeof(u_int32_t); \
+ info->indirectBuffer->used += __count * (int)sizeof(uint32_t); \
} while (0)
#define OUT_RING( x ) do { \
{
R128InfoPtr info = ctx->driverPrivate;
unsigned char *R128MMIO = ctx->MMIOAddress;
- u_int32_t chunk;
+ uint32_t chunk;
int ret;
int flags;
* SwapBuffers with client-side throttling
*/
-static u_int32_t r200GetLastFrame(r200ContextPtr rmesa)
+static uint32_t r200GetLastFrame(r200ContextPtr rmesa)
{
drm_radeon_getparam_t gp;
int ret;
- u_int32_t frame;
+ uint32_t frame;
gp.param = RADEON_PARAM_LAST_FRAME;
gp.value = (int *)&frame;
static void r200UpdateSpecular( GLcontext *ctx )
{
r200ContextPtr rmesa = R200_CONTEXT(ctx);
- u_int32_t p = rmesa->hw.ctx.cmd[CTX_PP_CNTL];
+ uint32_t p = rmesa->hw.ctx.cmd[CTX_PP_CNTL];
R200_STATECHANGE( rmesa, tcl );
R200_STATECHANGE( rmesa, vtx );
* SwapBuffers with client-side throttling
*/
-static u_int32_t radeonGetLastFrame (radeonContextPtr rmesa)
+static uint32_t radeonGetLastFrame (radeonContextPtr rmesa)
{
drm_radeon_getparam_t gp;
int ret;
- u_int32_t frame;
+ uint32_t frame;
gp.param = RADEON_PARAM_LAST_FRAME;
gp.value = (int *)&frame;
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
__DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
drm_radeon_sarea_t *sarea = rmesa->sarea;
- u_int32_t clear;
+ uint32_t clear;
GLuint flags = 0;
GLuint color_mask = 0;
GLint ret, i;
GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
};
- u_int8_t depth_bits_array[2];
- u_int8_t stencil_bits_array[2];
+ uint8_t depth_bits_array[2];
+ uint8_t stencil_bits_array[2];
depth_bits_array[0] = depth_bits;
__driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
return NULL;
}
- screen->scratch = (__volatile__ u_int32_t *)
+ screen->scratch = (__volatile__ uint32_t *)
((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
screen->buffers = drmMapBufs( sPriv->fd );
drmBufMapPtr buffers;
- __volatile__ u_int32_t *scratch;
+ __volatile__ uint32_t *scratch;
__DRIscreenPrivate *driScreen;
unsigned int sarea_priv_offset;
static void radeonUpdateSpecular( GLcontext *ctx )
{
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- u_int32_t p = rmesa->hw.ctx.cmd[CTX_PP_CNTL];
+ uint32_t p = rmesa->hw.ctx.cmd[CTX_PP_CNTL];
GLuint flag = 0;
RADEON_STATECHANGE( rmesa, tcl );
GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
};
- u_int8_t depth_bits_array[2];
- u_int8_t stencil_bits_array[2];
+ uint8_t depth_bits_array[2];
+ uint8_t stencil_bits_array[2];
depth_bits_array[0] = depth_bits;
depth_bits_array[1] = depth_bits;
unsigned reserved : 4;
unsigned ofs : 28;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegZPixelOffset;
/* This reg exists only on Savage4. */
unsigned passZpassOp : 3;
unsigned reserved : 3;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegStencilCtrl;
/**************************
unsigned palSize : 2;
unsigned newPal : 1;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegTexDescr_s4;
typedef union
{
unsigned reserved3 : 10;
unsigned newPal : 1;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegTexDescr_s3d;
/* The layout of this reg is the same on Savage4 and Savage3D,
unsigned reserved : 1;
unsigned addr : 29;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegTexAddr;
/* The layout of this reg is the same on Savage4 and Savage3D. */
unsigned reserved : 3;
unsigned addr : 29;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegTexPalAddr;
/* The layout of this reg on Savage4 and Savage3D are very similar. */
unsigned xprClr0 : 16;
unsigned xprClr1 : 16; /* this is reserved on Savage3D */
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegTexXprClr; /* transparency color in RGB565 format*/
/* The layout of this reg differs between Savage4 and Savage3D.
unsigned alphaArg1Invert : 1;
unsigned alphaArg2Invert : 1;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegTexCtrl_s4;
typedef union
{
unsigned texXprEn : 1;
unsigned reserved2 : 11;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegTexCtrl_s3d;
/* This reg exists only on Savage4. */
unsigned colorDoDiffMul : 1;
unsigned LeftShiftVal : 2;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegTexBlendCtrl;
/* This reg exists only on Savage4. */
unsigned red : 8;
unsigned alpha : 8;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegTexBlendColor;
/********************************
unsigned widthInTile : 6;
unsigned bitPerPixel : 1;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegTiledSurface;
/********************************
unsigned scissorYStart : 12;
unsigned alphaRefVal : 8;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegDrawCtrl0;
/* This reg exists only on Savage4. */
unsigned alphaTestCmpFunc : 3;
unsigned alphaTestEn : 1;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegDrawCtrl1;
/* This reg exists only on Savage4. */
unsigned flushPdDestWrites : 1;
unsigned flushPdZbufWrites : 1;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegDrawLocalCtrl;
/* This reg exists only on Savage3D. */
*/
unsigned interpMode : 1;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegDrawCtrl;
#define SAVAGETBC_DECAL_S3D 0
unsigned scissorYStart : 11;
unsigned reserved2 : 5;
} ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegScissorsStart;
/* This reg exists only on Savage3D. */
unsigned scissorYEnd : 11;
unsigned reserved2 : 5;
} ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegScissorsEnd;
/********************************
unsigned reserved : 1;
unsigned addr : 29; /*quad word aligned*/
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegVertBufAddr;
/* I havn't found a Savage3D equivalent of this reg in the Utah-driver.
unsigned reserved : 1;
unsigned addr : 29; /*4-quad word aligned*/
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegDMABufAddr;
/********************************
unsigned reserved : 17;
unsigned kickOff : 1;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegFlag;
/********************************
unsigned floatZEn : 1;
unsigned wToZEn : 1;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegZBufCtrl_s4;
typedef union
{
unsigned wrZafterAlphaTst : 1;
unsigned reserved2 : 15;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegZBufCtrl_s3d;
/* The layout of this reg on Savage4 and Savage3D is very similar. */
*/
unsigned zDepthSelect : 1;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegZBufOffset;
/* The layout of this reg is the same on Savage4 and Savage3D. */
unsigned wHigh : 6;
unsigned reserved4 : 2;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegZWatermarks;
/********************************
unsigned fogMode : 1;
unsigned fogEndShift : 2;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegFogCtrl;
/*not in spec, but tempo for pp and driver*/
unsigned fogDensity : 16;
unsigned fogStart : 16;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegFogParam;
/**************************************
unsigned antiAliasMode : 2;
unsigned dstPixFmt : 1;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegDestCtrl;
/* The layout of this reg on Savage4 and Savage3D are very similar. */
* However, it is not used in either driver. */
unsigned destFlush : 2;
}ni;
- u_int32_t ui;
+ uint32_t ui;
} savageRegDestTexWatermarks;
/* Savage4/Twister/ProSavage register BCI addresses */
#define SAVAGE_FIRST_REG 0x18
#define SAVAGE_NR_REGS 34
typedef struct savage_registers_s4_t {
- u_int32_t unused1[6]; /* 0x18-0x1d */
+ uint32_t unused1[6]; /* 0x18-0x1d */
savageRegDrawLocalCtrl drawLocalCtrl; /* 0x1e */
savageRegTexPalAddr texPalAddr; /* 0x1f */
savageRegTexCtrl_s4 texCtrl[2]; /* 0x20, 0x21 */
savageRegTexBlendCtrl texBlendCtrl[2]; /* 0x24, 0x25 */
savageRegTexXprClr texXprClr; /* 0x26 */
savageRegTexDescr_s4 texDescr; /* 0x27 */
- u_int8_t fogTable[32]; /* 0x28-0x2f (8dwords) */
+ uint8_t fogTable[32]; /* 0x28-0x2f (8dwords) */
savageRegFogCtrl fogCtrl; /* 0x30 */
savageRegStencilCtrl stencilCtrl; /* 0x31 */
savageRegZBufCtrl_s4 zBufCtrl; /* 0x32 */
savageRegTexAddr texAddr; /* 0x1a */
savageRegTexDescr_s3d texDescr; /* 0x1b */
savageRegTexCtrl_s3d texCtrl; /* 0x1c */
- u_int32_t unused1[3]; /* 0x1d-0x1f */
- u_int8_t fogTable[64]; /* 0x20-0x2f (16dwords) */
+ uint32_t unused1[3]; /* 0x1d-0x1f */
+ uint8_t fogTable[64]; /* 0x20-0x2f (16dwords) */
savageRegFogCtrl fogCtrl; /* 0x30 */
savageRegDrawCtrl drawCtrl; /* 0x31 */
savageRegZBufCtrl_s3d zBufCtrl; /* 0x32 */
savageRegScissorsEnd scissorsEnd; /* 0x36 */
savageRegZWatermarks zWatermarks; /* 0x37 */
savageRegDestTexWatermarks destTexWatermarks; /* 0x38 */
- u_int32_t unused2; /* 0x39 */
+ uint32_t unused2; /* 0x39 */
} savageRegistersS3D;
typedef union savage_registers_t {
savageRegistersS4 s4;
savageRegistersS3D s3d;
- u_int32_t ui[SAVAGE_NR_REGS];
+ uint32_t ui[SAVAGE_NR_REGS];
} savageRegisters;
imesa->clientVtxBuf.total = imesa->bufferSize / 4;
imesa->clientVtxBuf.used = 0;
imesa->clientVtxBuf.flushed = 0;
- imesa->clientVtxBuf.buf = (u_int32_t *)malloc(imesa->bufferSize);
+ imesa->clientVtxBuf.buf = (uint32_t *)malloc(imesa->bufferSize);
imesa->vtxBuf = &imesa->clientVtxBuf;
GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
};
- u_int8_t depth_bits_array[2];
- u_int8_t stencil_bits_array[2];
+ uint8_t depth_bits_array[2];
+ uint8_t stencil_bits_array[2];
depth_bits_array[0] = depth_bits;
struct savage_vtxbuf_t {
GLuint total, used, flushed; /* in 32 bit units */
GLuint idx; /* for DMA buffers */
- u_int32_t *buf;
+ uint32_t *buf;
};
struct savage_cmdbuf_t {
imesa->dmaVtxBuf.used = 0;
imesa->dmaVtxBuf.flushed = 0;
imesa->dmaVtxBuf.idx = buf->idx;
- imesa->dmaVtxBuf.buf = (u_int32_t *)buf->address;
+ imesa->dmaVtxBuf.buf = (uint32_t *)buf->address;
if (SAVAGE_DEBUG & DEBUG_DMA)
fprintf(stderr, "finished getbuffer\n");
unsigned int y = pbox->y1;
unsigned int width = pbox->x2 - x;
unsigned int height = pbox->y2 - y;
- u_int32_t *bciptr;
+ uint32_t *bciptr;
if (pbox->x1 > pbox->x2 ||
pbox->y1 > pbox->y2 ||
if ( pclear->flags & SAVAGE_FRONT ) {
bciptr = savageDMAAlloc (imesa, 8);
- WRITE_CMD((bciptr) , 0x4BCC8C00,u_int32_t);
- WRITE_CMD((bciptr) , imesa->savageScreen->frontOffset,u_int32_t);
- WRITE_CMD((bciptr) , imesa->savageScreen->frontBitmapDesc,u_int32_t);
- WRITE_CMD((bciptr) , pclear->clear_color,u_int32_t);
- WRITE_CMD((bciptr) , (y <<16) | x,u_int32_t);
- WRITE_CMD((bciptr) , (height << 16) | width,u_int32_t);
+ WRITE_CMD((bciptr) , 0x4BCC8C00,uint32_t);
+ WRITE_CMD((bciptr) , imesa->savageScreen->frontOffset,uint32_t);
+ WRITE_CMD((bciptr) , imesa->savageScreen->frontBitmapDesc,uint32_t);
+ WRITE_CMD((bciptr) , pclear->clear_color,uint32_t);
+ WRITE_CMD((bciptr) , (y <<16) | x,uint32_t);
+ WRITE_CMD((bciptr) , (height << 16) | width,uint32_t);
savageDMACommit (imesa, bciptr);
}
if ( pclear->flags & SAVAGE_BACK ) {
bciptr = savageDMAAlloc (imesa, 8);
- WRITE_CMD((bciptr) , 0x4BCC8C00,u_int32_t);
- WRITE_CMD((bciptr) , imesa->savageScreen->backOffset,u_int32_t);
- WRITE_CMD((bciptr) , imesa->savageScreen->backBitmapDesc,u_int32_t);
- WRITE_CMD((bciptr) , pclear->clear_color,u_int32_t);
- WRITE_CMD((bciptr) , (y <<16) | x,u_int32_t);
- WRITE_CMD((bciptr) , (height << 16) | width,u_int32_t);
+ WRITE_CMD((bciptr) , 0x4BCC8C00,uint32_t);
+ WRITE_CMD((bciptr) , imesa->savageScreen->backOffset,uint32_t);
+ WRITE_CMD((bciptr) , imesa->savageScreen->backBitmapDesc,uint32_t);
+ WRITE_CMD((bciptr) , pclear->clear_color,uint32_t);
+ WRITE_CMD((bciptr) , (y <<16) | x,uint32_t);
+ WRITE_CMD((bciptr) , (height << 16) | width,uint32_t);
savageDMACommit (imesa, bciptr);
}
if ( pclear->flags & (SAVAGE_DEPTH |SAVAGE_STENCIL) ) {
- u_int32_t writeMask = 0x0;
+ uint32_t writeMask = 0x0;
if(imesa->hw_stencil)
{
if(pclear->flags & SAVAGE_STENCIL)
bciptr = savageDMAAlloc (imesa, 10);
if(writeMask != 0xFFFFFFFF)
{
- WRITE_CMD((bciptr) , 0x960100D7,u_int32_t);
- WRITE_CMD((bciptr) , writeMask,u_int32_t);
+ WRITE_CMD((bciptr) , 0x960100D7,uint32_t);
+ WRITE_CMD((bciptr) , writeMask,uint32_t);
}
}
else
bciptr = savageDMAAlloc (imesa, 6);
}
- WRITE_CMD((bciptr) , 0x4BCC8C00,u_int32_t);
- WRITE_CMD((bciptr) , imesa->savageScreen->depthOffset,u_int32_t);
- WRITE_CMD((bciptr) , imesa->savageScreen->depthBitmapDesc,u_int32_t);
- WRITE_CMD((bciptr) , pclear->clear_depth,u_int32_t);
- WRITE_CMD((bciptr) , (y <<16) | x,u_int32_t);
- WRITE_CMD((bciptr) , (height << 16) | width,u_int32_t);
+ WRITE_CMD((bciptr) , 0x4BCC8C00,uint32_t);
+ WRITE_CMD((bciptr) , imesa->savageScreen->depthOffset,uint32_t);
+ WRITE_CMD((bciptr) , imesa->savageScreen->depthBitmapDesc,uint32_t);
+ WRITE_CMD((bciptr) , pclear->clear_depth,uint32_t);
+ WRITE_CMD((bciptr) , (y <<16) | x,uint32_t);
+ WRITE_CMD((bciptr) , (height << 16) | width,uint32_t);
if(imesa->hw_stencil)
{
if(writeMask != 0xFFFFFFFF)
{
- WRITE_CMD((bciptr) , 0x960100D7,u_int32_t);
- WRITE_CMD((bciptr) , 0xFFFFFFFF,u_int32_t);
+ WRITE_CMD((bciptr) , 0x960100D7,uint32_t);
+ WRITE_CMD((bciptr) , 0xFFFFFFFF,uint32_t);
}
}
savageDMACommit (imesa, bciptr);
int nbox = imesa->sarea->nbox;
drm_clip_rect_t *pbox = imesa->sarea->boxes;
int i;
- volatile u_int32_t *bciptr;
+ volatile uint32_t *bciptr;
if (nbox > SAVAGE_NR_SAREA_CLIPRECTS)
nbox = SAVAGE_NR_SAREA_CLIPRECTS;
}
static __inline
-u_int32_t *savageAllocVtxBuf( savageContextPtr imesa, GLuint words )
+uint32_t *savageAllocVtxBuf( savageContextPtr imesa, GLuint words )
{
struct savage_vtxbuf_t *buffer = imesa->vtxBuf;
- u_int32_t *head;
+ uint32_t *head;
if (buffer == &imesa->dmaVtxBuf) {
if (!buffer->total) {
}
static __inline
-u_int32_t *savageAllocIndexedVerts( savageContextPtr imesa, GLuint n )
+uint32_t *savageAllocIndexedVerts( savageContextPtr imesa, GLuint n )
{
- u_int32_t *ret;
+ uint32_t *ret;
savageFlushVertices(imesa);
ret = savageAllocVtxBuf(imesa, n*imesa->HwVertexSize);
imesa->firstElt = imesa->vtxBuf->flushed / imesa->HwVertexSize;
* - increments the number of elts. Final allocation is done in savageFlushElts
*/
static __inline
-u_int16_t *savageAllocElts( savageContextPtr imesa, GLuint n )
+uint16_t *savageAllocElts( savageContextPtr imesa, GLuint n )
{
- u_int16_t *ret;
+ uint16_t *ret;
GLuint qwords;
assert (savageHaveIndexedVerts(imesa));
imesa->elts.n = 0;
}
- ret = (u_int16_t *)(imesa->elts.cmd+1) + imesa->elts.n;
+ ret = (uint16_t *)(imesa->elts.cmd+1) + imesa->elts.n;
imesa->elts.n += n;
return ret;
}
static void savageBlendFunc_s4(GLcontext *ctx)
{
savageContextPtr imesa = SAVAGE_CONTEXT(ctx);
- u_int32_t drawLocalCtrl = imesa->regs.s4.drawLocalCtrl.ui;
- u_int32_t drawCtrl0 = imesa->regs.s4.drawCtrl0.ui;
- u_int32_t drawCtrl1 = imesa->regs.s4.drawCtrl1.ui;
+ uint32_t drawLocalCtrl = imesa->regs.s4.drawLocalCtrl.ui;
+ uint32_t drawCtrl0 = imesa->regs.s4.drawCtrl0.ui;
+ uint32_t drawCtrl1 = imesa->regs.s4.drawCtrl1.ui;
/* set up draw control register (including blending, alpha
* test, and shading model)
static void savageBlendFunc_s3d(GLcontext *ctx)
{
savageContextPtr imesa = SAVAGE_CONTEXT(ctx);
- u_int32_t drawCtrl = imesa->regs.s3d.drawCtrl.ui;
- u_int32_t zBufCtrl = imesa->regs.s3d.zBufCtrl.ui;
+ uint32_t drawCtrl = imesa->regs.s3d.drawCtrl.ui;
+ uint32_t zBufCtrl = imesa->regs.s3d.zBufCtrl.ui;
/* set up draw control register (including blending, alpha
* test, dithering, and shading model)
{
savageContextPtr imesa = SAVAGE_CONTEXT(ctx);
ZCmpFunc zmode;
- u_int32_t drawLocalCtrl = imesa->regs.s4.drawLocalCtrl.ui;
- u_int32_t zBufCtrl = imesa->regs.s4.zBufCtrl.ui;
- u_int32_t zWatermarks = imesa->regs.s4.zWatermarks.ui; /* FIXME: in DRM */
+ uint32_t drawLocalCtrl = imesa->regs.s4.drawLocalCtrl.ui;
+ uint32_t zBufCtrl = imesa->regs.s4.zBufCtrl.ui;
+ uint32_t zWatermarks = imesa->regs.s4.zWatermarks.ui; /* FIXME: in DRM */
/* set up z-buffer control register (global)
* set up z-buffer offset register (global)
{
savageContextPtr imesa = SAVAGE_CONTEXT(ctx);
ZCmpFunc zmode;
- u_int32_t drawCtrl = imesa->regs.s3d.drawCtrl.ui;
- u_int32_t zBufCtrl = imesa->regs.s3d.zBufCtrl.ui;
- u_int32_t zWatermarks = imesa->regs.s3d.zWatermarks.ui; /* FIXME: in DRM */
+ uint32_t drawCtrl = imesa->regs.s3d.drawCtrl.ui;
+ uint32_t zBufCtrl = imesa->regs.s3d.zBufCtrl.ui;
+ uint32_t zWatermarks = imesa->regs.s3d.zWatermarks.ui; /* FIXME: in DRM */
/* set up z-buffer control register (global)
* set up z-buffer offset register (global)
static void savageDDDrawBuffer(GLcontext *ctx, GLenum mode )
{
savageContextPtr imesa = SAVAGE_CONTEXT(ctx);
- u_int32_t destCtrl = imesa->regs.s4.destCtrl.ui;
+ uint32_t destCtrl = imesa->regs.s4.destCtrl.ui;
/*
* _DrawDestMask is easier to cope with than <mode>.
static void savageUpdateSpecular_s4(GLcontext *ctx) {
savageContextPtr imesa = SAVAGE_CONTEXT( ctx );
- u_int32_t drawLocalCtrl = imesa->regs.s4.drawLocalCtrl.ui;
+ uint32_t drawLocalCtrl = imesa->regs.s4.drawLocalCtrl.ui;
if (NEED_SECONDARY_COLOR(ctx)) {
imesa->regs.s4.drawLocalCtrl.ni.specShadeEn = GL_TRUE;
static void savageUpdateSpecular_s3d(GLcontext *ctx) {
savageContextPtr imesa = SAVAGE_CONTEXT( ctx );
- u_int32_t drawCtrl = imesa->regs.s3d.drawCtrl.ui;
+ uint32_t drawCtrl = imesa->regs.s3d.drawCtrl.ui;
if (NEED_SECONDARY_COLOR(ctx)) {
imesa->regs.s3d.drawCtrl.ni.specShadeEn = GL_TRUE;
static void savageDDShadeModel_s4(GLcontext *ctx, GLuint mod)
{
savageContextPtr imesa = SAVAGE_CONTEXT( ctx );
- u_int32_t drawLocalCtrl = imesa->regs.s4.drawLocalCtrl.ui;
+ uint32_t drawLocalCtrl = imesa->regs.s4.drawLocalCtrl.ui;
if (mod == GL_SMOOTH)
{
static void savageDDShadeModel_s3d(GLcontext *ctx, GLuint mod)
{
savageContextPtr imesa = SAVAGE_CONTEXT( ctx );
- u_int32_t drawCtrl = imesa->regs.s3d.drawCtrl.ui;
+ uint32_t drawCtrl = imesa->regs.s3d.drawCtrl.ui;
if (mod == GL_SMOOTH)
{
{
savageContextPtr imesa = SAVAGE_CONTEXT(ctx);
GLuint fogClr;
- u_int32_t fogCtrl = imesa->regs.s4.fogCtrl.ui;
+ uint32_t fogCtrl = imesa->regs.s4.fogCtrl.ui;
/*if ((ctx->Fog.Enabled) &&(pname == GL_FOG_COLOR))*/
if (ctx->Fog.Enabled)
{
savageContextPtr imesa = SAVAGE_CONTEXT(ctx);
unsigned a=0;
- const u_int32_t zBufCtrl = imesa->regs.s4.zBufCtrl.ui;
- const u_int32_t stencilCtrl = imesa->regs.s4.stencilCtrl.ui;
+ const uint32_t zBufCtrl = imesa->regs.s4.zBufCtrl.ui;
+ const uint32_t stencilCtrl = imesa->regs.s4.stencilCtrl.ui;
imesa->regs.s4.zBufCtrl.ni.stencilRefVal = ctx->Stencil.Ref[0] & 0xff;
imesa->regs.s4.stencilCtrl.ni.readMask = ctx->Stencil.ValueMask[0] & 0xff;
GLenum zfail, GLenum zpass)
{
savageContextPtr imesa = SAVAGE_CONTEXT(ctx);
- const u_int32_t stencilCtrl = imesa->regs.s4.stencilCtrl.ui;
+ const uint32_t stencilCtrl = imesa->regs.s4.stencilCtrl.ui;
imesa->regs.s4.stencilCtrl.ni.failOp = get_stencil_op_value( ctx->Stencil.FailFunc[0] );
imesa->regs.s4.stencilCtrl.ni.passZfailOp = get_stencil_op_value( ctx->Stencil.ZFailFunc[0] );
imesa->globalRegMask.s3d.zBufCtrl.ni.zBufEn = 0x1;
}
void savageDDInitState( savageContextPtr imesa ) {
- memset (imesa->regs.ui, 0, SAVAGE_NR_REGS*sizeof(u_int32_t));
- memset (imesa->globalRegMask.ui, 0xff, SAVAGE_NR_REGS*sizeof(u_int32_t));
+ memset (imesa->regs.ui, 0, SAVAGE_NR_REGS*sizeof(uint32_t));
+ memset (imesa->globalRegMask.ui, 0xff, SAVAGE_NR_REGS*sizeof(uint32_t));
if (imesa->savageScreen->chipset >= S3_SAVAGE4)
savageDDInitState_s4 (imesa);
else
imesa->regs.s4.zBufOffset.ni.zDepthSelect = 1;
}
- memcpy (imesa->oldRegs.ui, imesa->regs.ui, SAVAGE_NR_REGS*sizeof(u_int32_t));
+ memcpy (imesa->oldRegs.ui, imesa->regs.ui, SAVAGE_NR_REGS*sizeof(uint32_t));
/* Emit the initial state to the (empty) command buffer. */
assert (imesa->cmdBuf.write == imesa->cmdBuf.base);
if (imesa->regs.s4.texDescr.ni.tex1En)
imesa->regs.s4.texDescr.ni.texBLoopEn = GL_TRUE;
- imesa->regs.s4.texAddr[0].ui = (u_int32_t) t->setup.physAddr | 0x2;
+ imesa->regs.s4.texAddr[0].ui = (uint32_t) t->setup.physAddr | 0x2;
if(t->base.heap->heapId == SAVAGE_AGP_HEAP)
imesa->regs.s4.texAddr[0].ui |= 0x1;
imesa->regs.s4.texCtrl[1].ni.dMax = t->base.lastLevel - t->base.firstLevel;
imesa->regs.s4.texDescr.ni.texBLoopEn = GL_TRUE;
- imesa->regs.s4.texAddr[1].ui = (u_int32_t) t->setup.physAddr | 2;
+ imesa->regs.s4.texAddr[1].ui = (uint32_t) t->setup.physAddr | 2;
if(t->base.heap->heapId == SAVAGE_AGP_HEAP)
imesa->regs.s4.texAddr[1].ui |= 0x1;
}
assert (t->hwFormat <= 7);
imesa->regs.s3d.texDescr.ni.texFmt = t->hwFormat;
- imesa->regs.s3d.texAddr.ui = (u_int32_t) t->setup.physAddr | 2;
+ imesa->regs.s3d.texAddr.ui = (uint32_t) t->setup.physAddr | 2;
if(t->base.heap->heapId == SAVAGE_AGP_HEAP)
imesa->regs.s3d.texAddr.ui |= 0x1;
}
savageVertexPtr v1,
savageVertexPtr v2) {
GLuint vertsize = imesa->HwVertexSize;
- u_int32_t *vb = savageAllocVtxBuf (imesa, 3*vertsize);
+ uint32_t *vb = savageAllocVtxBuf (imesa, 3*vertsize);
GLuint j;
EMIT_VERT (j, vb, vertsize, 0, v0);
savageVertexPtr v2,
savageVertexPtr v3) {
GLuint vertsize = imesa->HwVertexSize;
- u_int32_t *vb = savageAllocVtxBuf (imesa, 6*vertsize);
+ uint32_t *vb = savageAllocVtxBuf (imesa, 6*vertsize);
GLuint j;
EMIT_VERT (j, vb, vertsize, 0, v0);
static __inline__ void savage_draw_point (savageContextPtr imesa,
savageVertexPtr tmp) {
GLuint vertsize = imesa->HwVertexSize;
- u_int32_t *vb = savageAllocVtxBuf (imesa, 6*vertsize);
+ uint32_t *vb = savageAllocVtxBuf (imesa, 6*vertsize);
const GLfloat x = tmp->v.x;
const GLfloat y = tmp->v.y;
const GLfloat sz = 0.5 * CLAMP(imesa->glCtx->Point.Size,
savageVertexPtr v0,
savageVertexPtr v1 ) {
GLuint vertsize = imesa->HwVertexSize;
- u_int32_t *vb = savageAllocVtxBuf (imesa, 6*vertsize);
+ uint32_t *vb = savageAllocVtxBuf (imesa, 6*vertsize);
const GLfloat width = CLAMP(imesa->glCtx->Line.Width,
imesa->glCtx->Const.MinLineWidth,
imesa->glCtx->Const.MaxLineWidth);
savageVertexPtr v1,
savageVertexPtr v2) {
GLuint vertsize = imesa->HwVertexSize;
- u_int32_t *vb = savageAllocVtxBuf (imesa, 3*vertsize);
+ uint32_t *vb = savageAllocVtxBuf (imesa, 3*vertsize);
savageVertex tmp;
GLuint j;
savageVertexPtr v0,
savageVertexPtr v1 ) {
GLuint vertsize = imesa->HwVertexSize;
- u_int32_t *vb = savageAllocVtxBuf (imesa, 6*vertsize);
+ uint32_t *vb = savageAllocVtxBuf (imesa, 6*vertsize);
const GLfloat width = CLAMP(imesa->glCtx->Line.Width,
imesa->glCtx->Const.MinLineWidth,
imesa->glCtx->Const.MaxLineWidth);
static __inline__ void savage_ptex_point (savageContextPtr imesa,
savageVertexPtr v0) {
GLuint vertsize = imesa->HwVertexSize;
- u_int32_t *vb = savageAllocVtxBuf (imesa, 6*vertsize);
+ uint32_t *vb = savageAllocVtxBuf (imesa, 6*vertsize);
const GLfloat x = v0->v.x;
const GLfloat y = v0->v.y;
const GLfloat sz = 0.5 * CLAMP(imesa->glCtx->Point.Size,
static const GLenum back_buffer_modes[] = {
GLX_NONE, GLX_SWAP_UNDEFINED_OML
};
- u_int8_t depth_bits_array[4];
- u_int8_t stencil_bits_array[4];
+ uint8_t depth_bits_array[4];
+ uint8_t stencil_bits_array[4];
depth_bits_array[0] = 0;
stencil_bits_array[0] = 0;
/* _SOLO : missing macros normally defined by X code */
#define xf86DrvMsg(a, b, ...) fprintf(stderr, __VA_ARGS__)
-#define MMIO_IN8(base, addr) ((*(((volatile u_int8_t*)base)+(addr)))+0)
-#define MMIO_OUT8(base, addr, val) ((*(((volatile u_int8_t*)base)+(addr)))=((u_int8_t)val))
-#define MMIO_OUT16(base, addr, val) ((*(volatile u_int16_t*)(((u_int8_t*)base)+(addr)))=((u_int16_t)val))
+#define MMIO_IN8(base, addr) ((*(((volatile uint8_t*)base)+(addr)))+0)
+#define MMIO_OUT8(base, addr, val) ((*(((volatile uint8_t*)base)+(addr)))=((uint8_t)val))
+#define MMIO_OUT16(base, addr, val) ((*(volatile uint16_t*)(((uint8_t*)base)+(addr)))=((uint16_t)val))
#define VIDEO 0
#define AGP 1
drmInfo.fb_offset = pVia->FrameBufferBase;
drmInfo.mmio_offset = pVia->registerHandle;
if (pVia->IsPCI)
- drmInfo.agpAddr = (u_int32_t)NULL;
+ drmInfo.agpAddr = (uint32_t)NULL;
else
- drmInfo.agpAddr = (u_int32_t)pVia->agpAddr;
+ drmInfo.agpAddr = (uint32_t)pVia->agpAddr;
if ((drmCommandWrite(pVia->drmFD, DRM_VIA_MAP_INIT,&drmInfo,
sizeof(drm_via_init_t))) < 0)
static void VIADisableExtendedFIFO(DRIDriverContext *ctx)
{
VIAPtr pVia = VIAPTR(ctx);
- u_int32_t dwGE230, dwGE298;
+ uint32_t dwGE230, dwGE298;
/* Cause of exit XWindow will dump back register value, others chipset no
* need to set extended fifo value */
static void VIAEnableExtendedFIFO(DRIDriverContext *ctx)
{
VIAPtr pVia = VIAPTR(ctx);
- u_int8_t bRegTemp;
- u_int32_t dwGE230, dwGE298;
+ uint8_t bRegTemp;
+ uint32_t dwGE230, dwGE298;
switch (pVia->Chipset) {
case VIA_CLE266:
SR1C[7:0], SR1D[1:0] (10bits) *=*/
wRegTemp = (pBIOSInfo->offsetWidthByQWord >> 1) + 4;
VGAOUT8(0x3c4, 0x1c);
- VGAOUT8(0x3c5, (u_int8_t)(wRegTemp & 0xFF));
+ VGAOUT8(0x3c5, (uint8_t)(wRegTemp & 0xFF));
VGAOUT8(0x3c4, 0x1d);
bRegTemp = VGAIN8(0x3c5) & ~0x03;
VGAOUT8(0x3c5, bRegTemp | ((wRegTemp & 0x300) >> 8));
SR1C[7:0], SR1D[1:0] (10bits) *=*/
wRegTemp = (pBIOSInfo->offsetWidthByQWord >> 1) + 4;
VGAOUT8(0x3c4, 0x1c);
- VGAOUT8(0x3c5, (u_int8_t)(wRegTemp & 0xFF));
+ VGAOUT8(0x3c5, (uint8_t)(wRegTemp & 0xFF));
VGAOUT8(0x3c4, 0x1d);
bRegTemp = VGAIN8(0x3c5) & ~0x03;
VGAOUT8(0x3c5, bRegTemp | ((wRegTemp & 0x300) >> 8));
static void VIAInitialize2DEngine(DRIDriverContext *ctx)
{
VIAPtr pVia = VIAPTR(ctx);
- u_int32_t dwVQStartAddr, dwVQEndAddr;
- u_int32_t dwVQLen, dwVQStartL, dwVQEndL, dwVQStartEndH;
- u_int32_t dwGEMode;
+ uint32_t dwVQStartAddr, dwVQEndAddr;
+ uint32_t dwVQLen, dwVQStartL, dwVQEndL, dwVQStartEndH;
+ uint32_t dwGEMode;
/* init 2D engine regs to reset 2D engine */
VIASETREG(0x04, 0x0);
for (i = 0; i <= 0x7D; i++)
{
- VIASETREG(0x440, (u_int32_t) i << 24);
+ VIASETREG(0x440, (uint32_t) i << 24);
}
VIASETREG(0x43C, 0x00020000);
for (i = 0; i <= 0x94; i++)
{
- VIASETREG(0x440, (u_int32_t) i << 24);
+ VIASETREG(0x440, (uint32_t) i << 24);
}
VIASETREG(0x440, 0x82400000);
for (i = 0; i <= 0x94; i++)
{
- VIASETREG(0x440, (u_int32_t) i << 24);
+ VIASETREG(0x440, (uint32_t) i << 24);
}
VIASETREG(0x440, 0x82400000);
for (i = 0; i <= 0x03; i++)
{
- VIASETREG(0x440, (u_int32_t) i << 24);
+ VIASETREG(0x440, (uint32_t) i << 24);
}
VIASETREG(0x43C, 0x00030000);
XAAInfoRecPtr AccelInfoRec;
xRectangle Rect;
#endif
- u_int32_t SavedCmd;
- u_int32_t SavedFgColor;
- u_int32_t SavedBgColor;
- u_int32_t SavedPattern0;
- u_int32_t SavedPattern1;
- u_int32_t SavedPatternAddr;
+ uint32_t SavedCmd;
+ uint32_t SavedFgColor;
+ uint32_t SavedBgColor;
+ uint32_t SavedPattern0;
+ uint32_t SavedPattern1;
+ uint32_t SavedPatternAddr;
#if 0
/* Support for Int10 processing */
#endif
/*
- u_int32_t Cap0_Deinterlace;
- u_int32_t Cap1_Deinterlace;
+ uint32_t Cap0_Deinterlace;
+ uint32_t Cap1_Deinterlace;
int Cap0_FieldSwap;
int NoCap0_HFilter;
VIAConfigPrivPtr pVisualConfigsPriv;
unsigned long agpHandle;
unsigned long registerHandle;
- u_int32_t agpAddr;
+ uint32_t agpAddr;
unsigned char *agpBase;
unsigned int agpSize;
int IsPCI;
#endif
int V4LEnabled;
- u_int16_t ActiveDevice; /* if SAMM, non-equal pBIOSInfo->ActiveDevice */
+ uint16_t ActiveDevice; /* if SAMM, non-equal pBIOSInfo->ActiveDevice */
unsigned char *CursorImage;
- u_int32_t CursorFG;
- u_int32_t CursorBG;
- u_int32_t CursorMC;
+ uint32_t CursorFG;
+ uint32_t CursorBG;
+ uint32_t CursorMC;
unsigned char MemClk;
int EnableExtendedFIFO;
/* The 32-bit depth-buffer mode isn't supported yet, so don't actually
* enable it.
*/
- static const u_int8_t depth_bits_array[4] = { 0, 16, 24, 32 };
- static const u_int8_t stencil_bits_array[4] = { 0, 0, 8, 0 };
+ static const uint8_t depth_bits_array[4] = { 0, 16, 24, 32 };
+ static const uint8_t stencil_bits_array[4] = { 0, 0, 8, 0 };
const unsigned depth_buffer_factor = 3;
/**
* Convert S and T texture coordinate wrap modes to hardware bits.
*/
-static u_int32_t
+static uint32_t
get_wrap_mode( GLenum sWrap, GLenum tWrap )
{
- u_int32_t v = 0;
+ uint32_t v = 0;
switch( sWrap ) {
return v;
}
-static u_int32_t
+static uint32_t
get_minmag_filter( GLenum min, GLenum mag )
{
- u_int32_t v = 0;
+ uint32_t v = 0;
switch (min) {
case GL_NEAREST:
projects / mesa.git / commitdiff