Add XC7_WIRE_DELAY macro to synth_xilinx.cc

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 2308ddadd7e632737d35d5ab21562eb733141bad..a1164887393f0614bfb93ec10710797f93e2005b 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -25,6 +25,8 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+#define XC7_WIRE_DELAY "160"
+
 struct SynthXilinxPass : public ScriptPass
 {
        SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
@@ -279,7 +281,7 @@ struct SynthXilinxPass : public ScriptPass
 
                if (check_label("map_luts")) {
                        if (abc == "abc9")
-                               run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W 160" + string(retime ? " -dff" : ""));
+                               run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -dff" : ""));
                        else if (help_mode)
                                run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
                        else