verilog: ignore '&&&' when not in -specify mode

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 9b43c250efaf06e03a4f1df93dafcf535d125b43..18fa2966b3be926242cf33b713fc301f2a384f14 100644 (file)
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -440,7 +440,7 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
 }
 
 "&&&" {
-       if (!specify_mode) REJECT;
+       if (!specify_mode) return TOK_IGNORED_SPECIFY_AND;
        return TOK_SPECIFY_AND;
 }
 

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 9b1b07f86ca65338332ddeb80b153be39c957337..f37c6d99b9d3068fce97d2e75e29cba68c938f8b 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -146,7 +146,7 @@ struct specify_rise_fall {
 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY
-%token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND
+%token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND TOK_IGNORED_SPECIFY_AND
 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
@@ -1117,6 +1117,7 @@ system_timing_arg :
 
 system_timing_args :
        system_timing_arg |
+       system_timing_args TOK_IGNORED_SPECIFY_AND system_timing_arg |
        system_timing_args ',' system_timing_arg ;
 
 path_delay_expression :
@@ -1137,9 +1138,9 @@ ignspec_constant_expression:
 ignspec_expr:
        expr { delete $1; } |
        expr ':' expr ':' expr {
-                delete $1;
-                delete $3;
-                delete $5;
+               delete $1;
+               delete $3;
+               delete $5;
        };
 
 ignspec_id:

diff --git a/tests/various/specify.v b/tests/various/specify.v
index 5006e4c381d556db86b329d2fe7a1a93661cdf75..aa8aca4bcd80c3d2fc271f7273587266e129ec18 100644 (file)
--- a/tests/various/specify.v
+++ b/tests/various/specify.v
@@ -51,3 +51,9 @@ specify
   $setuphold(d, posedge clk, 1:2:3, 4:5:6);
 endspecify
 endmodule
+
+module test5(input clk, d, e, output q);
+specify
+  $setup(d, posedge clk &&& e, 1:2:3);
+endspecify
+endmodule