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diff --git a/simple_v_extension/sv_prefix_proposal.rst b/simple_v_extension/sv_prefix_proposal.rst
index b6ac3affc3124f35758be9c9fcdfba4e2651143c..7a8d0950a7becef6c857272d0fa0d35baab4f0f1 100644 (file)
--- a/simple_v_extension/sv_prefix_proposal.rst
+++ b/simple_v_extension/sv_prefix_proposal.rst
@@ -15,13 +15,19 @@ Conventions
 ===========
 
 Conventions used in this document:
-- Bits are numbered starting from 0 at the LSB, so bit 3 is 1 in the integer 8.
-- Bit ranges are inclusive on both ends, so 5:3 means bits 5, 4, and 3.
 
-Operations work on variable-length vectors of sub-vectors, where each sub-vector
-has a length *svlen*, and an element type *etype*. When the vectors are stored
+* Bits are numbered starting from 0 at the LSB, so bit 3 is 1 in the integer 8.
+* Bit ranges are inclusive on both ends, so 5:3 means bits 5, 4, and 3.
+* Operations work on variable-length vectors of sub-vectors up to *VL* in length,
+where each sub-vector
+has a length *svlen*, and *svlen* elements of type *etype*.
+* The actual total number of elements is therefore *svlen* times *VL*.
+* When the vectors are stored
 in registers, all elements are packed so that there is no padding in-between
-elements of the same vector. The number of bytes in a sub-vector, *svsz*, is the
+elements of the same vector.
+* The register file itself is thus best viewed as a byte-level
+SRAM that is typecast to an array of *etype*s
+* The number of bytes in a sub-vector, *svsz*, is the
 product of *svlen* and the element size in bytes.
 
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