}
}
+void r300_emit_dsa_state(struct r300_context* r300,
+ struct r300_dsa_state* dsa)
+{
+ struct r300_screen* r300screen =
+ (struct r300_screen*)r300->context.screen;
+ CS_LOCALS(r300);
+ BEGIN_CS(r300screen->caps->is_r500 ? 12 : 10);
+ OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
+ OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
+ OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
+ OUT_CS(dsa->z_buffer_control);
+ OUT_CS(dsa->z_stencil_control);
+ OUT_CS(dsa->stencil_ref_mask);
+ OUT_CS_REG(R300_ZB_ZTOP, dsa->z_buffer_top);
+ if (r300screen->caps->is_r500) {
+ OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
+ }
+}
+
static void r300_emit_dirty_state(struct r300_context* r300)
{
struct r300_screen* r300screen =
}
if (r300->dirty_state & R300_NEW_DSA) {
- struct r300_dsa_state* dsa = r300->dsa_state;
- OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
- OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
- /* XXX next three are contiguous regs */
- OUT_CS_REG(R300_ZB_CNTL, dsa->z_buffer_control);
- OUT_CS_REG(R300_ZB_ZSTENCILCNTL, dsa->z_stencil_control);
- OUT_CS_REG(R300_ZB_STENCILREFMASK, dsa->stencil_ref_mask);
- OUT_CS_REG(R300_ZB_ZTOP, dsa->z_buffer_top);
- if (r300screen->caps->is_r500) {
- OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
- }
+ r300_emit_dsa_state(r300, r300->dsa_state);
}
if (r300->dirty_state & R300_NEW_RASTERIZER) {
void r300_emit_blend_color_state(struct r300_context* r300,
struct r300_blend_color_state* bc);
+
+void r300_emit_dsa_state(struct r300_context* r300,
+ struct r300_dsa_state* dsa);
OUT_CS_REG(0x4BC8, 0x00000000);
OUT_CS_REG(0x4BCC, 0x00000000);
OUT_CS_REG(0x4BD0, 0x00000000);
-OUT_CS_REG(0x4BD4, 0x00000000);
OUT_CS_REG(0x4BD8, 0x00000000);
OUT_CS_REG(0x4BD8, 0x00000000);
OUT_CS_REG(0x4E00, 0x00000000);
OUT_CS_REG(0x4F04, 0x00038038);
OUT_CS_REG(0x4F08, 0x00FFFF00);
OUT_CS_REG(0x4F10, 0x00000002);
-OUT_CS_REG(0x4F14, 0x00000001);
OUT_CS_REG(0x4F18, 0x00000003);
OUT_CS_REG(0x4F1C, 0x00000000);
OUT_CS_REG(0x4F28, 0x00000000);
OUT_CS_REG(0x2208, 0x00D10021);
OUT_CS_REG(0x2208, 0x01248021);
OUT_CS_REG(0x2208, 0x00000000);
+
+r300_emit_dsa_state(r300, &dsa_clear_state);
+
R300_PACIFY;
OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1);
OUT_CS_RELOC(dest->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
//OUT_CS_REG(0x4E38, 0x00C00100);
OUT_CS_REG(0x4E0C, 0x0000000F);
-OUT_CS_REG(0x4F00, 0x00000000);
-OUT_CS_REG(0x4F04, 0x00000000);
-OUT_CS_REG(0x4F08, 0x00FF0000);
-
/* XXX Packet3 */
OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
OUT_CS(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
.blend_color_green_blue = 0x0,
};
+const struct r300_dsa_state dsa_clear_state = {
+ .alpha_function = 0x0,
+ .alpha_reference = 0x0,
+ .z_buffer_control = 0x0,
+ .z_stencil_control = 0x0,
+ .stencil_ref_mask = 0x0,
+ .z_buffer_top = R300_ZTOP_ENABLE,
+ .stencil_ref_bf = 0x0,
+};
+
#endif /* R300_SURFACE_H */