* m32r-asm.c,m32r-opc.c: Regenerate (-Wall cleanups).

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index efa615ecbc6d2d54f279ccd50b2e42e936a9d1e3..4a1feb7f667c129f2b84c2551fd465447fb09a0d 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+Fri Jul 24 11:41:37 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+       * m32r-asm.c,m32r-opc.c: Regenerate (-Wall cleanups).
+
 start-sanitize-am33
 Thu Jul 23 09:21:03 1998  Jeffrey A Law  (law@cygnus.com)
 

diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c
index 27dec03344c395903eddb39ea93eaaf49d7876a1..a1a1f65cde2ac731301abffd74e71a134f599410 100644 (file)
--- a/opcodes/m32r-opc.c
+++ b/opcodes/m32r-opc.c
@@ -995,7 +995,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_ADD, "add", "add",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0xa0,
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
@@ -1004,7 +1004,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_ADD3, "add3", "add3",
-    { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
     { 32, 32, 0xf0f00000 }, 0x80a00000,
     (PTR) & fmt_add3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1013,7 +1013,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_AND, "and", "and",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0xc0,
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
@@ -1022,7 +1022,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_AND3, "and3", "and3",
-    { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
     { 32, 32, 0xf0f00000 }, 0x80c00000,
     (PTR) & fmt_and3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1031,7 +1031,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_OR, "or", "or",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0xe0,
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
@@ -1040,7 +1040,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_OR3, "or3", "or3",
-    { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
     { 32, 32, 0xf0f00000 }, 0x80e00000,
     (PTR) & fmt_or3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1049,7 +1049,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_XOR, "xor", "xor",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0xd0,
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
@@ -1058,7 +1058,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_XOR3, "xor3", "xor3",
-    { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
     { 32, 32, 0xf0f00000 }, 0x80d00000,
     (PTR) & fmt_and3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1067,7 +1067,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_ADDI, "addi", "addi",
-    { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
     { 16, 16, 0xf000 }, 0x4000,
     (PTR) & fmt_addi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
@@ -1076,7 +1076,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_ADDV, "addv", "addv",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x80,
     (PTR) & fmt_addv_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
@@ -1085,7 +1085,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_ADDV3, "addv3", "addv3",
-    { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
     { 32, 32, 0xf0f00000 }, 0x80800000,
     (PTR) & fmt_addv3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1094,7 +1094,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_ADDX, "addx", "addx",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x90,
     (PTR) & fmt_addx_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
@@ -1103,7 +1103,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_BC8, "bc8", "bc.s",
-    { MNEM, ' ', OP (DISP8), 0 },
+    { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7c00,
     (PTR) & fmt_bc8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
@@ -1112,7 +1112,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_BC24, "bc24", "bc.l",
-    { MNEM, ' ', OP (DISP24), 0 },
+    { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xfc000000,
     (PTR) & fmt_bc24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
@@ -1121,7 +1121,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_BEQ, "beq", "beq",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
     { 32, 32, 0xf0f00000 }, 0xb0000000,
     (PTR) & fmt_beq_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
@@ -1130,7 +1130,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_BEQZ, "beqz", "beqz",
-    { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
+    { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
     { 32, 32, 0xfff00000 }, 0xb0800000,
     (PTR) & fmt_beqz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
@@ -1139,7 +1139,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_BGEZ, "bgez", "bgez",
-    { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
+    { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
     { 32, 32, 0xfff00000 }, 0xb0b00000,
     (PTR) & fmt_beqz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
@@ -1148,7 +1148,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_BGTZ, "bgtz", "bgtz",
-    { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
+    { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
     { 32, 32, 0xfff00000 }, 0xb0d00000,
     (PTR) & fmt_beqz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
@@ -1157,7 +1157,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_BLEZ, "blez", "blez",
-    { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
+    { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
     { 32, 32, 0xfff00000 }, 0xb0c00000,
     (PTR) & fmt_beqz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
@@ -1166,7 +1166,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_BLTZ, "bltz", "bltz",
-    { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
+    { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
     { 32, 32, 0xfff00000 }, 0xb0a00000,
     (PTR) & fmt_beqz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
@@ -1175,7 +1175,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_BNEZ, "bnez", "bnez",
-    { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
+    { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
     { 32, 32, 0xfff00000 }, 0xb0900000,
     (PTR) & fmt_beqz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
@@ -1184,7 +1184,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_BL8, "bl8", "bl.s",
-    { MNEM, ' ', OP (DISP8), 0 },
+    { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7e00,
     (PTR) & fmt_bl8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
@@ -1193,7 +1193,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_BL24, "bl24", "bl.l",
-    { MNEM, ' ', OP (DISP24), 0 },
+    { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xfe000000,
     (PTR) & fmt_bl24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
@@ -1203,7 +1203,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_BCL8, "bcl8", "bcl.s",
-    { MNEM, ' ', OP (DISP8), 0 },
+    { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7800,
     (PTR) & fmt_bcl8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
@@ -1214,7 +1214,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_BCL24, "bcl24", "bcl.l",
-    { MNEM, ' ', OP (DISP24), 0 },
+    { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xf8000000,
     (PTR) & fmt_bcl24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
@@ -1224,7 +1224,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_BNC8, "bnc8", "bnc.s",
-    { MNEM, ' ', OP (DISP8), 0 },
+    { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7d00,
     (PTR) & fmt_bc8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
@@ -1233,7 +1233,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_BNC24, "bnc24", "bnc.l",
-    { MNEM, ' ', OP (DISP24), 0 },
+    { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xfd000000,
     (PTR) & fmt_bc24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
@@ -1242,7 +1242,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_BNE, "bne", "bne",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
     { 32, 32, 0xf0f00000 }, 0xb0100000,
     (PTR) & fmt_beq_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
@@ -1251,7 +1251,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_BRA8, "bra8", "bra.s",
-    { MNEM, ' ', OP (DISP8), 0 },
+    { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7f00,
     (PTR) & fmt_bra8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
@@ -1260,7 +1260,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_BRA24, "bra24", "bra.l",
-    { MNEM, ' ', OP (DISP24), 0 },
+    { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xff000000,
     (PTR) & fmt_bra24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
@@ -1270,7 +1270,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_BNCL8, "bncl8", "bncl.s",
-    { MNEM, ' ', OP (DISP8), 0 },
+    { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7900,
     (PTR) & fmt_bcl8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
@@ -1281,7 +1281,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_BNCL24, "bncl24", "bncl.l",
-    { MNEM, ' ', OP (DISP24), 0 },
+    { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xf9000000,
     (PTR) & fmt_bcl24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
@@ -1291,7 +1291,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_CMP, "cmp", "cmp",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x40,
     (PTR) & fmt_cmp_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
@@ -1300,7 +1300,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_CMPI, "cmpi", "cmpi",
-    { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 },
+    { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
     { 32, 32, 0xfff00000 }, 0x80400000,
     (PTR) & fmt_cmpi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1309,7 +1309,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_CMPU, "cmpu", "cmpu",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x50,
     (PTR) & fmt_cmp_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
@@ -1318,7 +1318,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_CMPUI, "cmpui", "cmpui",
-    { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 },
+    { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
     { 32, 32, 0xfff00000 }, 0x80500000,
     (PTR) & fmt_cmpi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1328,7 +1328,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_CMPEQ, "cmpeq", "cmpeq",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x60,
     (PTR) & fmt_cmp_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
@@ -1339,7 +1339,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_CMPZ, "cmpz", "cmpz",
-    { MNEM, ' ', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC2), 0 } },
     { 16, 16, 0xfff0 }, 0x70,
     (PTR) & fmt_cmpz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
@@ -1349,7 +1349,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_DIV, "div", "div",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 32, 32, 0xf0f0ffff }, 0x90000000,
     (PTR) & fmt_div_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1358,7 +1358,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_DIVU, "divu", "divu",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 32, 32, 0xf0f0ffff }, 0x90100000,
     (PTR) & fmt_div_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1367,7 +1367,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_REM, "rem", "rem",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 32, 32, 0xf0f0ffff }, 0x90200000,
     (PTR) & fmt_div_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1376,7 +1376,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_REMU, "remu", "remu",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 32, 32, 0xf0f0ffff }, 0x90300000,
     (PTR) & fmt_div_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1386,7 +1386,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_DIVH, "divh", "divh",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 32, 32, 0xf0f0ffff }, 0x90000010,
     (PTR) & fmt_div_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
@@ -1397,7 +1397,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_JC, "jc", "jc",
-    { MNEM, ' ', OP (SR), 0 },
+    { { MNEM, ' ', OP (SR), 0 } },
     { 16, 16, 0xfff0 }, 0x1cc0,
     (PTR) & fmt_jc_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
@@ -1408,7 +1408,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_JNC, "jnc", "jnc",
-    { MNEM, ' ', OP (SR), 0 },
+    { { MNEM, ' ', OP (SR), 0 } },
     { 16, 16, 0xfff0 }, 0x1dc0,
     (PTR) & fmt_jc_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
@@ -1418,7 +1418,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_JL, "jl", "jl",
-    { MNEM, ' ', OP (SR), 0 },
+    { { MNEM, ' ', OP (SR), 0 } },
     { 16, 16, 0xfff0 }, 0x1ec0,
     (PTR) & fmt_jl_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
@@ -1427,7 +1427,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_JMP, "jmp", "jmp",
-    { MNEM, ' ', OP (SR), 0 },
+    { { MNEM, ' ', OP (SR), 0 } },
     { 16, 16, 0xfff0 }, 0x1fc0,
     (PTR) & fmt_jmp_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
@@ -1436,7 +1436,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_LD, "ld", "ld",
-    { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x20c0,
     (PTR) & fmt_ld_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -1445,7 +1445,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_LD_D, "ld-d", "ld",
-    { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0c00000,
     (PTR) & fmt_ld_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1454,7 +1454,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_LDB, "ldb", "ldb",
-    { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x2080,
     (PTR) & fmt_ldb_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -1463,7 +1463,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_LDB_D, "ldb-d", "ldb",
-    { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0800000,
     (PTR) & fmt_ldb_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1472,7 +1472,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_LDH, "ldh", "ldh",
-    { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x20a0,
     (PTR) & fmt_ldh_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -1481,7 +1481,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_LDH_D, "ldh-d", "ldh",
-    { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0a00000,
     (PTR) & fmt_ldh_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1490,7 +1490,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_LDUB, "ldub", "ldub",
-    { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x2090,
     (PTR) & fmt_ldb_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -1499,7 +1499,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_LDUB_D, "ldub-d", "ldub",
-    { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0900000,
     (PTR) & fmt_ldb_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1508,7 +1508,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_LDUH, "lduh", "lduh",
-    { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x20b0,
     (PTR) & fmt_ldh_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -1517,7 +1517,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_LDUH_D, "lduh-d", "lduh",
-    { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0b00000,
     (PTR) & fmt_ldh_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1526,7 +1526,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_LD_PLUS, "ld-plus", "ld",
-    { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } },
     { 16, 16, 0xf0f0 }, 0x20e0,
     (PTR) & fmt_ld_plus_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -1535,7 +1535,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_LD24, "ld24", "ld24",
-    { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } },
     { 32, 32, 0xf0000000 }, 0xe0000000,
     (PTR) & fmt_ld24_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1544,7 +1544,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_LDI8, "ldi8", "ldi8",
-    { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
     { 16, 16, 0xf000 }, 0x6000,
     (PTR) & fmt_ldi8_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
@@ -1553,7 +1553,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_LDI16, "ldi16", "ldi16",
-    { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
     { 32, 32, 0xf0ff0000 }, 0x90f00000,
     (PTR) & fmt_ldi16_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1562,7 +1562,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_LOCK, "lock", "lock",
-    { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x20d0,
     (PTR) & fmt_lock_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -1571,7 +1571,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MACHI, "machi", "machi",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x3040,
     (PTR) & fmt_machi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
@@ -1581,7 +1581,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MACHI_A, "machi-a", "machi",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
     { 16, 16, 0xf070 }, 0x3040,
     (PTR) & fmt_machi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
@@ -1591,7 +1591,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MACLO, "maclo", "maclo",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x3050,
     (PTR) & fmt_machi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
@@ -1601,7 +1601,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MACLO_A, "maclo-a", "maclo",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
     { 16, 16, 0xf070 }, 0x3050,
     (PTR) & fmt_machi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
@@ -1611,7 +1611,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MACWHI, "macwhi", "macwhi",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x3060,
     (PTR) & fmt_machi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
@@ -1620,7 +1620,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MACWLO, "macwlo", "macwlo",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x3070,
     (PTR) & fmt_machi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
@@ -1629,7 +1629,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MUL, "mul", "mul",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x1060,
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
@@ -1638,7 +1638,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MULHI, "mulhi", "mulhi",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x3000,
     (PTR) & fmt_mulhi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
@@ -1648,7 +1648,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MULHI_A, "mulhi-a", "mulhi",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
     { 16, 16, 0xf070 }, 0x3000,
     (PTR) & fmt_mulhi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
@@ -1658,7 +1658,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MULLO, "mullo", "mullo",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x3010,
     (PTR) & fmt_mulhi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
@@ -1668,7 +1668,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MULLO_A, "mullo-a", "mullo",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
     { 16, 16, 0xf070 }, 0x3010,
     (PTR) & fmt_mulhi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
@@ -1678,7 +1678,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MULWHI, "mulwhi", "mulwhi",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x3020,
     (PTR) & fmt_mulhi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
@@ -1687,7 +1687,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MULWLO, "mulwlo", "mulwlo",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x3030,
     (PTR) & fmt_mulhi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
@@ -1696,7 +1696,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MV, "mv", "mv",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x1080,
     (PTR) & fmt_mv_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
@@ -1705,7 +1705,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MVFACHI, "mvfachi", "mvfachi",
-    { MNEM, ' ', OP (DR), 0 },
+    { { MNEM, ' ', OP (DR), 0 } },
     { 16, 16, 0xf0ff }, 0x50f0,
     (PTR) & fmt_mvfachi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
@@ -1715,7 +1715,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi",
-    { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
     { 16, 16, 0xf0f3 }, 0x50f0,
     (PTR) & fmt_mvfachi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
@@ -1725,7 +1725,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo",
-    { MNEM, ' ', OP (DR), 0 },
+    { { MNEM, ' ', OP (DR), 0 } },
     { 16, 16, 0xf0ff }, 0x50f1,
     (PTR) & fmt_mvfachi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
@@ -1735,7 +1735,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo",
-    { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
     { 16, 16, 0xf0f3 }, 0x50f1,
     (PTR) & fmt_mvfachi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
@@ -1745,7 +1745,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi",
-    { MNEM, ' ', OP (DR), 0 },
+    { { MNEM, ' ', OP (DR), 0 } },
     { 16, 16, 0xf0ff }, 0x50f2,
     (PTR) & fmt_mvfachi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
@@ -1755,7 +1755,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi",
-    { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
     { 16, 16, 0xf0f3 }, 0x50f2,
     (PTR) & fmt_mvfachi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
@@ -1765,7 +1765,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MVFC, "mvfc", "mvfc",
-    { MNEM, ' ', OP (DR), ',', OP (SCR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
     { 16, 16, 0xf0f0 }, 0x1090,
     (PTR) & fmt_mvfc_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -1774,7 +1774,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MVTACHI, "mvtachi", "mvtachi",
-    { MNEM, ' ', OP (SRC1), 0 },
+    { { MNEM, ' ', OP (SRC1), 0 } },
     { 16, 16, 0xf0ff }, 0x5070,
     (PTR) & fmt_mvtachi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
@@ -1784,7 +1784,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi",
-    { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
     { 16, 16, 0xf0f3 }, 0x5070,
     (PTR) & fmt_mvtachi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
@@ -1794,7 +1794,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo",
-    { MNEM, ' ', OP (SRC1), 0 },
+    { { MNEM, ' ', OP (SRC1), 0 } },
     { 16, 16, 0xf0ff }, 0x5071,
     (PTR) & fmt_mvtachi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
@@ -1804,7 +1804,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo",
-    { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
     { 16, 16, 0xf0f3 }, 0x5071,
     (PTR) & fmt_mvtachi_a_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
@@ -1814,7 +1814,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MVTC, "mvtc", "mvtc",
-    { MNEM, ' ', OP (SR), ',', OP (DCR), 0 },
+    { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
     { 16, 16, 0xf0f0 }, 0x10a0,
     (PTR) & fmt_mvtc_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -1823,7 +1823,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_NEG, "neg", "neg",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x30,
     (PTR) & fmt_mv_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
@@ -1832,7 +1832,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_NOP, "nop", "nop",
-    { MNEM, 0 },
+    { { MNEM, 0 } },
     { 16, 16, 0xffff }, 0x7000,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
@@ -1841,7 +1841,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_NOT, "not", "not",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0xb0,
     (PTR) & fmt_mv_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
@@ -1850,7 +1850,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_RAC, "rac", "rac",
-    { MNEM, 0 },
+    { { MNEM, 0 } },
     { 16, 16, 0xffff }, 0x5090,
     (PTR) & fmt_rac_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
@@ -1860,7 +1860,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_RAC_DSI, "rac-dsi", "rac",
-    { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 },
+    { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
     { 16, 16, 0xf3f2 }, 0x5090,
     (PTR) & fmt_rac_dsi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
@@ -1870,7 +1870,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_RACH, "rach", "rach",
-    { MNEM, 0 },
+    { { MNEM, 0 } },
     { 16, 16, 0xffff }, 0x5080,
     (PTR) & fmt_rac_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
@@ -1880,7 +1880,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_RACH_DSI, "rach-dsi", "rach",
-    { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 },
+    { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
     { 16, 16, 0xf3f2 }, 0x5080,
     (PTR) & fmt_rac_dsi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
@@ -1890,7 +1890,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_RTE, "rte", "rte",
-    { MNEM, 0 },
+    { { MNEM, 0 } },
     { 16, 16, 0xffff }, 0x10d6,
     (PTR) & fmt_rte_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
@@ -1899,7 +1899,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_SETH, "seth", "seth",
-    { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
     { 32, 32, 0xf0ff0000 }, 0xd0c00000,
     (PTR) & fmt_seth_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1908,7 +1908,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_SLL, "sll", "sll",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x1040,
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -1917,7 +1917,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_SLL3, "sll3", "sll3",
-    { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
     { 32, 32, 0xf0f00000 }, 0x90c00000,
     (PTR) & fmt_sll3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1926,7 +1926,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_SLLI, "slli", "slli",
-    { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
     { 16, 16, 0xf0e0 }, 0x5040,
     (PTR) & fmt_slli_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -1935,7 +1935,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_SRA, "sra", "sra",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x1020,
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -1944,7 +1944,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_SRA3, "sra3", "sra3",
-    { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
     { 32, 32, 0xf0f00000 }, 0x90a00000,
     (PTR) & fmt_sll3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1953,7 +1953,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_SRAI, "srai", "srai",
-    { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
     { 16, 16, 0xf0e0 }, 0x5020,
     (PTR) & fmt_slli_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -1962,7 +1962,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_SRL, "srl", "srl",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x1000,
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -1971,7 +1971,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_SRL3, "srl3", "srl3",
-    { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
     { 32, 32, 0xf0f00000 }, 0x90800000,
     (PTR) & fmt_sll3_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -1980,7 +1980,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_SRLI, "srli", "srli",
-    { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
     { 16, 16, 0xf0e0 }, 0x5000,
     (PTR) & fmt_slli_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -1989,7 +1989,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_ST, "st", "st",
-    { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x2040,
     (PTR) & fmt_st_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -1998,7 +1998,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_ST_D, "st-d", "st",
-    { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
+    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0400000,
     (PTR) & fmt_st_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -2007,7 +2007,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_STB, "stb", "stb",
-    { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x2000,
     (PTR) & fmt_stb_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -2016,7 +2016,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_STB_D, "stb-d", "stb",
-    { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
+    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0000000,
     (PTR) & fmt_stb_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -2025,7 +2025,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_STH, "sth", "sth",
-    { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x2020,
     (PTR) & fmt_sth_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -2034,7 +2034,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_STH_D, "sth-d", "sth",
-    { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
+    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0200000,
     (PTR) & fmt_sth_d_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
@@ -2043,7 +2043,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_ST_PLUS, "st-plus", "st",
-    { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x2060,
     (PTR) & fmt_st_plus_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -2052,7 +2052,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_ST_MINUS, "st-minus", "st",
-    { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x2070,
     (PTR) & fmt_st_plus_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -2061,7 +2061,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_SUB, "sub", "sub",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x20,
     (PTR) & fmt_add_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
@@ -2070,7 +2070,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_SUBV, "subv", "subv",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x0,
     (PTR) & fmt_addv_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
@@ -2079,7 +2079,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_SUBX, "subx", "subx",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 16, 16, 0xf0f0 }, 0x10,
     (PTR) & fmt_addx_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
@@ -2088,7 +2088,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_TRAP, "trap", "trap",
-    { MNEM, ' ', OP (UIMM4), 0 },
+    { { MNEM, ' ', OP (UIMM4), 0 } },
     { 16, 16, 0xfff0 }, 0x10f0,
     (PTR) & fmt_trap_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
@@ -2097,7 +2097,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_UNLOCK, "unlock", "unlock",
-    { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x2050,
     (PTR) & fmt_unlock_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
@@ -2107,7 +2107,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_SATB, "satb", "satb",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 32, 32, 0xf0f0ffff }, 0x80600300,
     (PTR) & fmt_satb_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
@@ -2118,7 +2118,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_SATH, "sath", "sath",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 32, 32, 0xf0f0ffff }, 0x80600200,
     (PTR) & fmt_satb_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
@@ -2129,7 +2129,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_SAT, "sat", "sat",
-    { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     { 32, 32, 0xf0f0ffff }, 0x80600000,
     (PTR) & fmt_sat_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
@@ -2140,7 +2140,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz",
-    { MNEM, ' ', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC2), 0 } },
     { 16, 16, 0xfff0 }, 0x370,
     (PTR) & fmt_cmpz_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
@@ -2151,7 +2151,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_SADD, "sadd", "sadd",
-    { MNEM, 0 },
+    { { MNEM, 0 } },
     { 16, 16, 0xffff }, 0x50e4,
     (PTR) & fmt_sadd_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
@@ -2162,7 +2162,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MACWU1, "macwu1", "macwu1",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x50b0,
     (PTR) & fmt_macwu1_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
@@ -2173,7 +2173,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MSBLO, "msblo", "msblo",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x50d0,
     (PTR) & fmt_machi_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
@@ -2184,7 +2184,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MULWU1, "mulwu1", "mulwu1",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x50a0,
     (PTR) & fmt_mulwu1_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
@@ -2195,7 +2195,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_MACLH1, "maclh1", "maclh1",
-    { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
     { 16, 16, 0xf0f0 }, 0x50c0,
     (PTR) & fmt_macwu1_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
@@ -2206,7 +2206,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_SC, "sc", "sc",
-    { MNEM, 0 },
+    { { MNEM, 0 } },
     { 16, 16, 0xffff }, 0x7401,
     (PTR) & fmt_sc_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_O } }
@@ -2217,7 +2217,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     M32R_INSN_SNC, "snc", "snc",
-    { MNEM, 0 },
+    { { MNEM, 0 } },
     { 16, 16, 0xffff }, 0x7501,
     (PTR) & fmt_sc_ops[0],
     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_O } }
@@ -2251,7 +2251,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "bc8r", "bc",
-    { MNEM, ' ', OP (DISP8), 0 },
+    { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7c00,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
@@ -2260,7 +2260,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "bc24r", "bc",
-    { MNEM, ' ', OP (DISP24), 0 },
+    { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xfc000000,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
@@ -2269,7 +2269,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "bl8r", "bl",
-    { MNEM, ' ', OP (DISP8), 0 },
+    { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7e00,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
@@ -2278,7 +2278,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "bl24r", "bl",
-    { MNEM, ' ', OP (DISP24), 0 },
+    { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xfe000000,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
@@ -2287,7 +2287,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "bcl8r", "bcl",
-    { MNEM, ' ', OP (DISP8), 0 },
+    { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7800,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
@@ -2296,7 +2296,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "bcl24r", "bcl",
-    { MNEM, ' ', OP (DISP24), 0 },
+    { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xf8000000,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
@@ -2305,7 +2305,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "bnc8r", "bnc",
-    { MNEM, ' ', OP (DISP8), 0 },
+    { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7d00,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
@@ -2314,7 +2314,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "bnc24r", "bnc",
-    { MNEM, ' ', OP (DISP24), 0 },
+    { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xfd000000,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
@@ -2323,7 +2323,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "bra8r", "bra",
-    { MNEM, ' ', OP (DISP8), 0 },
+    { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7f00,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
@@ -2332,7 +2332,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "bra24r", "bra",
-    { MNEM, ' ', OP (DISP24), 0 },
+    { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xff000000,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
@@ -2341,7 +2341,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "bncl8r", "bncl",
-    { MNEM, ' ', OP (DISP8), 0 },
+    { { MNEM, ' ', OP (DISP8), 0 } },
     { 16, 16, 0xff00 }, 0x7900,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
@@ -2350,7 +2350,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "bncl24r", "bncl",
-    { MNEM, ' ', OP (DISP24), 0 },
+    { { MNEM, ' ', OP (DISP24), 0 } },
     { 32, 32, 0xff000000 }, 0xf9000000,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
@@ -2359,7 +2359,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "ld-2", "ld",
-    { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
     { 16, 16, 0xf0f0 }, 0x20c0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
@@ -2368,7 +2368,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "ld-d2", "ld",
-    { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0c00000,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
@@ -2377,7 +2377,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "ldb-2", "ldb",
-    { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
     { 16, 16, 0xf0f0 }, 0x2080,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
@@ -2386,7 +2386,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "ldb-d2", "ldb",
-    { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0800000,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
@@ -2395,7 +2395,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "ldh-2", "ldh",
-    { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
     { 16, 16, 0xf0f0 }, 0x20a0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
@@ -2404,7 +2404,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "ldh-d2", "ldh",
-    { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0a00000,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
@@ -2413,7 +2413,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "ldub-2", "ldub",
-    { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
     { 16, 16, 0xf0f0 }, 0x2090,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
@@ -2422,7 +2422,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "ldub-d2", "ldub",
-    { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0900000,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
@@ -2431,7 +2431,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "lduh-2", "lduh",
-    { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
     { 16, 16, 0xf0f0 }, 0x20b0,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
@@ -2440,7 +2440,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "lduh-d2", "lduh",
-    { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
+    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0b00000,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
@@ -2449,7 +2449,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "pop", "pop",
-    { MNEM, ' ', OP (DR), 0 },
+    { { MNEM, ' ', OP (DR), 0 } },
     { 16, 16, 0xf0ff }, 0x20ef,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
@@ -2458,7 +2458,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "ldi8a", "ldi",
-    { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
     { 16, 16, 0xf000 }, 0x6000,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
@@ -2467,7 +2467,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "ldi16a", "ldi",
-    { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
     { 32, 32, 0xf0ff0000 }, 0x90f00000,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
@@ -2476,7 +2476,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "rac-d", "rac",
-    { MNEM, ' ', OP (ACCD), 0 },
+    { { MNEM, ' ', OP (ACCD), 0 } },
     { 16, 16, 0xf3ff }, 0x5090,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
@@ -2485,7 +2485,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "rac-ds", "rac",
-    { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
+    { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
     { 16, 16, 0xf3f3 }, 0x5090,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
@@ -2494,7 +2494,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "rach-d", "rach",
-    { MNEM, ' ', OP (ACCD), 0 },
+    { { MNEM, ' ', OP (ACCD), 0 } },
     { 16, 16, 0xf3ff }, 0x5080,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
@@ -2503,7 +2503,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "rach-ds", "rach",
-    { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
+    { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
     { 16, 16, 0xf3f3 }, 0x5080,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
@@ -2512,7 +2512,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "st-2", "st",
-    { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
+    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
     { 16, 16, 0xf0f0 }, 0x2040,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
@@ -2521,7 +2521,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "st-d2", "st",
-    { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
+    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0400000,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
@@ -2530,7 +2530,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "stb-2", "stb",
-    { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
+    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
     { 16, 16, 0xf0f0 }, 0x2000,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
@@ -2539,7 +2539,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "stb-d2", "stb",
-    { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
+    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0000000,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
@@ -2548,7 +2548,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "sth-2", "sth",
-    { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
+    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
     { 16, 16, 0xf0f0 }, 0x2020,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
@@ -2557,7 +2557,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "sth-d2", "sth",
-    { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
+    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
     { 32, 32, 0xf0f00000 }, 0xa0200000,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
@@ -2566,7 +2566,7 @@ static const CGEN_INSN macro_insn_table_entries[] =
   {
     { 1, 1, 1, 1 },
     -1, "push", "push",
-    { MNEM, ' ', OP (SRC1), 0 },
+    { { MNEM, ' ', OP (SRC1), 0 } },
     { 16, 16, 0xf0ff }, 0x207f,
     (PTR) 0,
     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
@@ -2587,7 +2587,7 @@ static CGEN_INSN_TABLE macro_insn_table =
 };
 
 /* The hash functions are recorded here to help keep assembler code out of
-   the disassembler and vice versa.
+   the disassembler and vice versa.  */
 
 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
 static unsigned int asm_hash_insn PARAMS ((const char *));