FLAGS are the bitwise-or of the traits that apply to that core.
This need not include flags implied by the architecture.
COSTS is the name of the rtx_costs routine to use.
- IMP is the implementer ID of the CPU vendor. On a GNU/Linux system it can
- be found in /proc/cpuinfo.
- PART is the part number of the CPU. On a GNU/Linux system it can be found
- in /proc/cpuinfo. For big.LITTLE systems this should have the form at of
- "<big core part number>.<LITTLE core part number>". */
+ IMP is the implementer ID of the CPU vendor. On a GNU/Linux system it
+ can be found in /proc/cpuinfo. A partial list of implementer IDs is
+ given in the ARM Architecture Reference Manual ARMv8, for
+ ARMv8-A architecture profile.
+ PART is the part number of the CPU. On a GNU/Linux system it can be
+ found in /proc/cpuinfo. For big.LITTLE systems this should use the
+ macro AARCH64_BIG_LITTLE where the big part number comes as the first
+ argument to the macro and little is the second. */
/* V8 Architecture Processors. */
/* ARM ('A') cores. */
-AARCH64_CORE("cortex-a35", cortexa35, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa35, "0x41", "0xd04")
-AARCH64_CORE("cortex-a53", cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa53, "0x41", "0xd03")
-AARCH64_CORE("cortex-a57", cortexa57, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, "0x41", "0xd07")
-AARCH64_CORE("cortex-a72", cortexa72, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, "0x41", "0xd08")
-AARCH64_CORE("cortex-a73", cortexa73, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, "0x41", "0xd09")
+AARCH64_CORE("cortex-a35", cortexa35, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa35, 0x41, 0xd04)
+AARCH64_CORE("cortex-a53", cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa53, 0x41, 0xd03)
+AARCH64_CORE("cortex-a57", cortexa57, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, 0x41, 0xd07)
+AARCH64_CORE("cortex-a72", cortexa72, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, 0x41, 0xd08)
+AARCH64_CORE("cortex-a73", cortexa73, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, 0x41, 0xd09)
/* Samsung ('S') cores. */
-AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1, "0x53", "0x001")
+AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1, 0x53, 0x001)
/* Qualcomm ('Q') cores. */
-AARCH64_CORE("qdf24xx", qdf24xx, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx, "0x51", "0x800")
+AARCH64_CORE("qdf24xx", qdf24xx, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx, 0x51, 0x800)
/* Cavium ('C') cores. */
-AARCH64_CORE("thunderx", thunderx, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, "0x43", "0x0a1")
+AARCH64_CORE("thunderx", thunderx, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, 0x43, 0x0a1)
/* APM ('P') cores. */
-AARCH64_CORE("xgene1", xgene1, xgene1, 8A, AARCH64_FL_FOR_ARCH8, xgene1, "0x50", "0x000")
+AARCH64_CORE("xgene1", xgene1, xgene1, 8A, AARCH64_FL_FOR_ARCH8, xgene1, 0x50, 0x000)
/* V8.1 Architecture Processors. */
/* Broadcom ('B') cores. */
-AARCH64_CORE("vulcan", vulcan, cortexa57, 8_1A, AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, vulcan, "0x42", "0x516")
+AARCH64_CORE("vulcan", vulcan, cortexa57, 8_1A, AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, vulcan, 0x42, 0x516)
/* V8 big.LITTLE implementations. */
-AARCH64_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, "0x41", "0xd07.0xd03")
-AARCH64_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, "0x41", "0xd08.0xd03")
-AARCH64_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, "0x41", "0xd09.0xd04")
-AARCH64_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, "0x41", "0xd09.0xd03")
+AARCH64_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, 0x41, AARCH64_BIG_LITTLE (0xd07, 0xd03))
+AARCH64_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, 0x41, AARCH64_BIG_LITTLE (0xd08, 0xd03))
+AARCH64_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd09, 0xd04))
+AARCH64_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd09, 0xd03))
#undef AARCH64_CORE
{
const char* name;
const char* arch;
- const char* implementer_id;
- const char* part_no;
+ unsigned char implementer_id; /* Exactly 8 bits */
+ unsigned int part_no; /* 12 bits + 12 bits */
const unsigned long flags;
};
+#define AARCH64_BIG_LITTLE(BIG, LITTLE) \
+ (((BIG)&0xFFFu) << 12 | ((LITTLE) & 0xFFFu))
+#define INVALID_IMP ((unsigned char) -1)
+#define INVALID_CORE ((unsigned)-1)
+
#define AARCH64_CORE(CORE_NAME, CORE_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART) \
{ CORE_NAME, #ARCH, IMP, PART, FLAGS },
static struct aarch64_core_data aarch64_cpu_data[] =
{
#include "aarch64-cores.def"
- { NULL, NULL, NULL, NULL, 0 }
+ { NULL, NULL, INVALID_IMP, INVALID_CORE, 0 }
};
return NULL;
}
-/* Check wether the string CORE contains the same CPU part numbers
- as BL_STRING. For example CORE="{0xd03, 0xd07}" and BL_STRING="0xd07.0xd03"
- should return true. */
+/* Check wether the CORE array is the same as the big.LITTLE BL_CORE.
+ For an example CORE={0xd08, 0xd03} and
+ BL_CORE=AARCH64_BIG_LITTLE (0xd08, 0xd03) will return true. */
static bool
-valid_bL_string_p (const char** core, const char* bL_string)
+valid_bL_core_p (unsigned int *core, unsigned int bL_core)
+{
+ return AARCH64_BIG_LITTLE (core[0], core[1]) == bL_core
+ || AARCH64_BIG_LITTLE (core[1], core[0]) == bL_core;
+}
+
+/* Returns the hex integer that is after ':' for the FIELD.
+ Returns -1 is returned if there was problem parsing the integer. */
+static unsigned
+parse_field (const char *field)
{
- return strstr (bL_string, core[0]) != NULL
- && strstr (bL_string, core[1]) != NULL;
+ const char *rest = strchr (field, ':');
+ char *after;
+ unsigned fint = strtol (rest + 1, &after, 16);
+ if (after == rest + 1)
+ return -1;
+ return fint;
}
-/* Return true iff ARR contains STR in one of its two elements. */
+/* Return true iff ARR contains CORE, in either of the two elements. */
static bool
-contains_string_p (const char** arr, const char* str)
+contains_core_p (unsigned *arr, unsigned core)
{
- bool res = false;
-
- if (arr[0] != NULL)
+ if (arr[0] != INVALID_CORE)
{
- res = strstr (arr[0], str) != NULL;
- if (res)
- return res;
+ if (arr[0] == core)
+ return true;
- if (arr[1] != NULL)
- return strstr (arr[1], str) != NULL;
+ if (arr[1] != INVALID_CORE)
+ return arr[1] == core;
}
return false;
bool cpu = false;
unsigned int i = 0;
unsigned int core_idx = 0;
- const char* imps[2] = { NULL, NULL };
- const char* cores[2] = { NULL, NULL };
+ unsigned char imp = INVALID_IMP;
+ unsigned int cores[2] = { INVALID_CORE, INVALID_CORE };
unsigned int n_cores = 0;
- unsigned int n_imps = 0;
bool processed_exts = false;
const char *ext_string = "";
unsigned long extension_flags = 0;
{
if (strstr (buf, "implementer") != NULL)
{
- for (i = 0; aarch64_cpu_data[i].name != NULL; i++)
- if (strstr (buf, aarch64_cpu_data[i].implementer_id) != NULL
- && !contains_string_p (imps,
- aarch64_cpu_data[i].implementer_id))
- {
- if (n_imps == 2)
- goto not_found;
-
- imps[n_imps++] = aarch64_cpu_data[i].implementer_id;
-
- break;
- }
- continue;
+ unsigned cimp = parse_field (buf);
+ if (cimp == INVALID_IMP)
+ goto not_found;
+
+ if (imp == INVALID_IMP)
+ imp = cimp;
+ /* FIXME: BIG.little implementers are always equal. */
+ else if (imp != cimp)
+ goto not_found;
}
if (strstr (buf, "part") != NULL)
{
+ unsigned ccore = parse_field (buf);
for (i = 0; aarch64_cpu_data[i].name != NULL; i++)
- if (strstr (buf, aarch64_cpu_data[i].part_no) != NULL
- && !contains_string_p (cores, aarch64_cpu_data[i].part_no))
+ if (ccore == aarch64_cpu_data[i].part_no
+ && !contains_core_p (cores, ccore))
{
if (n_cores == 2)
goto not_found;
- cores[n_cores++] = aarch64_cpu_data[i].part_no;
+ cores[n_cores++] = ccore;
core_idx = i;
arch_id = aarch64_cpu_data[i].arch;
break;
f = NULL;
/* Weird cpuinfo format that we don't know how to handle. */
- if (n_cores == 0 || n_cores > 2 || n_imps != 1)
+ if (n_cores == 0 || n_cores > 2 || imp == INVALID_IMP)
goto not_found;
if (arch && !arch_id)
{
for (i = 0; aarch64_cpu_data[i].name != NULL; i++)
{
- if (strchr (aarch64_cpu_data[i].part_no, '.') != NULL
- && strncmp (aarch64_cpu_data[i].implementer_id,
- imps[0],
- strlen (imps[0]) - 1) == 0
- && valid_bL_string_p (cores, aarch64_cpu_data[i].part_no))
+ if (aarch64_cpu_data[i].implementer_id == imp
+ && valid_bL_core_p (cores, aarch64_cpu_data[i].part_no))
{
res = concat ("-m",
cpu ? "cpu" : "tune", "=",
/* The simple, non-big.LITTLE case. */
else
{
- if (strncmp (aarch64_cpu_data[core_idx].implementer_id, imps[0],
- strlen (imps[0]) - 1) != 0)
+ if (aarch64_cpu_data[core_idx].implementer_id != imp)
goto not_found;
res = concat ("-m", cpu ? "cpu" : "tune", "=",
projects / gcc.git / commitdiff