clarify abridged

diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn
index 981308b6d9f2bc03a6a532c12566d5dcfb40a67e..8197c17d04aaf6fd9414aa4bdfcc8868360f7096 100644 (file)
--- a/simple_v_extension/abridged_spec.mdwn
+++ b/simple_v_extension/abridged_spec.mdwn
@@ -37,10 +37,10 @@ the behaviour becomes effectively identical to standard RV execution, however
 SV is never truly actually "off".
 
 Note: **there are *no* new opcodes**. The scheme works *entirely*
-on hidden context that augments *scalar* RISC-V instructions.  Thus it
-may cover existing, future and custom scalar extensions, turning all
-existing, all future and all custom scalar operations parallel, without
-requiring any special opcodes to do so.
+on hidden context that augments (nests) *scalar* RISC-V instructions.
+Thus it may cover existing, future and custom scalar extensions, turning
+all existing, all future and all custom scalar operations parallel,
+without requiring any special (identical, parallel variant) opcodes to do so.
 
 # CSRs <a name="csrs"></a>