freedreno/registers: update varying-related registers

Note:

* a3xx change based on available register documentation
* a4xx guesses (RB_RENDER_CONTROL2 bits especially)
* a5xx change based on a6xx, these registers seem identical

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5582>

diff --git a/src/freedreno/registers/a3xx.xml b/src/freedreno/registers/a3xx.xml
index 5cfa1fe9ea924324d8005f85bca8701efcc09795..c8849693f8c9d54dd7d28ed8bf05738b83bbb411 100644 (file)
--- a/src/freedreno/registers/a3xx.xml
+++ b/src/freedreno/registers/a3xx.xml
@@ -792,7 +792,10 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 
        <!-- GRAS registers -->
        <reg32 offset="0x2040" name="GRAS_CL_CLIP_CNTL">
-               <bitfield name="IJ_PERSP_CENTER" pos="12" type="boolean"/> <!-- is it more bits? -->
+               <bitfield name="IJ_PERSP_CENTER" pos="12" type="boolean"/>
+               <bitfield name="IJ_NON_PERSP_CENTER" pos="13" type="boolean"/>
+               <bitfield name="IJ_PERSP_CENTROID" pos="14" type="boolean"/>
+               <bitfield name="IJ_NON_PERSP_CENTROID" pos="15" type="boolean"/>
                <bitfield name="CLIP_DISABLE" pos="16" type="boolean"/>
                <bitfield name="ZFAR_CLIP_DISABLE" pos="17" type="boolean"/>
                <bitfield name="VP_CLIP_CODE_IGNORE" pos="19" type="boolean"/>
@@ -1135,8 +1138,10 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
                <bitfield name="PRIMALLOCTHRESHOLD" low="26" high="31" type="uint"/>
        </reg32>
        <reg32 offset="0x2203" name="HLSQ_CONTROL_3_REG">
-               <!-- register loaded with position (bary.f, gl_FragCoord, etc) -->
-               <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
+               <bitfield name="IJPERSPCENTERREGID" low="0" high="7" type="a3xx_regid"/>
+               <bitfield name="IJNONPERSPCENTERREGID" low="8" high="15" type="a3xx_regid"/>
+               <bitfield name="IJPERSPCENTROIDREGID" low="16" high="23" type="a3xx_regid"/>
+               <bitfield name="IJNONPERSPCENTROIDREGID" low="24" high="31" type="a3xx_regid"/>
        </reg32>
        <reg32 offset="0x2204" name="HLSQ_VS_CONTROL_REG" type="a3xx_hlsq_vs_fs_control_reg"/>
        <reg32 offset="0x2205" name="HLSQ_FS_CONTROL_REG" type="a3xx_hlsq_vs_fs_control_reg"/>

diff --git a/src/freedreno/registers/a4xx.xml b/src/freedreno/registers/a4xx.xml
index 284e491c886a5443696217c7b3cbb480f807d9b7..454ee596de8eb05309a0afd24149f700e8be155a 100644 (file)
--- a/src/freedreno/registers/a4xx.xml
+++ b/src/freedreno/registers/a4xx.xml
@@ -2058,11 +2058,17 @@ perhaps they should be taken with a grain of salt
                <bitfield name="SAMPLEMASK_REGID" low="18" high="25" type="a3xx_regid"/>
        </reg32>
        <reg32 offset="0x23c3" name="HLSQ_CONTROL_3_REG">
-               <!-- register loaded with position (bary.f, gl_FragCoord, etc) -->
-               <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
+               <!-- register loaded with position (bary.f) -->
+               <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
+               <bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>
+               <bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>
+               <bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>
        </reg32>
        <!-- 0x23c4 3 regids, lowest one goes to 0 when *not* per-sample shading -->
-       <reg32 offset="0x23c4" name="HLSQ_CONTROL_4_REG"/>
+       <reg32 offset="0xb985" name="HLSQ_CONTROL_4_REG">
+               <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
+               <bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>
+       </reg32>
 
        <bitset name="a4xx_xs_control_reg" inline="yes">
                <bitfield name="CONSTLENGTH" low="0" high="7" type="uint"/>

diff --git a/src/freedreno/registers/a5xx.xml b/src/freedreno/registers/a5xx.xml
index f954a7bd8adecb07fb350026c4348ea0a4691ca0..d80691d61d53c9ece6cfc8b971516f0f4282f03c 100644 (file)
--- a/src/freedreno/registers/a5xx.xml
+++ b/src/freedreno/registers/a5xx.xml
@@ -1825,7 +1825,9 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
        <reg32 offset="0xe004" name="UNKNOWN_E004"/> <!-- always 00000000? -->
        <reg32 offset="0xe005" name="GRAS_CNTL">
                <!-- see also RB_RENDER_CONTROL0 -->
-               <bitfield name="VARYING" pos="0" type="boolean"/>
+               <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
+               <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
+               <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
                <!--
                bit 3 set when blob turns on WCOORD.. which also corresponds to
                register being set in in HLSQ_CONTROL_3_REG bits 8..15 (which
@@ -1833,7 +1835,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
                way??
                Also, when that happens, VARYING bits are turned on as well.
                 -->
-               <bitfield name="UNK3" pos="3" type="boolean"/>
+               <bitfield name="SIZE" pos="3" type="boolean"/>
                <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
        </reg32>
        <reg32 offset="0xe006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
@@ -1976,7 +1978,9 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32?  not set
         -->
        <reg32 offset="0xe144" name="RB_RENDER_CONTROL0">
                <!-- see also GRAS_CNTL -->
-               <bitfield name="VARYING" pos="0" type="boolean"/>
+               <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
+               <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
+               <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
                <!--
                bit 3 set when blob turns on WCOORD.. which also corresponds to
                register being set in in HLSQ_CONTROL_3_REG bits 8..15 (which
@@ -1984,7 +1988,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32?  not set
                way??
                Also, when that happens, VARYING bits are turned on as well.
                 -->
-               <bitfield name="UNK3" pos="3" type="boolean"/>
+               <bitfield name="SIZE" pos="3" type="boolean"/>
                <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
        </reg32>
        <reg32 offset="0xe145" name="RB_RENDER_CONTROL1">
@@ -2633,12 +2637,18 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32?  not set
                <!-- SAMPLEID is loaded into a half-precision register: -->
                <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
                <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
+               <bitfield name="SIZE" low="24" high="31" type="a3xx_regid"/>
        </reg32>
        <reg32 offset="0xe787" name="HLSQ_CONTROL_3_REG">
                <!-- register loaded with position (bary.f) -->
-               <bitfield name="FRAGCOORDXYREGID" low="0" high="7" type="a3xx_regid"/>
+               <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
+               <bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>
+               <bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>
+               <bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>
        </reg32>
        <reg32 offset="0xe788" name="HLSQ_CONTROL_4_REG">
+               <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
+               <bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>
                <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
                <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
        </reg32>

diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml
index 129ec464e48f5dc707af9cd003e3e7d42dcea34a..06e51d7c439de8433ebcb35114fe95de680721ce 100644 (file)
--- a/src/freedreno/registers/a6xx.xml
+++ b/src/freedreno/registers/a6xx.xml
@@ -1902,11 +1902,11 @@ to upconvert to 32b float internally?
 
        <reg32 offset="0x8005" name="GRAS_CNTL">
                <!-- see also RB_RENDER_CONTROL0 -->
-               <bitfield name="VARYING" pos="0" type="boolean"/>
+               <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
                <!-- b1 set for interpolateAtCentroid() -->
-               <bitfield name="CENTROID" pos="1" type="boolean"/>
+               <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
                <!-- b2 set instead of b0 when running in per-sample mode -->
-               <bitfield name="PERSAMP_VARYING" pos="2" type="boolean"/>
+               <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
                <!--
                b3 set for interpolateAt{Offset,Sample}() if not in per-sample
                mode, and frag_face
@@ -2158,11 +2158,11 @@ to upconvert to 32b float internally?
         -->
        <reg32 offset="0x8809" name="RB_RENDER_CONTROL0">
                <!-- see also GRAS_CNTL -->
-               <bitfield name="VARYING" pos="0" type="boolean"/>
+               <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
                <!-- b1 set for interpolateAtCentroid() -->
-               <bitfield name="CENTROID" pos="1" type="boolean"/>
+               <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
                <!-- b2 set instead of b0 when running in per-sample mode -->
-               <bitfield name="PERSAMP_VARYING" pos="2" type="boolean"/>
+               <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
                <!--
                b3 set for interpolateAt{Offset,Sample}() if not in per-sample
                mode, and frag_face
@@ -3320,11 +3320,14 @@ to upconvert to 32b float internally?
        </reg32>
        <reg32 offset="0xb984" name="HLSQ_CONTROL_3_REG">
                <!-- register loaded with position (bary.f) -->
-               <bitfield name="BARY_IJ_PIXEL" low="0" high="7" type="a3xx_regid"/>
-               <bitfield name="BARY_IJ_CENTROID" low="16" high="23" type="a3xx_regid"/>
+               <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
+               <bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>
+               <bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>
+               <bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>
        </reg32>
        <reg32 offset="0xb985" name="HLSQ_CONTROL_4_REG">
-               <bitfield name="BARY_IJ_PIXEL_PERSAMP" low="0" high="7" type="a3xx_regid"/>
+               <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
+               <bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>
                <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
                <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
        </reg32>

diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index 64a92008af2a34d142343873e0d74675f824c706..ca05fa3beca2497ea93f99f234bd3761c0e0c825 100644 (file)
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -1150,12 +1150,12 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
                   A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
                   A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
                   A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
-   tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
-                  A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
+   tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_pix_regid) |
+                  A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_cent_regid) |
                   0xfc00fc00);
    tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
                   A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
-                  A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
+                  A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_samp_regid) |
                   0x0000fc00);
    tu_cs_emit(cs, 0xfc);
 
@@ -1164,9 +1164,9 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
 
    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
    tu_cs_emit(cs,
-         CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
-         CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
-         CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
+         CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
+         CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
+         CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
          COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
          COND(VALIDREG(ij_size_regid) &&  sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
          COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_SIZE |
@@ -1175,9 +1175,9 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
 
    tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
    tu_cs_emit(cs,
-         CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
-         CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
-         CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
+         CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
+         CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
+         CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
          COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
          COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
          COND(VALIDREG(ij_size_regid) &&  sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |

diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_program.c b/src/gallium/drivers/freedreno/a3xx/fd3_program.c
index 238b7dafdd81a3720addcc90262ff4a8e64fa27a..8ab7cd2cbb6ac560ef122a9a9eafda897fb36f3a 100644 (file)
--- a/src/gallium/drivers/freedreno/a3xx/fd3_program.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_program.c
@@ -203,7 +203,7 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
                        A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(zwcoord_regid));
        OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31) |
                        A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(face_regid));
-       OUT_RING(ring, A3XX_HLSQ_CONTROL_3_REG_REGID(vcoord_regid));
+       OUT_RING(ring, A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID(vcoord_regid));
        OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) |
                        A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
                        A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vpbuffersz));

diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_program.c b/src/gallium/drivers/freedreno/a4xx/fd4_program.c
index 9484a219eb02dbf82901128d51c335a7174bd21c..1a9c43ab9f57d3bdfb2ae6942eea56f345d2a5b3 100644 (file)
--- a/src/gallium/drivers/freedreno/a4xx/fd4_program.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_program.c
@@ -235,7 +235,7 @@ fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit,
        OUT_RING(ring, A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(63) |
                        0x3f3f000 |           /* XXX */
                        A4XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid));
-       OUT_RING(ring, A4XX_HLSQ_CONTROL_3_REG_REGID(vcoord_regid) |
+       OUT_RING(ring, A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(vcoord_regid) |
                        0xfcfcfc00);
        OUT_RING(ring, 0x00fcfcfc);   /* XXX HLSQ_CONTROL_4 */
 

diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_program.c b/src/gallium/drivers/freedreno/a5xx/fd5_program.c
index 258a643144345433f972acef73393982c8c89ee8..0d812487f0b4b290d5a0f25b627f6f7be45ebfc0 100644 (file)
--- a/src/gallium/drivers/freedreno/a5xx/fd5_program.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_program.c
@@ -511,7 +511,7 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
                        A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
                        A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samp_mask_regid) |
                        0xfc000000);               /* XXX */
-       OUT_RING(ring, A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(vcoord_regid) |
+       OUT_RING(ring, A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(vcoord_regid) |
                        0xfcfcfc00);               /* XXX */
        OUT_RING(ring, A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
                        A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
@@ -537,18 +537,18 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
        OUT_RING(ring, 0x00000010);        /* XXX */
 
        OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
-       OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_GRAS_CNTL_VARYING) |
+       OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
                        COND(s[FS].v->fragcoord_compmask != 0,
                                        A5XX_GRAS_CNTL_COORD_MASK(s[FS].v->fragcoord_compmask) |
-                                       A5XX_GRAS_CNTL_UNK3) |
-                       COND(s[FS].v->frag_face, A5XX_GRAS_CNTL_UNK3));
+                                       A5XX_GRAS_CNTL_SIZE) |
+                       COND(s[FS].v->frag_face, A5XX_GRAS_CNTL_SIZE));
 
        OUT_PKT4(ring, REG_A5XX_RB_RENDER_CONTROL0, 2);
-       OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_RB_RENDER_CONTROL0_VARYING) |
+       OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
                        COND(s[FS].v->fragcoord_compmask != 0,
                                        A5XX_RB_RENDER_CONTROL0_COORD_MASK(s[FS].v->fragcoord_compmask) |
-                                       A5XX_RB_RENDER_CONTROL0_UNK3) |
-                       COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL0_UNK3));
+                                       A5XX_RB_RENDER_CONTROL0_SIZE) |
+                       COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL0_SIZE));
        OUT_RING(ring,
                        COND(samp_mask_regid != regid(63, 0),
                                A5XX_RB_RENDER_CONTROL1_SAMPLEMASK) |

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
index 5b5d9b56420c8b31f7bba691431baec52a6277a2..34fccfd1c84f03d4b7c4bae400fa57b1c4716648 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
@@ -638,12 +638,12 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
                         A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
                         A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
                         A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
-       OUT_RING(ring, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
-                        A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
+       OUT_RING(ring, A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_pix_regid) |
+                        A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_cent_regid) |
                         0xfc00fc00);               /* XXX */
        OUT_RING(ring, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
                         A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
-                        A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
+                        A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_samp_regid) |
                         0x0000fc00);               /* XXX */
        OUT_RING(ring, 0xfc);              /* XXX */
 
@@ -668,9 +668,9 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
 
        OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
        OUT_RING(ring,
-                       CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
-                       CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
-                       CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
+                       CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
+                       CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
+                       CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
                        COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
                        COND(VALIDREG(ij_size_regid) &&  sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
                        COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_SIZE |
@@ -679,9 +679,9 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
 
        OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
        OUT_RING(ring,
-                       CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
-                       CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
-                       CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
+                       CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
+                       CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
+                       CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
                        COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
                        COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
                        COND(VALIDREG(ij_size_regid) &&  sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |