Do not simplemap for variable test

diff --git a/tests/xilinx/xilinx_srl.ys b/tests/xilinx/xilinx_srl.ys
index 4e3c44a98e176cf8a791da2a16500adbfab7cd43..b8df0e55a396661b16b926e0d499532ecb27a263 100644 (file)
--- a/tests/xilinx/xilinx_srl.ys
+++ b/tests/xilinx/xilinx_srl.ys
@@ -40,14 +40,14 @@ hierarchy -top xilinx_srl_variable_test
 prep
 design -save gold
 
-simplemap t:$dff t:$dffe
 xilinx_srl -variable
 opt
 
 #stat
 # show -width
 # write_verilog -noexpr -norename
-select -assert-count 1 t:$_DFF_P_
+select -assert-count 1 t:$dff
+select -assert-count 1 t:$dff r:WIDTH=1 %i
 select -assert-count 2 t:$__XILINX_SHREG_
 
 design -stash gate