Fix $__XILINX_MUXF78 box timing

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 273d365739006bc1109855849c0e9ccf286517b8..3789ff350ab479dd07dc7e0786567af02796c070 100644 (file)
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -17,7 +17,7 @@ MUXF8 2 1 3 1
 # Inputs: I0 I1 I2 I3 S0 S1
 # Outputs: O
 $__MUXF78 3 1 6 1
-190 193 217 223 296 273
+294 297 311 317 390 273
 
 # CARRY4 + CARRY4_[ABCD]X
 # Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI