(no commit message)

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 087142d0034f3f343ba473db5f3cca32b11988dc..d92de32faa25da1d2b7794053581413c168d6549 100644 (file)
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -55,6 +55,16 @@ Idea 2: implement using outer loop on varying setvl Horizontal-First
 with `1<<r3` predicate mask for src2 as scalar, creates CR field vector, transfer into INT with mfcrweird then OR into
 result.
 
+    li r3, 1
+    li result, 0
+    for i in range(target):
+        setvl target
+        sv.addi/sm=1<<r3 t0, src1.v, 0 # copy src1[i]
+        sv.cmpi src2.v, t0 # compare src2 vector to scalar
+        mfcrweird t1, cr0.v, eq # copy CR eq result bits to t1
+        or result, result, t1
+        srr r3, r3, 1 # shift r3 predicate up by one
+
 ## iota
 
 Based on RVV vmiota.  vmiota may be viewed as a cumulative variant of popcount, generating multiple results.  successive iterations include more and more bits of the bitstream being tested.