ARM: Set ITSTATE correctly after FlushPipe

diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index e388c72a875efea91070ee7222f72b038d1b10be..9ce2e2da41b80c1e29714ca31bc84c4b48086dfe 100644 (file)
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -220,6 +220,7 @@ FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
     // start refetching from the next instruction.
     PCState pc = tc->pcState();
     assert(inst);
+    pc.forcedItState(inst->machInst.newItstate);
     inst->advancePC(pc);
     tc->pcState(pc);
 }