i965/fs: Don't interfere with too many base registers

On older GENs in SIMD16 mode, we were accidentally building too much
interference into our register classes.  Since everything is divided by 2,
the reigster allocator thinks we have 64 base registers instead of 128.
The actual GRF mapping still needs to be doubled, but as far as the ra_set
is concerned, we only have 64.  We were accidentally adding way too much
interference.

Signed-off-by: Jason Ekstrand <jason.ekstrand@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 34ee40fd050b8541eba14431d0ad163eca66b95f..0c4888fbd578bb91f85b8debf75f52bd83bf6358 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -179,8 +179,8 @@ brw_alloc_reg_set(struct intel_screen *screen, int reg_width)
 
             ra_reg_to_grf[reg] = j * 2;
 
-            for (int base_reg = j * 2;
-                 base_reg < j * 2 + class_sizes[i];
+            for (int base_reg = j;
+                 base_reg < j + (class_sizes[i] + 1) / 2;
                  base_reg++) {
                ra_add_transitive_reg_conflict(regs, base_reg, reg);
             }