vexriscv: update

diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog
index 3b5b0e7c13ae2b7874fac40cbb3c4dc75deb1e1d..e8a30b95b9aa1445b5a4a76579a98a0552e2db53 160000 (submodule)
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ b/litex/soc/cores/cpu/vexriscv/verilog
@@ -1 +1 @@
-Subproject commit 3b5b0e7c13ae2b7874fac40cbb3c4dc75deb1e1d
+Subproject commit e8a30b95b9aa1445b5a4a76579a98a0552e2db53