return x;
}
-static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
-static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
-static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP;
static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM;
if (!op_disp && i.types[op].bitfield.baseindex)
{
- i.types[op].bitfield.disp8 = 0;
- i.types[op].bitfield.disp16 = 0;
- i.types[op].bitfield.disp32 = 0;
- i.types[op].bitfield.disp32s = 0;
- i.types[op].bitfield.disp64 = 0;
- i.op[op].disps = 0;
+ i.types[op] = operand_type_and_not (i.types[op], anydisp);
+ i.op[op].disps = NULL;
i.disp_operands--;
continue;
}
{
fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
i.op[op].disps, 0, i.reloc[op]);
- i.types[op].bitfield.disp8 = 0;
- i.types[op].bitfield.disp16 = 0;
- i.types[op].bitfield.disp32 = 0;
- i.types[op].bitfield.disp32s = 0;
- i.types[op].bitfield.disp64 = 0;
+ i.types[op] = operand_type_and_not (i.types[op], anydisp);
}
else
/* We only support 64bit displacement on constants. */
{
i.sib.base = NO_BASE_REGISTER;
i.sib.scale = i.log2_scale_factor;
- i.types[op].bitfield.disp8 = 0;
- i.types[op].bitfield.disp16 = 0;
- i.types[op].bitfield.disp64 = 0;
+ i.types[op] = operand_type_and_not (i.types[op], anydisp);
if (want_disp32 (&i.tm))
- {
- /* Must be 32 bit */
- i.types[op].bitfield.disp32 = 1;
- i.types[op].bitfield.disp32s = 0;
- }
+ i.types[op].bitfield.disp32 = 1;
else
- {
- i.types[op].bitfield.disp32 = 0;
- i.types[op].bitfield.disp32s = 1;
- }
+ i.types[op].bitfield.disp32s = 1;
}
/* Since the mandatory SIB always has index register, so
fake_zero_displacement = 1;
if (i.index_reg == 0)
{
- i386_operand_type newdisp;
-
/* Both check for VSIB and mandatory non-vector SIB. */
gas_assert (!i.tm.opcode_modifier.sib
|| i.tm.opcode_modifier.sib == SIBMEM);
/* Operand is just <disp> */
+ i.types[op] = operand_type_and_not (i.types[op], anydisp);
if (flag_code == CODE_64BIT)
{
/* 64bit mode overwrites the 32bit absolute
i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
i.sib.base = NO_BASE_REGISTER;
i.sib.index = NO_INDEX_REGISTER;
- newdisp = (want_disp32(&i.tm) ? disp32 : disp32s);
+ if (want_disp32 (&i.tm))
+ i.types[op].bitfield.disp32 = 1;
+ else
+ i.types[op].bitfield.disp32s = 1;
}
else if ((flag_code == CODE_16BIT)
^ (i.prefix[ADDR_PREFIX] != 0))
{
i.rm.regmem = NO_BASE_REGISTER_16;
- newdisp = disp16;
+ i.types[op].bitfield.disp16 = 1;
}
else
{
i.rm.regmem = NO_BASE_REGISTER;
- newdisp = disp32;
+ i.types[op].bitfield.disp32 = 1;
}
- i.types[op] = operand_type_and_not (i.types[op], anydisp);
- i.types[op] = operand_type_or (i.types[op], newdisp);
}
else if (!i.tm.opcode_modifier.sib)
{
i.sib.base = NO_BASE_REGISTER;
i.sib.scale = i.log2_scale_factor;
i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
- i.types[op].bitfield.disp8 = 0;
- i.types[op].bitfield.disp16 = 0;
- i.types[op].bitfield.disp64 = 0;
+ i.types[op] = operand_type_and_not (i.types[op], anydisp);
if (want_disp32 (&i.tm))
- {
- /* Must be 32 bit */
- i.types[op].bitfield.disp32 = 1;
- i.types[op].bitfield.disp32s = 0;
- }
+ i.types[op].bitfield.disp32 = 1;
else
- {
- i.types[op].bitfield.disp32 = 0;
- i.types[op].bitfield.disp32s = 1;
- }
+ i.types[op].bitfield.disp32s = 1;
if ((i.index_reg->reg_flags & RegRex) != 0)
i.rex |= REX_X;
}
i.types[this_operand].bitfield.disp8 = 1;
/* Check if this is a displacement only operand. */
- bigdisp = i.types[this_operand];
- bigdisp.bitfield.disp8 = 0;
- bigdisp.bitfield.disp16 = 0;
- bigdisp.bitfield.disp32 = 0;
- bigdisp.bitfield.disp32s = 0;
- bigdisp.bitfield.disp64 = 0;
+ bigdisp = operand_type_and_not (i.types[this_operand], anydisp);
if (operand_type_all_zero (&bigdisp))
i.types[this_operand] = operand_type_and (i.types[this_operand],
types);