nouveau: Very rough cut at gallium winsys + nv40 pipe driver.

diff --git a/src/mesa/drivers/dri/nouveau_winsys/Makefile b/src/mesa/drivers/dri/nouveau_winsys/Makefile
new file mode 100644 (file)
index 0000000..97b8615
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/Makefile
@@ -0,0 +1,38 @@
+
+TOP = ../../../../..
+include $(TOP)/configs/current
+
+LIBNAME = nouveau_dri.so
+
+MINIGLX_SOURCES =
+
+PIPE_DRIVERS = \
+       $(TOP)/src/mesa/pipe/softpipe/libsoftpipe.a \
+       $(TOP)/src/mesa/pipe/nv40/libnv40.a
+
+DRIVER_SOURCES = \
+       nouveau_bo.c \
+       nouveau_channel.c \
+       nouveau_context.c \
+       nouveau_device.c \
+       nouveau_dma.c \
+       nouveau_grobj.c \
+       nouveau_lock.c \
+       nouveau_notifier.c \
+       nouveau_screen.c \
+       nouveau_swapbuffers.c \
+       nouveau_winsys.c \
+       nouveau_winsys_pipe.c \
+       nouveau_winsys_softpipe.c \
+       nv04_region.c \
+       nv50_region.c
+
+C_SOURCES = \
+       $(COMMON_SOURCES) \
+       $(DRIVER_SOURCES)
+
+ASM_SOURCES = 
+
+include ../Makefile.template
+
+symlinks:

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_bo.c b/src/mesa/drivers/dri/nouveau_winsys/nouveau_bo.c
new file mode 100644 (file)
index 0000000..3b508cf
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_bo.c
@@ -0,0 +1,347 @@
+/*
+ * Copyright 2007 Nouveau Project
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <errno.h>
+
+#include "nouveau_drmif.h"
+#include "nouveau_dma.h"
+#include "nouveau_local.h"
+
+int
+nouveau_bo_init(struct nouveau_device *userdev)
+{
+       struct nouveau_device_priv *nv = nouveau_device(userdev);
+       struct nouveau_channel *chan;
+       int ret;
+
+       if ((ret = nouveau_channel_alloc(userdev, 0x80000001, 0x80000002,
+                                        &nv->bufmgr.channel)))
+               return ret;
+       chan = nv->bufmgr.channel;
+
+       if ((ret = nouveau_notifier_alloc(nv->bufmgr.channel, 0x80000003, 1,
+                                         &nv->bufmgr.notify)))
+               return ret;
+
+       if ((ret = nouveau_grobj_alloc(nv->bufmgr.channel, 0x80000004, 0x39,
+                                      &nv->bufmgr.m2mf)))
+               return ret;
+
+       nouveau_notifier_reset(nv->bufmgr.notify, 0);
+       BEGIN_RING_CH(chan, nv->bufmgr.m2mf, 0x180, 1);
+       OUT_RING_CH  (chan, nv->bufmgr.notify->handle);
+       BEGIN_RING_CH(chan, nv->bufmgr.m2mf, 0x104, 1);
+       OUT_RING_CH  (chan, 0);
+       BEGIN_RING_CH(chan, nv->bufmgr.m2mf, 0x100, 1);
+       OUT_RING_CH  (chan, 0);
+       FIRE_RING_CH (chan);
+       if ((ret = nouveau_notifier_wait_status(nv->bufmgr.notify, 0, 0, 2000)))
+               return ret;
+
+       return 0;
+}
+
+void
+nouveau_bo_takedown(struct nouveau_device *userdev)
+{
+       struct nouveau_device_priv *nv = nouveau_device(userdev);
+
+       nouveau_notifier_free(&nv->bufmgr.notify);
+       nouveau_grobj_free(&nv->bufmgr.m2mf);
+       nouveau_channel_free(&nv->bufmgr.channel);
+}
+
+static int
+nouveau_bo_realloc_gpu(struct nouveau_bo_priv *bo, uint32_t flags, int size)
+{
+       struct nouveau_device_priv *nv = nouveau_device(bo->base.device);
+       int ret;
+
+       if (bo->drm.size && bo->drm.size != size) {
+               struct drm_nouveau_mem_free f;
+
+               if (bo->map) {
+                       drmUnmap(bo->map, bo->drm.size);
+                       bo->map = NULL;
+               }
+
+               f.flags = bo->drm.flags;
+               f.offset = bo->drm.offset;
+               drmCommandWrite(nv->fd, DRM_NOUVEAU_MEM_FREE, &f, sizeof(f));
+
+               bo->drm.size = 0;
+       }
+
+       if (size && !bo->drm.size) {
+               if (flags) {
+                       bo->drm.flags = 0;
+                       if (flags & NOUVEAU_BO_VRAM)
+                               bo->drm.flags |= NOUVEAU_MEM_FB;
+                       if (flags & NOUVEAU_BO_GART)
+                               bo->drm.flags |= (NOUVEAU_MEM_AGP |
+                                                 NOUVEAU_MEM_PCI);
+                       bo->drm.flags |= NOUVEAU_MEM_MAPPED;
+               }
+
+               bo->drm.size = size;
+               
+               ret = drmCommandWriteRead(nv->fd, DRM_NOUVEAU_MEM_ALLOC,
+                                         &bo->drm, sizeof(bo->drm));
+               if (ret) {
+                       free(bo);
+                       return ret;
+               }
+
+               ret = drmMap(nv->fd, bo->drm.map_handle, bo->drm.size,
+                            &bo->map);
+               if (ret) {
+                       bo->map = NULL;
+                       nouveau_bo_del((void *)&bo);
+                       return ret;
+               }
+       }
+
+       return 0;
+}
+
+int
+nouveau_bo_new(struct nouveau_device *userdev, uint32_t flags, int align,
+              int size, struct nouveau_bo **userbo)
+{
+       struct nouveau_bo_priv *bo;
+       int ret;
+
+       if (!userdev || !userbo || *userbo)
+               return -EINVAL;
+
+       bo = calloc(1, sizeof(*bo));
+       if (!bo)
+               return -ENOMEM;
+       bo->base.device = userdev;
+       bo->drm.alignment = align;
+
+       if (flags & NOUVEAU_BO_PIN) {
+               ret = nouveau_bo_realloc_gpu(bo, flags, size);
+               if (ret) {
+                       free(bo);
+                       return ret;
+               }       
+       } else {
+               bo->sysmem = malloc(size);
+               if (!bo->sysmem) {
+                       free(bo);
+                       return -ENOMEM;
+               }
+       }
+
+       bo->base.size = size;
+       bo->base.offset = bo->drm.offset;
+       bo->base.handle = (unsigned long)bo;
+       bo->refcount = 1;
+       *userbo = &bo->base;
+       return 0;
+}
+
+int
+nouveau_bo_user(struct nouveau_device *userdev, void *ptr, int size,
+               struct nouveau_bo **userbo)
+{
+       struct nouveau_bo_priv *bo;
+
+       if (!userdev || !userbo || *userbo)
+               return -EINVAL;
+
+       bo = calloc(1, sizeof(*bo));
+       if (!bo)
+               return -ENOMEM;
+       bo->base.device = userdev;
+       
+       bo->sysmem = ptr;
+       bo->user = 1;
+
+       bo->base.size = size;
+       bo->base.offset = bo->drm.offset;
+       bo->base.handle = (unsigned long)bo;
+       bo->refcount = 1;
+       *userbo = &bo->base;
+       return 0;
+}
+
+int
+nouveau_bo_ref(struct nouveau_device *userdev, uint64_t handle,
+              struct nouveau_bo **userbo)
+{
+       struct nouveau_bo_priv *bo = (void *)(unsigned long)handle;
+
+       if (!userdev || !userbo || *userbo)
+               return -EINVAL;
+
+       bo->refcount++;
+       *userbo = &bo->base;
+       return 0;
+}
+
+int
+nouveau_bo_resize(struct nouveau_bo *userbo, int size)
+{
+       struct nouveau_bo_priv *bo = nouveau_bo(userbo);
+       int ret;
+
+       if (!bo || bo->user)
+               return -EINVAL;
+
+       if (bo->sysmem) {
+               bo->sysmem = realloc(bo->sysmem, size);
+               if (!bo->sysmem)
+                       return -ENOMEM;
+       } else {
+               ret = nouveau_bo_realloc_gpu(bo, 0, size);
+               if (ret)
+                       return ret;
+       }
+
+       bo->base.size = size;
+       return 0;
+}
+
+void
+nouveau_bo_del(struct nouveau_bo **userbo)
+{
+       struct nouveau_bo_priv *bo;
+
+       if (!userbo || !*userbo)
+               return;
+       bo = nouveau_bo(*userbo);
+       *userbo = NULL;
+
+       if (--bo->refcount)
+               return;
+
+       nouveau_bo_realloc_gpu(bo, 0, 0);
+       if (bo->sysmem && !bo->user)
+               free(bo->sysmem);
+       free(bo);
+}
+
+int
+nouveau_bo_map(struct nouveau_bo *userbo, uint32_t flags)
+{
+       struct nouveau_bo_priv *bo = nouveau_bo(userbo);
+
+       if (!bo)
+               return -EINVAL;
+
+       if (bo->sysmem)
+               userbo->map = bo->sysmem;
+       else
+               userbo->map = bo->map;
+       return 0;
+}
+
+void
+nouveau_bo_unmap(struct nouveau_bo *userbo)
+{
+       userbo->map = NULL;
+}
+
+void
+nouveau_bo_emit_reloc(struct nouveau_channel *userchan, void *ptr,
+                     struct nouveau_bo *userbo, uint32_t data, uint32_t flags,
+                     uint32_t vor, uint32_t tor)
+{
+       struct nouveau_channel_priv *chan = nouveau_channel(userchan);
+       struct nouveau_bo_priv *bo = nouveau_bo(userbo);
+       struct nouveau_bo_reloc *r;
+       int i, on_list = 0;
+
+       for (i = 0; i < chan->nr_buffers; i++) {
+               if (chan->buffers[i].bo == bo) {
+                       on_list = 1;
+                       break;
+               }
+       }
+
+       if (i >= 128)
+               return;
+
+       if (on_list) {
+               chan->buffers[i].flags &= (flags | NOUVEAU_BO_RDWR);
+               chan->buffers[i].flags |= (flags & NOUVEAU_BO_RDWR);
+       } else {
+               chan->buffers[i].bo = bo;
+               chan->buffers[i].flags = flags;
+               chan->nr_buffers++;
+       }
+
+       if (chan->num_relocs >= chan->max_relocs)
+               FIRE_RING_CH(userchan);
+       r = &chan->relocs[chan->num_relocs++];
+
+       r->ptr = ptr;
+       r->bo = bo;
+       r->data = data;
+       r->flags = flags;
+       r->vor = vor;
+       r->tor = tor;
+}
+
+static int
+nouveau_bo_upload(struct nouveau_bo_priv *bo)
+{
+       memcpy(bo->map, bo->sysmem, bo->drm.size);
+       return 0;
+}
+
+void
+nouveau_bo_validate(struct nouveau_channel *userchan)
+{
+       struct nouveau_channel_priv *chan = nouveau_channel(userchan);
+       int i;
+
+       for (i = 0; i < chan->nr_buffers; i++) {
+               struct nouveau_bo_priv *bo = chan->buffers[i].bo;
+
+               if (!bo->drm.size) {
+                       nouveau_bo_realloc_gpu(bo, chan->buffers[i].flags,
+                                              bo->base.size);
+                       nouveau_bo_upload(bo);
+               } else
+               if (bo->user || bo->base.map)
+                       nouveau_bo_upload(bo);
+
+               if (!bo->user && !bo->base.map) {
+                       free(bo->sysmem);
+                       bo->sysmem = NULL;
+               }
+
+
+               bo->base.offset = bo->drm.offset;
+               if (bo->drm.flags & NOUVEAU_MEM_AGP)
+                       bo->base.flags = NOUVEAU_BO_GART;
+               else
+                       bo->base.flags = NOUVEAU_BO_VRAM;
+       }
+       chan->nr_buffers = 0;
+}
+

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_channel.c b/src/mesa/drivers/dri/nouveau_winsys/nouveau_channel.c
new file mode 100644 (file)
index 0000000..ef41020
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_channel.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright 2007 Nouveau Project
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+
+#include "nouveau_drmif.h"
+#include "nouveau_dma.h"
+
+int
+nouveau_channel_alloc(struct nouveau_device *userdev, uint32_t fb_ctxdma,
+                     uint32_t tt_ctxdma, struct nouveau_channel **userchan)
+{
+       struct nouveau_device_priv *nv = nouveau_device(userdev);
+       struct nouveau_channel_priv *chan;
+       int ret;
+
+       if (!nv || !userchan || *userchan)
+           return -EINVAL;
+
+       chan = calloc(1, sizeof(*chan));
+       if (!chan)
+               return -ENOMEM;
+       chan->base.device = userdev;
+
+       chan->drm.fb_ctxdma_handle = fb_ctxdma;
+       chan->drm.tt_ctxdma_handle = tt_ctxdma;
+       ret = drmCommandWriteRead(nv->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
+                                 &chan->drm, sizeof(chan->drm));
+       if (ret) {
+               free(chan);
+               return ret;
+       }
+
+       chan->base.id = chan->drm.channel;
+       if (nouveau_grobj_ref(&chan->base, chan->drm.fb_ctxdma_handle,
+                             &chan->base.vram) ||
+           nouveau_grobj_ref(&chan->base, chan->drm.tt_ctxdma_handle,
+                             &chan->base.gart)) {
+               nouveau_channel_free((void *)&chan);
+               return -EINVAL;
+       }
+
+       ret = drmMap(nv->fd, chan->drm.ctrl, chan->drm.ctrl_size,
+                    (void*)&chan->user);
+       if (ret) {
+               nouveau_channel_free((void *)&chan);
+               return ret;
+       }
+       chan->put     = &chan->user[0x40/4];
+       chan->get     = &chan->user[0x44/4];
+       chan->ref_cnt = &chan->user[0x48/4];
+
+       ret = drmMap(nv->fd, chan->drm.notifier, chan->drm.notifier_size,
+                    (drmAddressPtr)&chan->notifier_block);
+       if (ret) {
+               nouveau_channel_free((void *)&chan);
+               return ret;
+       }
+
+       ret = drmMap(nv->fd, chan->drm.cmdbuf, chan->drm.cmdbuf_size,
+                    (void*)&chan->pushbuf);
+       if (ret) {
+               nouveau_channel_free((void *)&chan);
+               return ret;
+       }
+
+       chan->max_relocs = chan->drm.cmdbuf_size / 4;
+       chan->num_relocs = 0;
+       chan->relocs =
+               malloc(sizeof(struct nouveau_bo_reloc) * chan->max_relocs);
+
+       nouveau_dma_channel_init(&chan->base);
+
+       *userchan = &chan->base;
+       return 0;
+}
+
+void
+nouveau_channel_free(struct nouveau_channel **userchan)
+{
+       struct nouveau_channel_priv *chan;
+       
+       if (!userchan)
+               return;
+       chan = nouveau_channel(*userchan);
+
+       if (chan) {
+               struct nouveau_device_priv *nv;
+               struct drm_nouveau_channel_free cf;
+
+               nv = nouveau_device((*userchan)->device);
+               *userchan = NULL;
+
+               FIRE_RING_CH(&chan->base);
+
+               if (chan->relocs)
+                       free(chan->relocs);
+
+               nouveau_grobj_free(&chan->base.vram);
+               nouveau_grobj_free(&chan->base.gart);
+
+               cf.channel = chan->drm.channel;
+               drmCommandWrite(nv->fd, DRM_NOUVEAU_CHANNEL_FREE,
+                               &cf, sizeof(cf));
+               free(chan);
+       }
+}
+
+

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_context.c b/src/mesa/drivers/dri/nouveau_winsys/nouveau_context.c
new file mode 100644 (file)
index 0000000..584d236
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_context.c
@@ -0,0 +1,228 @@
+#include "glheader.h"
+#include "context.h"
+#include "extensions.h"
+
+#include "tnl/tnl.h"
+#include "tnl/t_pipeline.h"
+#include "tnl/t_vertex.h"
+
+#include "drivers/common/driverfuncs.h"
+
+#include "drirenderbuffer.h"
+
+#include "state_tracker/st_public.h"
+#include "state_tracker/st_context.h"
+
+#include "pipe/p_defines.h"
+#include "pipe/p_context.h"
+
+#include "nouveau_context.h"
+#include "nouveau_dri.h"
+#include "nouveau_local.h"
+#include "nouveau_screen.h"
+#include "nouveau_winsys_pipe.h"
+
+#define need_GL_ARB_fragment_program
+#define need_GL_ARB_multisample
+#define need_GL_ARB_occlusion_query
+#define need_GL_ARB_texture_compression
+#define need_GL_ARB_vertex_program
+#define need_GL_ARB_vertex_buffer_object
+#define need_GL_EXT_compiled_vertex_array
+#define need_GL_EXT_fog_coord
+#define need_GL_EXT_secondary_color
+#define need_GL_EXT_framebuffer_object
+#include "extension_helper.h"
+
+const struct dri_extension common_extensions[] =
+{
+       { NULL, 0 }
+};
+
+const struct dri_extension nv40_extensions[] =
+{
+       { "GL_ARB_fragment_program", NULL },
+       { "GL_ARB_multisample", GL_ARB_multisample_functions },
+       { "GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions },
+       { "GL_ARB_texture_border_clamp", NULL },
+       { "GL_ARB_texture_compression", GL_ARB_texture_compression_functions },
+       { "GL_ARB_texture_cube_map", NULL },
+       { "GL_ARB_texture_env_add", NULL },
+       { "GL_ARB_texture_env_combine", NULL },
+       { "GL_ARB_texture_env_crossbar", NULL },
+       { "GL_ARB_texture_env_dot3", NULL },
+       { "GL_ARB_texture_mirrored_repeat", NULL },
+       { "GL_ARB_texture_non_power_of_two", NULL },
+       { "GL_ARB_vertex_program", GL_ARB_vertex_program_functions },
+       { "GL_ARB_vertex_buffer_object", GL_ARB_vertex_buffer_object_functions },
+       { "GL_ATI_texture_env_combine3", NULL },
+       { "GL_EXT_compiled_vertex_array", GL_EXT_compiled_vertex_array_functions },
+       { "GL_EXT_fog_coord", GL_EXT_fog_coord_functions },
+       { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
+       { "GL_EXT_secondary_color", GL_EXT_secondary_color_functions },
+       { "GL_EXT_texture_edge_clamp", NULL },
+       { "GL_EXT_texture_env_add", NULL },
+       { "GL_EXT_texture_env_combine", NULL },
+       { "GL_EXT_texture_env_dot3", NULL },
+       { "GL_EXT_texture_mirror_clamp", NULL },
+       { "GL_NV_texture_rectangle", NULL },
+       { NULL, 0 }
+};
+
+#ifdef DEBUG
+static const struct dri_debug_control debug_control[] = {
+       { "bo", DEBUG_BO },
+       { NULL, 0 }
+};
+int __nouveau_debug = 0;
+#endif
+
+GLboolean
+nouveau_context_create(const __GLcontextModes *glVis,
+                      __DRIcontextPrivate *driContextPriv,
+                      void *sharedContextPrivate)
+{
+       __DRIscreenPrivate *driScrnPriv = driContextPriv->driScreenPriv;
+       struct nouveau_screen  *nv_screen = driScrnPriv->private;
+       struct nouveau_context *nv = CALLOC_STRUCT(nouveau_context);
+       struct nouveau_device_priv *nvdev;
+       struct pipe_context *pipe = NULL;
+       struct st_context *st_share = NULL;
+       int ret;
+
+       if (sharedContextPrivate) {
+               st_share = ((struct nouveau_context *)sharedContextPrivate)->st;
+       }
+
+       if ((ret = nouveau_device_get_param(nv_screen->device,
+                                           NOUVEAU_GETPARAM_CHIPSET_ID,
+                                           &nv->chipset))) {
+               NOUVEAU_ERR("Error determining chipset id: %d\n", ret);
+               return GL_FALSE;
+       }
+
+       if ((ret = nouveau_channel_alloc(nv_screen->device,
+                                        0x8003d001, 0x8003d002,
+                                        &nv->channel))) {
+               NOUVEAU_ERR("Error creating GPU channel: %d\n", ret);
+               return GL_FALSE;
+       }
+
+       driContextPriv->driverPrivate = (void *)nv;
+       nv->nv_screen  = nv_screen;
+       nv->dri_screen = driScrnPriv;
+
+       nvdev = nouveau_device(nv_screen->device);
+       nvdev->ctx  = driContextPriv->hHWContext;
+       nvdev->lock = (drmLock *)&driScrnPriv->pSAREA->lock;
+
+       driParseConfigFiles(&nv->dri_option_cache, &nv_screen->option_cache,
+                           nv->dri_screen->myNum, "nouveau");
+#ifdef DEBUG
+       __nouveau_debug = driParseDebugString(getenv("NOUVEAU_DEBUG"),
+                                             debug_control);
+#endif
+
+       if ((ret = nouveau_grobj_alloc(nv->channel, 0x00000000, 0x30,
+                                      &nv->NvNull))) {
+               NOUVEAU_ERR("Error creating NULL object: %d\n", ret);
+               return GL_FALSE;
+       }
+       nv->next_handle = 0x80000000;
+
+       if ((ret = nouveau_notifier_alloc(nv->channel, nv->next_handle++, 1,
+                                         &nv->sync_notifier))) {
+               NOUVEAU_ERR("Error creating channel sync notifier: %d\n", ret);
+               return GL_FALSE;
+       }
+
+       if (nv->chipset < 0x50)
+               ret = nouveau_region_init_nv04(nv);
+       else
+               ret = nouveau_region_init_nv50(nv);
+       if (ret) {
+               return GL_FALSE;
+       }
+
+       if (!getenv("NOUVEAU_FORCE_SOFTPIPE")) {
+               pipe = nouveau_pipe_create(nv);
+               if (!pipe)
+                       NOUVEAU_ERR("Couldn't create hw pipe\n");
+       }
+
+       if (!pipe) {
+               NOUVEAU_MSG("Using softpipe\n");
+               pipe = nouveau_create_softpipe(nv);
+               if (!pipe) {
+                       NOUVEAU_ERR("Error creating pipe, bailing\n");
+                       return GL_FALSE;
+               }
+       }
+
+       pipe->priv = nv;
+       nv->st = st_create_context(pipe, glVis, st_share);
+       return GL_TRUE;
+}
+
+void
+nouveau_context_destroy(__DRIcontextPrivate *driContextPriv)
+{
+       struct nouveau_context *nv = driContextPriv->driverPrivate;
+
+       assert(nv);
+
+       st_flush(nv->st, PIPE_FLUSH_WAIT);
+       st_destroy_context(nv->st);
+
+       nouveau_grobj_free(&nv->NvCtxSurf2D);
+       nouveau_grobj_free(&nv->NvImageBlit);
+       nouveau_channel_free(&nv->channel);
+
+       free(nv);
+}
+
+GLboolean
+nouveau_context_bind(__DRIcontextPrivate *driContextPriv,
+                    __DRIdrawablePrivate *driDrawPriv,
+                    __DRIdrawablePrivate *driReadPriv)
+{
+       struct nouveau_context *nv;
+       struct nouveau_framebuffer *draw, *read;
+
+       if (!driContextPriv) {
+               st_make_current(NULL, NULL, NULL);
+               return GL_TRUE;
+       }
+
+       nv = driContextPriv->driverPrivate;
+       draw = driDrawPriv->driverPrivate;
+       read = driReadPriv->driverPrivate;
+
+       st_make_current(nv->st, draw->stfb, read->stfb);
+
+       if ((nv->dri_drawable != driDrawPriv) ||
+           (nv->last_stamp != driDrawPriv->lastStamp)) {
+               nv->dri_drawable = driDrawPriv;
+               st_resize_framebuffer(draw->stfb, driDrawPriv->w,
+                                     driDrawPriv->h);
+               nv->last_stamp = driDrawPriv->lastStamp;
+       }
+
+       if (driDrawPriv != driReadPriv) {
+               st_resize_framebuffer(read->stfb, driReadPriv->w,
+                                     driReadPriv->h);
+       }
+
+       return GL_TRUE;
+}
+
+GLboolean
+nouveau_context_unbind(__DRIcontextPrivate *driContextPriv)
+{
+       struct nouveau_context *nv = driContextPriv->driverPrivate;
+       (void)nv;
+
+       st_flush(nv->st, 0);
+       return GL_TRUE;
+}
+

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_context.h b/src/mesa/drivers/dri/nouveau_winsys/nouveau_context.h
new file mode 100644 (file)
index 0000000..cd04b08
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_context.h
@@ -0,0 +1,104 @@
+#ifndef __NOUVEAU_CONTEXT_H__
+#define __NOUVEAU_CONTEXT_H__
+
+#include "glheader.h"
+#include "context.h"
+
+#include "dri_util.h"
+#include "xmlconfig.h"
+
+#include "pipe/nouveau/nouveau_winsys.h"
+#include "nouveau_device.h"
+#include "nouveau_drmif.h"
+#include "nouveau_dma.h"
+
+struct nouveau_framebuffer {
+       struct st_framebuffer *stfb;
+};
+
+struct nouveau_context {
+       struct st_context *st;
+
+       /* Misc HW info */
+       uint64_t chipset;
+
+       /* DRI stuff */
+       __DRIscreenPrivate    *dri_screen;
+       __DRIdrawablePrivate  *dri_drawable;
+       unsigned int           last_stamp;
+       driOptionCache         dri_option_cache;
+       drm_context_t          drm_context;
+       drmLock                drm_lock;
+       GLboolean              locked;
+       struct nouveau_screen *nv_screen;
+
+       /* Bufmgr */
+       struct {
+               struct nouveau_channel *channel;
+               struct nouveau_notifier *notify;
+               struct nouveau_grobj *m2mf;
+               uint32_t m2mf_src_ctxdma;
+               uint32_t m2mf_dst_ctxdma;
+               uint32_t next_sequence;
+       } bo;
+
+       /* Relocations */
+       struct nouveau_bo *reloc_head;
+
+       /* Hardware context */
+       struct nouveau_channel  *channel;
+       struct nouveau_notifier *sync_notifier;
+       struct nouveau_grobj    *NvNull;
+       struct nouveau_grobj    *NvCtxSurf2D;
+       struct nouveau_grobj    *NvImageBlit;
+       struct nouveau_grobj    *NvGdiRect;
+       uint32_t                 next_handle;
+       uint32_t                 next_sequence;
+
+       /* pipe_region accel */
+       int (*region_display)(void);
+       int (*region_copy)(struct nouveau_context *, struct pipe_region *,
+                          unsigned, unsigned, unsigned, struct pipe_region *,
+                          unsigned, unsigned, unsigned, unsigned, unsigned);
+       int (*region_fill)(struct nouveau_context *, struct pipe_region *,
+                          unsigned, unsigned, unsigned, unsigned, unsigned,
+                          unsigned);
+       int (*region_data)(struct nouveau_context *, struct pipe_region *,
+                          unsigned, unsigned, unsigned, const void *,
+                          unsigned, unsigned, unsigned, unsigned, unsigned);
+};
+
+static INLINE struct nouveau_context *
+nouveau_context(GLcontext *ctx)
+{
+       return (struct nouveau_context *)ctx;
+}
+
+extern GLboolean nouveau_context_create(const __GLcontextModes *,
+                                       __DRIcontextPrivate *, void *);
+extern void nouveau_context_destroy(__DRIcontextPrivate *);
+extern GLboolean nouveau_context_bind(__DRIcontextPrivate *,
+                                     __DRIdrawablePrivate *draw,
+                                     __DRIdrawablePrivate *read);
+extern GLboolean nouveau_context_unbind(__DRIcontextPrivate *);
+
+#ifdef DEBUG
+extern int __nouveau_debug;
+
+#define DEBUG_BO (1 << 0)
+
+#define DBG(flag, ...) do {                   \
+       if (__nouveau_debug & (DEBUG_##flag)) \
+               NOUVEAU_ERR(__VA_ARGS__);     \
+} while(0)
+#else
+#define DBG(flag, ...)
+#endif
+
+extern void LOCK_HARDWARE(struct nouveau_context *);
+extern void UNLOCK_HARDWARE(struct nouveau_context *);
+
+extern int nouveau_region_init_nv04(struct nouveau_context *);
+extern int nouveau_region_init_nv50(struct nouveau_context *);
+
+#endif

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_device.c b/src/mesa/drivers/dri/nouveau_winsys/nouveau_device.c
new file mode 100644 (file)
index 0000000..a3f5513
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_device.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright 2007 Nouveau Project
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <errno.h>
+
+#include "nouveau_drmif.h"
+
+int
+nouveau_device_open_existing(struct nouveau_device **userdev, int close,
+                            int fd, drm_context_t ctx)
+{
+       struct nouveau_device_priv *nv;
+       int ret;
+
+       if (!userdev || *userdev)
+           return -EINVAL;
+
+       nv = calloc(1, sizeof(*nv));
+       if (!nv)
+           return -ENOMEM;
+       nv->fd = fd;
+       nv->ctx = ctx;
+       nv->needs_close = close;
+
+       drmCommandNone(nv->fd, DRM_NOUVEAU_CARD_INIT);
+
+       if ((ret = nouveau_bo_init(&nv->base))) {
+               nouveau_device_close((void *)&nv);
+               return ret;
+       }
+
+       *userdev = &nv->base;
+       return 0;
+}
+
+int
+nouveau_device_open(struct nouveau_device **userdev, const char *busid)
+{
+       drm_context_t ctx;
+       int fd, ret;
+
+       if (!userdev || *userdev)
+               return -EINVAL;
+
+       fd = drmOpen("nouveau", busid);
+       if (fd < 0)
+               return -EINVAL;
+
+       ret = drmCreateContext(fd, &ctx);
+       if (ret) {
+               drmClose(fd);
+               return ret;
+       }
+
+       ret = nouveau_device_open_existing(userdev, 1, fd, ctx);
+       if (ret) {
+           drmDestroyContext(fd, ctx);
+           drmClose(fd);
+           return ret;
+       }
+
+       return 0;
+}
+
+void
+nouveau_device_close(struct nouveau_device **userdev)
+{
+       struct nouveau_device_priv *nv;
+
+       if (userdev || !*userdev)
+               return;
+       nv = (struct nouveau_device_priv *)*userdev;
+       *userdev = NULL;
+
+       nouveau_bo_takedown(&nv->base);
+
+       if (nv->needs_close) {
+               drmDestroyContext(nv->fd, nv->ctx);
+               drmClose(nv->fd);
+       }
+       free(nv);
+}
+
+int
+nouveau_device_get_param(struct nouveau_device *userdev,
+                        uint64_t param, uint64_t *value)
+{
+       struct nouveau_device_priv *nv = (struct nouveau_device_priv *)userdev;
+       struct drm_nouveau_getparam g;
+       int ret;
+
+       if (!nv || !value)
+               return -EINVAL;
+
+       g.param = param;
+       ret = drmCommandWriteRead(nv->fd, DRM_NOUVEAU_GETPARAM, &g, sizeof(g));
+       if (ret)
+               return ret;
+
+       *value = g.value;
+       return 0;
+}
+
+int
+nouveau_device_set_param(struct nouveau_device *userdev,
+                        uint64_t param, uint64_t value)
+{
+       struct nouveau_device_priv *nv = (struct nouveau_device_priv *)userdev;
+       struct drm_nouveau_setparam s;
+       int ret;
+
+       if (!nv)
+               return -EINVAL;
+
+       s.param = param;
+       s.value = value;
+       ret = drmCommandWriteRead(nv->fd, DRM_NOUVEAU_SETPARAM, &s, sizeof(s));
+       if (ret)
+               return ret;
+
+       return 0;
+}
+

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_device.h b/src/mesa/drivers/dri/nouveau_winsys/nouveau_device.h
new file mode 100644 (file)
index 0000000..744a89f
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_device.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2007 Nouveau Project
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef __NOUVEAU_DEVICE_H__
+#define __NOUVEAU_DEVICE_H__
+
+struct nouveau_device {
+};
+
+#endif

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_dma.c b/src/mesa/drivers/dri/nouveau_winsys/nouveau_dma.c
new file mode 100644 (file)
index 0000000..6e123c4
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_dma.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright 2007 Nouveau Project
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <stdint.h>
+#include <assert.h>
+#include <errno.h>
+
+#include "nouveau_drmif.h"
+#include "nouveau_dma.h"
+#include "nouveau_local.h"
+
+#define READ_GET(ch) ((*(ch)->get - (ch)->dma.base) >> 2)
+#define WRITE_PUT(ch, val) do {                       \
+       volatile int dum;                             \
+       NOUVEAU_DMA_BARRIER;                          \
+       dum=READ_GET(ch);                             \
+       *(ch)->put = (((val) << 2) + (ch)->dma.base); \
+       NOUVEAU_DMA_BARRIER;                          \
+} while(0)
+
+void
+nouveau_dma_channel_init(struct nouveau_channel *userchan)
+{
+       struct nouveau_channel_priv *chan = nouveau_channel(userchan);
+       int i;
+
+       chan->dma.base = chan->drm.put_base;
+       chan->dma.cur  = chan->dma.put = RING_SKIPS;
+       chan->dma.max  = (chan->drm.cmdbuf_size >> 2) - 2;
+       chan->dma.free = chan->dma.max - chan->dma.cur;
+
+       for (i = 0; i < RING_SKIPS; i++)
+               chan->pushbuf[i] = 0x00000000;
+}
+
+#define CHECK_TIMEOUT() do {                                                   \
+       if ((NOUVEAU_TIME_MSEC() - t_start) > NOUVEAU_DMA_TIMEOUT)             \
+               return - EBUSY;                                                \
+} while(0)
+
+int
+nouveau_dma_wait(struct nouveau_channel *userchan, int size)
+{
+       struct nouveau_channel_priv *chan = nouveau_channel(userchan);
+       uint32_t get, t_start;
+
+       FIRE_RING_CH(userchan);
+
+       t_start = NOUVEAU_TIME_MSEC();
+       while (chan->dma.free < size) {
+               get = READ_GET(chan);
+
+               if (chan->dma.put >= get) {
+                       chan->dma.free = chan->dma.max - chan->dma.cur;
+
+                       if (chan->dma.free < size) {
+#ifdef NOUVEAU_DMA_DEBUG
+                               chan->dma.push_free = 1;
+#endif
+                               OUT_RING_CH(userchan,
+                                           0x20000000 | chan->dma.base);
+                               if (get <= RING_SKIPS) {
+                                       /*corner case - will be idle*/
+                                       if (chan->dma.put <= RING_SKIPS)
+                                               WRITE_PUT(chan, RING_SKIPS + 1);
+
+                                       do {
+                                               CHECK_TIMEOUT();
+                                               get = READ_GET(chan);
+                                       } while (get <= RING_SKIPS);
+                               }
+
+                               WRITE_PUT(chan, RING_SKIPS);
+                               chan->dma.cur  = chan->dma.put = RING_SKIPS;
+                               chan->dma.free = get - (RING_SKIPS + 1);
+                       }
+               } else {
+                       chan->dma.free = get - chan->dma.cur - 1;
+               }
+
+               CHECK_TIMEOUT();
+       }
+
+       return 0;
+}
+
+#ifdef NOUVEAU_DMA_SUBCHAN_LRU
+void
+nouveau_dma_subc_bind(struct nouveau_grobj *grobj)
+{
+       struct nouveau_channel_priv *chan = nouveau_channel(grobj->channel);
+       int subc = -1, i;
+       
+       for (i = 0; i < 8; i++) {
+               if (chan->subchannel[i].grobj &&
+                   chan->subchannel[i].grobj->bound == 
+                   NOUVEAU_GROBJ_EXPLICIT_BIND)
+                       continue;
+               if (chan->subchannel[i].seq < chan->subchannel[subc].seq)
+                       subc = i;
+       }
+       assert(subc >= 0);
+
+       if (chan->subchannel[subc].grobj)
+               chan->subchannel[subc].grobj->bound = 0;
+       chan->subchannel[subc].grobj = grobj;
+       grobj->subc  = subc;
+       grobj->bound = NOUVEAU_GROBJ_BOUND;
+
+       BEGIN_RING_CH(grobj->channel, grobj, 0, 1);
+       nouveau_dma_out  (grobj->channel, grobj->handle);
+}
+#endif
+
+void
+nouveau_dma_kickoff(struct nouveau_channel *userchan)
+{
+       struct nouveau_channel_priv *chan = nouveau_channel(userchan);
+       uint32_t put_offset;
+       int i;
+
+       if (chan->dma.cur == chan->dma.put)
+               return;
+
+       if (chan->num_relocs) {
+               nouveau_bo_validate(userchan);
+               
+               for (i = 0; i < chan->num_relocs; i++) {
+                       struct nouveau_bo_reloc *r = &chan->relocs[i];
+                       uint32_t push;
+
+                       if (r->flags & NOUVEAU_BO_LOW) {
+                               push = r->bo->base.offset + r->data;
+                       } else
+                       if (r->flags & NOUVEAU_BO_HIGH) {
+                               push = (r->bo->base.offset + r->data) >> 32;
+                       } else {
+                               push = r->data;
+                       }
+
+                       if (r->flags & NOUVEAU_BO_OR) {
+                               if (r->bo->base.flags & NOUVEAU_BO_VRAM)
+                                       push |= r->vor;
+                               else
+                                       push |= r->tor;
+                       }
+
+                       *r->ptr = push;
+               }
+
+               chan->num_relocs = 0;
+       }
+
+#ifdef NOUVEAU_DMA_DEBUG
+       if (chan->dma.push_free) {
+               NOUVEAU_ERR("Packet incomplete: %d left\n", chan->dma.push_free);
+               return;
+       }
+#endif
+
+#ifdef NOUVEAU_DMA_DUMP_POSTRELOC_PUSHBUF
+       for (i = chan->dma.put; i < chan->dma.cur; i++)
+               NOUVEAU_MSG("0x%08x\n", chan->pushbuf[i]);
+#endif
+
+       put_offset = (chan->dma.cur << 2) + chan->dma.base;
+#ifdef NOUVEAU_DMA_TRACE
+       NOUVEAU_MSG("FIRE_RING %d/0x%08x\n", chan->drm.channel, put_offset);
+#endif
+       chan->dma.put  = chan->dma.cur;
+       NOUVEAU_DMA_BARRIER;
+       *chan->put     = put_offset;
+       NOUVEAU_DMA_BARRIER;
+}

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_dma.h b/src/mesa/drivers/dri/nouveau_winsys/nouveau_dma.h
new file mode 100644 (file)
index 0000000..927841c
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_dma.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright 2007 Nouveau Project
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef __NOUVEAU_DMA_H__
+#define __NOUVEAU_DMA_H__
+
+#include <string.h>
+#include "nouveau_drmif.h"
+#include "nouveau_local.h"
+
+#define RING_SKIPS 8
+
+extern int  nouveau_dma_wait(struct nouveau_channel *chan, int size);
+extern void nouveau_dma_subc_bind(struct nouveau_grobj *);
+extern void nouveau_dma_channel_init(struct nouveau_channel *);
+extern void nouveau_dma_kickoff(struct nouveau_channel *);
+
+#ifdef NOUVEAU_DMA_DEBUG
+static char faulty[1024];
+#endif
+
+static inline void
+nouveau_dma_out(struct nouveau_channel *userchan, uint32_t data)
+{
+       struct nouveau_channel_priv *chan = nouveau_channel(userchan);
+
+#ifdef NOUVEAU_DMA_DEBUG
+       if (chan->dma.push_free == 0) {
+               NOUVEAU_ERR("No space left in packet. Error at %s\n",faulty);
+               return;
+       }
+       chan->dma.push_free--;
+#endif
+#ifdef NOUVEAU_DMA_TRACE
+       {
+               uint32_t offset = (chan->dma.cur << 2) + chan->dma.base;
+               NOUVEAU_MSG("\tOUT_RING %d/0x%08x -> 0x%08x\n",
+                           chan->drm.channel, offset, data);
+       }
+#endif
+       chan->pushbuf[chan->dma.cur++] = data;
+}
+
+static inline void
+nouveau_dma_outp(struct nouveau_channel *userchan, uint32_t *ptr, int size)
+{
+       struct nouveau_channel_priv *chan = nouveau_channel(userchan);
+       (void)chan;
+
+#ifdef NOUVEAU_DMA_DEBUG
+       if (chan->dma.push_free < size) {
+               NOUVEAU_ERR("Packet too small.  Free=%d, Need=%d\n",
+                           chan->dma.push_free, size);
+               return;
+       }
+#endif
+#ifdef NOUVEAU_DMA_TRACE
+       while (size--) {
+               nouveau_dma_out(userchan, *ptr);
+               ptr++;
+       }
+#else
+       memcpy(&chan->pushbuf[chan->dma.cur], ptr, size << 2);
+#ifdef NOUVEAU_DMA_DEBUG
+       chan->dma.push_free -= size;
+#endif
+       chan->dma.cur += size;
+#endif
+}
+
+static inline void
+nouveau_dma_begin(struct nouveau_channel *userchan, struct nouveau_grobj *grobj,
+                 int method, int size, const char* file, int line)
+{
+       struct nouveau_channel_priv *chan = nouveau_channel(userchan);
+       int push_size = size + 1;
+
+#ifdef NOUVEAU_DMA_SUBCHAN_LRU
+       if (grobj->bound == NOUVEAU_GROBJ_UNBOUND)
+               nouveau_dma_subc_bind(grobj);
+       chan->subchannel[grobj->subc].seq = chan->subc_sequence++;
+#endif
+
+#ifdef NOUVEAU_DMA_TRACE
+       NOUVEAU_MSG("BEGIN_RING %d/%08x/%d/0x%04x/%d\n", chan->drm.channel,
+                   grobj->handle, grobj->subc, method, size);
+#endif
+
+#ifdef NOUVEAU_DMA_DEBUG
+       if (chan->dma.push_free) {
+               NOUVEAU_ERR("Previous packet incomplete: %d left. Error at %s\n",
+                           chan->dma.push_free,faulty);
+               return;
+       }
+       sprintf(faulty,"%s:%d",file,line);
+#endif
+
+       if (chan->dma.free < push_size) {
+               if (nouveau_dma_wait(userchan, push_size) &&
+                   userchan->hang_notify) {
+                       userchan->hang_notify(userchan);
+               }
+       }
+       chan->dma.free -= push_size;
+#ifdef NOUVEAU_DMA_DEBUG
+       chan->dma.push_free = push_size;
+#endif
+
+       nouveau_dma_out(userchan, (size << 18) | (grobj->subc << 13) | method);
+}
+
+static inline void
+nouveau_dma_bind(struct nouveau_channel *userchan, struct nouveau_grobj *grobj,
+                int subc)
+{
+       struct nouveau_channel_priv *chan = nouveau_channel(userchan);
+
+       if (chan->subchannel[subc].grobj == grobj)
+               return;
+
+       if (chan->subchannel[subc].grobj)
+               chan->subchannel[subc].grobj->bound = NOUVEAU_GROBJ_UNBOUND;
+       chan->subchannel[subc].grobj = grobj;
+       grobj->subc  = subc;
+       grobj->bound = NOUVEAU_GROBJ_EXPLICIT_BIND;
+
+       nouveau_dma_begin(userchan, grobj, 0x0000, 1, __FUNCTION__, __LINE__);
+       nouveau_dma_out  (userchan, grobj->handle);
+}
+
+#define BIND_RING_CH(ch,gr,sc)       nouveau_dma_bind((ch), (gr), (sc))
+#define BEGIN_RING_CH(ch,gr,m,sz)    nouveau_dma_begin((ch), (gr), (m), (sz), __FUNCTION__, __LINE__ )
+#define OUT_RING_CH(ch, data)        nouveau_dma_out((ch), (data))
+#define OUT_RINGp_CH(ch,ptr,dwords)  nouveau_dma_outp((ch), (void*)(ptr),      \
+                                                     (dwords))
+#define FIRE_RING_CH(ch)             nouveau_dma_kickoff((ch))
+#define WAIT_RING_CH(ch,sz)          nouveau_dma_wait((ch), (sz))
+               
+#endif

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_dri.h b/src/mesa/drivers/dri/nouveau_winsys/nouveau_dri.h
new file mode 100644 (file)
index 0000000..1207c2d
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_dri.h
@@ -0,0 +1,28 @@
+#ifndef _NOUVEAU_DRI_
+#define _NOUVEAU_DRI_
+
+#include "xf86drm.h"
+#include "drm.h"
+#include "nouveau_drm.h"
+
+struct nouveau_dri {
+       uint32_t device_id;     /**< \brief PCI device ID */
+       uint32_t width;         /**< \brief width in pixels of display */
+       uint32_t height;        /**< \brief height in scanlines of display */
+       uint32_t depth;         /**< \brief depth of display (8, 15, 16, 24) */
+       uint32_t bpp;           /**< \brief bit depth of display (8, 16, 24, 32) */
+
+       uint32_t bus_type;      /**< \brief ths bus type */
+       uint32_t bus_mode;      /**< \brief bus mode (used for AGP, maybe also for PCI-E ?) */
+
+       uint32_t front_offset;  /**< \brief front buffer offset */
+       uint32_t front_pitch;   /**< \brief front buffer pitch */
+       uint32_t back_offset;   /**< \brief private back buffer offset */
+       uint32_t back_pitch;    /**< \brief private back buffer pitch */
+       uint32_t depth_offset;  /**< \brief private depth buffer offset */
+       uint32_t depth_pitch;   /**< \brief private depth buffer pitch */
+
+};
+
+#endif
+

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_drmif.h b/src/mesa/drivers/dri/nouveau_winsys/nouveau_drmif.h
new file mode 100644 (file)
index 0000000..1a21da6
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_drmif.h
@@ -0,0 +1,212 @@
+/*
+ * Copyright 2007 Nouveau Project
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef __NOUVEAU_DRMIF_H__
+#define __NOUVEAU_DRMIF_H__
+
+#include <stdint.h>
+#include <xf86drm.h>
+#include <nouveau_drm.h>
+
+#include "nouveau_device.h"
+#include "pipe/nouveau/nouveau_channel.h"
+#include "pipe/nouveau/nouveau_grobj.h"
+#include "pipe/nouveau/nouveau_notifier.h"
+#include "pipe/nouveau/nouveau_bo.h"
+
+struct nouveau_device_priv {
+       struct nouveau_device base;
+
+       int fd;
+       drm_context_t ctx;
+       drmLock *lock;
+       int needs_close;
+
+       struct {
+               struct nouveau_channel *channel;
+               struct nouveau_notifier *notify;
+               struct nouveau_grobj *m2mf;
+       } bufmgr;
+};
+#define nouveau_device(n) ((struct nouveau_device_priv *)(n))
+
+extern int
+nouveau_device_open_existing(struct nouveau_device **, int close,
+                            int fd, drm_context_t ctx);
+
+extern int
+nouveau_device_open(struct nouveau_device **, const char *busid);
+
+extern void
+nouveau_device_close(struct nouveau_device **);
+
+extern int
+nouveau_device_get_param(struct nouveau_device *, uint64_t param, uint64_t *v);
+
+extern int
+nouveau_device_set_param(struct nouveau_device *, uint64_t param, uint64_t val);
+
+struct nouveau_channel_priv {
+       struct nouveau_channel base;
+
+       struct drm_nouveau_channel_alloc drm;
+
+       struct {
+               struct nouveau_grobj *grobj;
+               uint32_t seq;
+       } subchannel[8];
+       uint32_t subc_sequence;
+
+       uint32_t *pushbuf;
+       void     *notifier_block;
+
+       volatile uint32_t *user;
+       volatile uint32_t *put;
+       volatile uint32_t *get;
+       volatile uint32_t *ref_cnt;
+
+       struct {
+               uint32_t base, max;
+               uint32_t cur, put;
+               uint32_t free;
+
+               int push_free;
+       } dma;
+
+       struct {
+               struct nouveau_bo_priv *bo;
+               uint32_t flags;
+       } buffers[128];
+       int nr_buffers;
+
+       struct nouveau_bo_reloc *relocs;
+       int num_relocs;
+       int max_relocs;
+};
+#define nouveau_channel(n) ((struct nouveau_channel_priv *)(n))
+
+extern int
+nouveau_channel_alloc(struct nouveau_device *, uint32_t fb, uint32_t tt,
+                     struct nouveau_channel **);
+
+extern void
+nouveau_channel_free(struct nouveau_channel **);
+
+struct nouveau_grobj_priv {
+       struct nouveau_grobj base;
+};
+#define nouveau_grobj(n) ((struct nouveau_grobj_priv *)(n))
+
+extern int nouveau_grobj_alloc(struct nouveau_channel *, uint32_t handle,
+                              int class, struct nouveau_grobj **);
+extern int nouveau_grobj_ref(struct nouveau_channel *, uint32_t handle,
+                            struct nouveau_grobj **);
+extern void nouveau_grobj_free(struct nouveau_grobj **);
+
+
+struct nouveau_notifier_priv {
+       struct nouveau_notifier base;
+
+       struct drm_nouveau_notifierobj_alloc drm;
+       volatile void *map;
+};
+#define nouveau_notifier(n) ((struct nouveau_notifier_priv *)(n))
+
+extern int
+nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, int count,
+                      struct nouveau_notifier **);
+
+extern void
+nouveau_notifier_free(struct nouveau_notifier **);
+
+extern void
+nouveau_notifier_reset(struct nouveau_notifier *, int id);
+
+extern uint32_t
+nouveau_notifier_status(struct nouveau_notifier *, int id);
+
+extern uint32_t
+nouveau_notifier_return_val(struct nouveau_notifier *, int id);
+
+extern int
+nouveau_notifier_wait_status(struct nouveau_notifier *, int id, int status,
+                            int timeout);
+
+struct nouveau_bo_priv {
+       struct nouveau_bo base;
+
+       struct drm_nouveau_mem_alloc drm;
+       void *map;
+
+       void *sysmem;
+       int user;
+
+       int refcount;
+};
+
+struct nouveau_bo_reloc {
+       struct nouveau_bo_priv *bo;
+       uint32_t *ptr;
+       uint32_t flags;
+       uint32_t data, vor, tor;
+};
+
+#define nouveau_bo(n) ((struct nouveau_bo_priv *)(n))
+
+extern int
+nouveau_bo_init(struct nouveau_device *);
+
+extern void
+nouveau_bo_takedown(struct nouveau_device *);
+
+extern int
+nouveau_bo_new(struct nouveau_device *, uint32_t flags, int align, int size,
+              struct nouveau_bo **);
+
+extern int
+nouveau_bo_user(struct nouveau_device *, void *ptr, int size,
+               struct nouveau_bo **);
+
+extern int
+nouveau_bo_ref(struct nouveau_device *, uint64_t handle, struct nouveau_bo **);
+
+extern int
+nouveau_bo_resize(struct nouveau_bo *, int size);
+
+extern void
+nouveau_bo_del(struct nouveau_bo **);
+
+extern int
+nouveau_bo_map(struct nouveau_bo *, uint32_t flags);
+
+extern void
+nouveau_bo_unmap(struct nouveau_bo *);
+
+extern void
+nouveau_bo_emit_reloc(struct nouveau_channel *chan, void *ptr,
+                     struct nouveau_bo *, uint32_t data, uint32_t flags,
+                     uint32_t vor, uint32_t tor);
+
+extern void
+nouveau_bo_validate(struct nouveau_channel *);
+
+#endif

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_grobj.c b/src/mesa/drivers/dri/nouveau_winsys/nouveau_grobj.c
new file mode 100644 (file)
index 0000000..8dab202
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_grobj.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2007 Nouveau Project
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <stdlib.h>
+#include <errno.h>
+
+#include "nouveau_drmif.h"
+
+int
+nouveau_grobj_alloc(struct nouveau_channel *userchan, uint32_t handle,
+                   int class, struct nouveau_grobj **usergrobj)
+{
+       struct nouveau_device_priv *nv = nouveau_device(userchan->device);
+       struct nouveau_grobj_priv *gr;
+       struct drm_nouveau_grobj_alloc g;
+       int ret;
+
+       if (!nv || !usergrobj || *usergrobj)
+               return -EINVAL;
+
+       gr = calloc(1, sizeof(*gr));
+       if (!gr)
+               return -ENOMEM;
+       gr->base.channel = userchan;
+       gr->base.handle  = handle;
+       gr->base.grclass = class;
+
+       g.channel = userchan->id;
+       g.handle  = handle;
+       g.class   = class;
+       ret = drmCommandWrite(nv->fd, DRM_NOUVEAU_GROBJ_ALLOC, &g, sizeof(g));
+       if (ret) {
+               nouveau_grobj_free((void *)&gr);
+               return ret;
+       }
+
+       *usergrobj = &gr->base;
+       return 0;
+}
+
+int
+nouveau_grobj_ref(struct nouveau_channel *userchan, uint32_t handle,
+                 struct nouveau_grobj **usergr)
+{
+       struct nouveau_grobj_priv *gr;
+
+       if (!userchan || !usergr || *usergr)
+               return -EINVAL;
+
+       gr = calloc(1, sizeof(*gr));
+       if (!gr)
+               return -ENOMEM;
+       gr->base.channel = userchan;
+       gr->base.handle = handle;
+       gr->base.grclass = 0;
+
+       *usergr = &gr->base;
+       return 0;
+}
+
+void
+nouveau_grobj_free(struct nouveau_grobj **usergrobj)
+{
+       struct nouveau_grobj_priv *gr;
+
+       if (!usergrobj)
+               return;
+       gr = nouveau_grobj(*usergrobj);
+       *usergrobj = NULL;
+
+       if (gr) {
+               struct nouveau_channel_priv *chan;
+               struct nouveau_device_priv *nv;
+               struct drm_nouveau_gpuobj_free f;
+
+               chan = nouveau_channel(gr->base.channel);
+               nv   = nouveau_device(chan->base.device);
+
+               if (gr->base.grclass) {
+                       f.channel = chan->drm.channel;
+                       f.handle  = gr->base.handle;
+                       drmCommandWrite(nv->fd, DRM_NOUVEAU_GPUOBJ_FREE,
+                                       &f, sizeof(f)); 
+               }
+               free(gr);
+       }
+}
+

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_local.h b/src/mesa/drivers/dri/nouveau_winsys/nouveau_local.h
new file mode 100644 (file)
index 0000000..4ada5d0
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_local.h
@@ -0,0 +1,82 @@
+#ifndef __NOUVEAU_LOCAL_H__
+#define __NOUVEAU_LOCAL_H__
+
+#include <stdio.h>
+
+/* Debug output */
+#define NOUVEAU_MSG(fmt, args...) do {                                         \
+       fprintf(stdout, "nouveau: "fmt, ##args);                               \
+       fflush(stdout);                                                        \
+} while(0)
+
+#define NOUVEAU_ERR(fmt, args...) do {                                         \
+       fprintf(stderr, "%s:%d -  "fmt, __func__, __LINE__, ##args);           \
+       fflush(stderr);                                                        \
+} while(0)
+
+#define NOUVEAU_TIME_MSEC() 0
+
+/* User FIFO control */
+//#define NOUVEAU_DMA_TRACE
+//#define NOUVEAU_DMA_DEBUG
+//#define NOUVEAU_DMA_DUMP_POSTRELOC_PUSHBUF
+#define NOUVEAU_DMA_SUBCHAN_LRU
+#define NOUVEAU_DMA_BARRIER 
+#define NOUVEAU_DMA_TIMEOUT 2000
+
+/* Push buffer access macros */
+#define BEGIN_RING(obj,mthd,size) do {                                         \
+       BEGIN_RING_CH(nv->channel, nv->obj, (mthd), (size));                   \
+} while(0)
+
+#define OUT_RING(data) do {                                                    \
+       OUT_RING_CH(nv->channel, (data));                                      \
+} while(0)
+
+#define OUT_RINGp(src,size) do {                                               \
+       OUT_RINGp_CH(nv->channel, (src), (size));                              \
+} while(0)
+
+#define OUT_RINGf(data) do {                                                   \
+       union { float v; uint32_t u; } c;                                      \
+       c.v = (data);                                                          \
+       OUT_RING(c.u);                                                         \
+} while(0)
+
+#define WAIT_RING(size) do {                                                   \
+       WAIT_RING_CH(nv->channel, (size));                                     \
+} while(0)
+
+#define FIRE_RING() do {                                                       \
+       FIRE_RING_CH(nv->channel);                                             \
+} while(0)
+
+#define OUT_RELOC(bo,data,flags,vor,tor) do {                                  \
+       struct nouveau_channel_priv *chan = nouveau_channel(nv->channel);      \
+       nouveau_bo_emit_reloc(nv->channel, &chan->pushbuf[chan->dma.cur],      \
+                             (void*)(bo), (data), (flags), (vor), (tor));     \
+       OUT_RING(0);                                                           \
+} while(0)
+
+/* Raw data + flags depending on FB/TT buffer */
+#define OUT_RELOCd(bo,data,flags,vor,tor) do {                                 \
+       OUT_RELOC((bo), (data), (flags) | NOUVEAU_BO_OR, (vor), (tor));        \
+} while(0)
+
+/* FB/TT object handle */
+#define OUT_RELOCo(bo,flags) do {                                              \
+       OUT_RELOC((bo), 0, (flags) | NOUVEAU_BO_OR,                            \
+                 nv->channel->vram->handle, nv->channel->gart->handle);       \
+} while(0)
+
+/* Low 32-bits of offset */
+#define OUT_RELOCl(bo,delta,flags) do {                                        \
+       OUT_RELOC((bo), (delta), (flags) | NOUVEAU_BO_LOW, 0, 0);              \
+} while(0)
+
+/* High 32-bits of offset */
+#define OUT_RELOCh(bo,delta,flags) do {                                        \
+       OUT_RELOC((bo), (delta), (flags) | NOUVEAU_BO_HIGH, 0, 0);             \
+} while(0)
+
+#endif

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_lock.c b/src/mesa/drivers/dri/nouveau_winsys/nouveau_lock.c
new file mode 100644 (file)
index 0000000..ffe7d01
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_lock.c
@@ -0,0 +1,103 @@
+/**************************************************************************
+ * 
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ * 
+ **************************************************************************/
+
+
+#include "glheader.h"
+#include "context.h"
+#include "extensions.h"
+
+#include "state_tracker/st_public.h"
+#include "state_tracker/st_context.h"
+
+#include "drirenderbuffer.h"
+#include "vblank.h"
+#include "utils.h"
+#include "xmlpool.h"            /* for symbolic values of enum-type options */
+
+#include "nouveau_context.h"
+#include "nouveau_screen.h"
+
+_glthread_DECLARE_STATIC_MUTEX( lockMutex );
+
+static void
+nouveau_contended_lock(struct nouveau_context *nv, GLuint flags)
+{
+       __DRIdrawablePrivate *dPriv = nv->dri_drawable;
+       __DRIscreenPrivate *sPriv = nv->dri_screen;
+       struct nouveau_screen *nv_screen = nv->nv_screen;
+       struct nouveau_device *dev = nv_screen->device;
+       struct nouveau_device_priv *nvdev = nouveau_device(dev);
+
+       drmGetLock(nvdev->fd, nvdev->ctx, flags);
+
+       /* If the window moved, may need to set a new cliprect now.
+        *
+        * NOTE: This releases and regains the hw lock, so all state
+        * checking must be done *after* this call:
+        */
+       if (dPriv)
+               DRI_VALIDATE_DRAWABLE_INFO(sPriv, dPriv);
+}
+
+/* Lock the hardware and validate our state.
+ */
+void
+LOCK_HARDWARE(struct nouveau_context *nv)
+{
+       struct nouveau_screen *nv_screen = nv->nv_screen;
+       struct nouveau_device *dev = nv_screen->device;
+       struct nouveau_device_priv *nvdev = nouveau_device(dev);
+       char __ret=0;
+
+       _glthread_LOCK_MUTEX(lockMutex);
+       assert(!nv->locked);
+       
+       DRM_CAS(nvdev->lock, nvdev->ctx,
+               (DRM_LOCK_HELD | nvdev->ctx), __ret);
+       
+       if (__ret)
+               nouveau_contended_lock(nv, 0);
+       nv->locked = GL_TRUE;
+}
+
+
+  /* Unlock the hardware using the global current context 
+   */
+void
+UNLOCK_HARDWARE(struct nouveau_context *nv)
+{
+       struct nouveau_screen *nv_screen = nv->nv_screen;
+       struct nouveau_device *dev = nv_screen->device;
+       struct nouveau_device_priv *nvdev = nouveau_device(dev);
+
+       assert(nv->locked);
+       nv->locked = GL_FALSE;
+
+       DRM_UNLOCK(nvdev->fd, nvdev->lock, nvdev->ctx);
+
+       _glthread_UNLOCK_MUTEX(lockMutex);
+} 

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_notifier.c b/src/mesa/drivers/dri/nouveau_winsys/nouveau_notifier.c
new file mode 100644 (file)
index 0000000..e423d59
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_notifier.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright 2007 Nouveau Project
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <stdlib.h>
+#include <errno.h>
+
+#include "nouveau_drmif.h"
+#include "nouveau_local.h"
+
+#define NOTIFIER(__v)                                                          \
+       struct nouveau_notifier_priv *notifier = nouveau_notifier(user);       \
+       volatile uint32_t *n = (void*)notifier->map + (id * 32)
+
+int
+nouveau_notifier_alloc(struct nouveau_channel *userchan, uint32_t handle,
+                      int count, struct nouveau_notifier **usernotifier)
+{
+       struct nouveau_notifier_priv *notifier;
+       int ret;
+
+       if (!userchan || !usernotifier || *usernotifier)
+               return -EINVAL;
+
+       notifier = calloc(1, sizeof(*notifier));
+       if (!notifier)
+               return -ENOMEM;
+       notifier->base.channel = userchan;
+       notifier->base.handle  = handle;
+
+       notifier->drm.channel = userchan->id;
+       notifier->drm.handle  = handle;
+       notifier->drm.count   = count;
+       if ((ret = drmCommandWriteRead(nouveau_device(userchan->device)->fd,
+                                      DRM_NOUVEAU_NOTIFIEROBJ_ALLOC,
+                                      &notifier->drm,
+                                      sizeof(notifier->drm)))) {
+               nouveau_notifier_free((void *)&notifier);
+               return ret;
+       }
+
+       notifier->map = (void *)nouveau_channel(userchan)->notifier_block +
+                               notifier->drm.offset;
+       *usernotifier = &notifier->base;
+       return 0;
+}
+
+void
+nouveau_notifier_free(struct nouveau_notifier **usernotifier)
+{
+
+       struct nouveau_notifier_priv *notifier;
+
+       if (!usernotifier)
+               return;
+       notifier = nouveau_notifier(*usernotifier);
+       *usernotifier = NULL;
+
+       if (notifier) {
+               struct nouveau_channel_priv *chan;
+               struct nouveau_device_priv *nv;
+               struct drm_nouveau_gpuobj_free f;
+
+               chan = nouveau_channel(notifier->base.channel);
+               nv   = nouveau_device(chan->base.device);
+
+               f.channel = chan->drm.channel;
+               f.handle  = notifier->base.handle;
+               drmCommandWrite(nv->fd, DRM_NOUVEAU_GPUOBJ_FREE, &f, sizeof(f));                
+               free(notifier);
+       }
+}
+
+void
+nouveau_notifier_reset(struct nouveau_notifier *user, int id)
+{
+       NOTIFIER(n);
+
+       n[NV_NOTIFY_TIME_0      /4] = 0x00000000;
+       n[NV_NOTIFY_TIME_1      /4] = 0x00000000;
+       n[NV_NOTIFY_RETURN_VALUE/4] = 0x00000000;
+       n[NV_NOTIFY_STATE       /4] = (NV_NOTIFY_STATE_STATUS_IN_PROCESS <<
+                                      NV_NOTIFY_STATE_STATUS_SHIFT);
+}
+
+uint32_t
+nouveau_notifier_status(struct nouveau_notifier *user, int id)
+{
+       NOTIFIER(n);
+
+       return n[NV_NOTIFY_STATE/4] >> NV_NOTIFY_STATE_STATUS_SHIFT;
+}
+
+uint32_t
+nouveau_notifier_return_val(struct nouveau_notifier *user, int id)
+{
+       NOTIFIER(n);
+
+       return n[NV_NOTIFY_RETURN_VALUE/4];
+}
+
+int
+nouveau_notifier_wait_status(struct nouveau_notifier *user, int id,
+                            int status, int timeout)
+{
+       NOTIFIER(n);
+       uint32_t time = 0, t_start = NOUVEAU_TIME_MSEC();
+
+       while (time <= timeout) {
+               uint32_t v;
+
+               v = n[NV_NOTIFY_STATE/4] >> NV_NOTIFY_STATE_STATUS_SHIFT;
+               if (v == status)
+                       return 0;
+
+               if (timeout)
+                       time = NOUVEAU_TIME_MSEC() - t_start;
+       }
+
+       return -EBUSY;
+}
+

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_screen.c b/src/mesa/drivers/dri/nouveau_winsys/nouveau_screen.c
new file mode 100644 (file)
index 0000000..48f583c
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_screen.c
@@ -0,0 +1,253 @@
+#include "glheader.h"
+#include "context.h"
+#include "framebuffer.h"
+#include "matrix.h"
+#include "renderbuffer.h"
+#include "simple_list.h"
+#include "utils.h"
+#include "vblank.h"
+#include "xmlpool.h"
+
+#include "pipe/p_context.h"
+#include "state_tracker/st_public.h"
+#include "state_tracker/st_cb_fbo.h"
+
+#include "nouveau_context.h"
+#include "nouveau_device.h"
+#include "nouveau_drm.h"
+#include "nouveau_dri.h"
+#include "nouveau_local.h"
+#include "nouveau_screen.h"
+#include "nouveau_swapbuffers.h"
+
+#if NOUVEAU_DRM_HEADER_PATCHLEVEL != 10
+#error nouveau_drm.h version does not match expected version
+#endif
+
+PUBLIC const char __driConfigOptions[] =
+DRI_CONF_BEGIN
+DRI_CONF_END;
+static const GLuint __driNConfigOptions = 0;
+
+extern const struct dri_extension common_extensions[];
+extern const struct dri_extension nv40_extensions[];
+
+static GLboolean
+nouveau_screen_create(__DRIscreenPrivate *driScrnPriv)
+{
+       struct nouveau_dri *nv_dri = driScrnPriv->pDevPriv;
+       struct nouveau_screen *nv_screen;
+       int ret;
+
+       if (driScrnPriv->devPrivSize != sizeof(struct nouveau_dri)) {
+               NOUVEAU_ERR("DRI struct mismatch between DDX/DRI\n");
+               return GL_FALSE;
+       }
+
+       nv_screen = CALLOC_STRUCT(nouveau_screen);
+       if (!nv_screen)
+               return GL_FALSE;
+       nv_screen->driScrnPriv = driScrnPriv;
+       driScrnPriv->private = (void *)nv_screen;
+
+       driParseOptionInfo(&nv_screen->option_cache,
+                          __driConfigOptions, __driNConfigOptions);
+
+       if ((ret = nouveau_device_open_existing(&nv_screen->device, 0,
+                                               driScrnPriv->fd, 0))) {
+               NOUVEAU_ERR("Failed opening nouveau device: %d\n", ret);
+               return GL_FALSE;
+       }
+
+       nv_screen->front_offset = nv_dri->front_offset;
+       nv_screen->front_pitch  = nv_dri->front_pitch * (nv_dri->bpp / 8);
+
+       return GL_TRUE;
+}
+
+static void
+nouveau_screen_destroy(__DRIscreenPrivate *driScrnPriv)
+{
+       struct nouveau_screen *nv_screen = driScrnPriv->private;
+
+       driScrnPriv->private = NULL;
+       FREE(nv_screen);
+}
+
+static GLboolean
+nouveau_create_buffer(__DRIscreenPrivate * driScrnPriv,
+                     __DRIdrawablePrivate * driDrawPriv,
+                     const __GLcontextModes *glVis, GLboolean pixmapBuffer)
+{
+       struct nouveau_framebuffer *nvfb;
+
+       if (pixmapBuffer)
+               return GL_FALSE;
+
+       nvfb = CALLOC_STRUCT(nouveau_framebuffer);
+       if (!nvfb)
+               return GL_FALSE;
+
+       nvfb->stfb = st_create_framebuffer(glVis, GL_TRUE, (void*)nvfb);
+       if (!nvfb->stfb) {
+               free(nvfb);
+               return  GL_FALSE;
+       }
+
+       driDrawPriv->driverPrivate = (void *)nvfb;
+       return GL_TRUE;
+}
+
+static void
+nouveau_destroy_buffer(__DRIdrawablePrivate * driDrawPriv)
+{
+       struct nouveau_framebuffer *nvfb;
+       
+       nvfb = (struct nouveau_framebuffer *)driDrawPriv;
+       st_unreference_framebuffer(&nvfb->stfb);
+       free(nvfb);
+}
+
+static struct __DriverAPIRec
+nouveau_api = {
+       .InitDriver     = nouveau_screen_create,
+       .DestroyScreen  = nouveau_screen_destroy,
+       .CreateContext  = nouveau_context_create,
+       .DestroyContext = nouveau_context_destroy,
+       .CreateBuffer   = nouveau_create_buffer,
+       .DestroyBuffer  = nouveau_destroy_buffer,
+       .SwapBuffers    = nouveau_swap_buffers,
+       .MakeCurrent    = nouveau_context_bind,
+       .UnbindContext  = nouveau_context_unbind,
+       .GetSwapInfo    = NULL,
+       .GetMSC         = NULL,
+       .WaitForMSC     = NULL,
+       .WaitForSBC     = NULL,
+       .SwapBuffersMSC = NULL,
+       .CopySubBuffer  = nouveau_copy_sub_buffer,
+       .setTexOffset   = NULL
+};
+
+static __GLcontextModes *
+nouveau_fill_in_modes(unsigned pixel_bits, unsigned depth_bits,
+                     unsigned stencil_bits, GLboolean have_back_buffer)
+{
+       __GLcontextModes * modes;
+       __GLcontextModes * m;
+       unsigned num_modes;
+       unsigned depth_buffer_factor;
+       unsigned back_buffer_factor;
+       int i;
+
+       static const struct {
+               GLenum format;
+               GLenum type;
+       } fb_format_array[] = {
+               { GL_RGB , GL_UNSIGNED_SHORT_5_6_5     },
+               { GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV },
+               { GL_BGR , GL_UNSIGNED_INT_8_8_8_8_REV },
+       };
+
+       /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
+        * support pageflipping at all.
+        */
+       static const GLenum back_buffer_modes[] = {
+               GLX_NONE, GLX_SWAP_UNDEFINED_OML, GLX_SWAP_COPY_OML
+       };
+
+       u_int8_t depth_bits_array[4]   = { 0, 16, 24 };
+       u_int8_t stencil_bits_array[4] = { 0,  0,  8 };
+
+       depth_buffer_factor = 4;
+       back_buffer_factor  = (have_back_buffer) ? 3 : 1;
+
+       num_modes = ((pixel_bits==16) ? 1 : 2) *
+               depth_buffer_factor * back_buffer_factor * 4;
+       modes = (*dri_interface->createContextModes)(num_modes,
+                                                    sizeof(__GLcontextModes));
+       m = modes;
+
+       for (i=((pixel_bits==16)?0:1);i<((pixel_bits==16)?1:3);i++) {
+               if (!driFillInModes(&m, fb_format_array[i].format,
+                                       fb_format_array[i].type,
+                                       depth_bits_array,
+                                       stencil_bits_array,
+                                       depth_buffer_factor,
+                                       back_buffer_modes,
+                                       back_buffer_factor,
+                                       GLX_TRUE_COLOR)) {
+               fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
+                               __func__, __LINE__ );
+               return NULL;
+               }
+
+               if (!driFillInModes(&m, fb_format_array[i].format,
+                                       fb_format_array[i].type,
+                                       depth_bits_array,
+                                       stencil_bits_array,
+                                       depth_buffer_factor,
+                                       back_buffer_modes,
+                                       back_buffer_factor,
+                                       GLX_DIRECT_COLOR)) {
+               fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
+                               __func__, __LINE__ );
+               return NULL;
+               }
+       }
+
+       return modes;
+}
+PUBLIC void *
+__driCreateNewScreen_20050727(__DRInativeDisplay *dpy, int scrn,
+                             __DRIscreen *psc, const __GLcontextModes * modes,
+                             const __DRIversion * ddx_version,
+                             const __DRIversion * dri_version,
+                             const __DRIversion * drm_version,
+                             const __DRIframebuffer * frame_buffer,
+                             void * pSAREA, int fd, int internal_api_version,
+                             const __DRIinterfaceMethods * interface,
+                             __GLcontextModes ** driver_modes)
+{
+       __DRIscreenPrivate *psp;
+       static const __DRIversion ddx_expected = { 1, 2, 0 };
+       static const __DRIversion dri_expected = { 4, 0, 0 };
+       static const __DRIversion drm_expected =
+               { 0, 0, NOUVEAU_DRM_HEADER_PATCHLEVEL };
+       struct nouveau_dri *nv_dri = NULL;
+
+       dri_interface = interface;
+
+       if (!driCheckDriDdxDrmVersions2("nouveau",
+                                       dri_version, &dri_expected,
+                                       ddx_version, &ddx_expected,
+                                       drm_version, &drm_expected)) {
+               return NULL;
+       }
+
+       if (drm_expected.patch != drm_version->patch) {
+               fprintf(stderr, "Incompatible DRM patch level.\n"
+                               "Expected: %d\n" "Current : %d\n",
+                       drm_expected.patch, drm_version->patch);
+               return NULL;
+       }
+
+       psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
+                                      ddx_version, dri_version, drm_version,
+                                      frame_buffer, pSAREA, fd,
+                                      internal_api_version,
+                                      &nouveau_api);
+       if (psp == NULL)
+               return NULL;
+       nv_dri = psp->pDevPriv;
+
+       *driver_modes = nouveau_fill_in_modes(nv_dri->bpp,
+                                             (nv_dri->bpp == 16) ? 16 : 24,
+                                             (nv_dri->bpp == 16) ? 0 : 8,
+                                             1);
+
+       driInitExtensions(NULL, common_extensions, GL_FALSE);
+       driInitExtensions(NULL, nv40_extensions, GL_FALSE);
+
+       return (void *)psp;
+}
+

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_screen.h b/src/mesa/drivers/dri/nouveau_winsys/nouveau_screen.h
new file mode 100644 (file)
index 0000000..e53cd87
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_screen.h
@@ -0,0 +1,17 @@
+#ifndef __NOUVEAU_SCREEN_H__
+#define __NOUVEAU_SCREEN_H__
+
+#include "xmlconfig.h"
+#include "nouveau_device.h"
+
+struct nouveau_screen {
+       __DRIscreenPrivate *driScrnPriv;
+       driOptionCache      option_cache;
+
+       struct nouveau_device *device;
+
+       uint32_t front_offset;
+       uint32_t front_pitch;
+};
+
+#endif

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_swapbuffers.c b/src/mesa/drivers/dri/nouveau_winsys/nouveau_swapbuffers.c
new file mode 100644 (file)
index 0000000..57598f9
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_swapbuffers.c
@@ -0,0 +1,98 @@
+#include "context.h"
+
+#include "pipe/p_context.h"
+#include "state_tracker/st_public.h"
+#include "state_tracker/st_cb_fbo.h"
+
+#include "nouveau_context.h"
+#include "nouveau_local.h"
+#include "nouveau_screen.h"
+#include "nouveau_swapbuffers.h"
+
+void
+nouveau_copy_buffer(__DRIdrawablePrivate *dPriv, struct pipe_surface *surf,
+                   const drm_clip_rect_t *rect)
+{
+       struct nouveau_context *nv = dPriv->driContextPriv->driverPrivate;
+       struct nouveau_screen *nv_screen = nv->nv_screen;
+       struct pipe_region *p_region = surf->region;
+       drm_clip_rect_t *pbox;
+       int nbox, i;
+
+       LOCK_HARDWARE(nv);
+       if (!dPriv->numClipRects) {
+               UNLOCK_HARDWARE(nv);
+               return;
+       }
+       pbox = dPriv->pClipRects;
+       nbox = dPriv->numClipRects;
+
+       BEGIN_RING(NvCtxSurf2D, 0x184, 2);
+       OUT_RELOCo(p_region->buffer, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
+       OUT_RING  (nv->channel->vram->handle);
+
+       BEGIN_RING(NvCtxSurf2D, 0x300, 4);
+       OUT_RING  ((p_region->cpp == 4) ? 6 : 4);
+       OUT_RING  ((nv_screen->front_pitch << 16) |
+                  (p_region->pitch * p_region->cpp));
+       OUT_RELOCl(p_region->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
+       OUT_RING  (nv_screen->front_offset);
+
+       for (i = 0; i < nbox; i++, pbox++) {
+               int sx, sy, dx, dy, w, h;
+
+               sx = pbox->x1 - dPriv->x;
+               sy = pbox->y1 - dPriv->y;
+               dx = pbox->x1;
+               dy = pbox->y1;
+               w  = pbox->x2 - pbox->x1;
+               h  = pbox->y2 - pbox->y1;
+
+               BEGIN_RING(NvImageBlit, 0x300, 3);
+               OUT_RING  ((sy << 16) | sx);
+               OUT_RING  ((dy << 16) | dx);
+               OUT_RING  (( h << 16) |  w);
+       }
+
+       FIRE_RING();
+       UNLOCK_HARDWARE(nv);
+
+       if (nv->last_stamp != dPriv->lastStamp) {
+               struct nouveau_framebuffer *nvfb = dPriv->driverPrivate;
+               st_resize_framebuffer(nvfb->stfb, dPriv->w, dPriv->h);
+               nv->last_stamp = dPriv->lastStamp;
+       }
+}
+
+void
+nouveau_copy_sub_buffer(__DRIdrawablePrivate *dPriv, int x, int y, int w, int h)
+{
+       struct nouveau_framebuffer *nvfb = dPriv->driverPrivate;
+       struct pipe_surface *surf;
+
+       surf = st_get_framebuffer_surface(nvfb->stfb, ST_SURFACE_BACK_LEFT);
+       if (surf) {
+               drm_clip_rect_t rect;
+               rect.x1 = x;
+               rect.y1 = y;
+               rect.x2 = x + w;
+               rect.y2 = y + h;
+
+               st_notify_swapbuffers(nvfb->stfb);
+               nouveau_copy_buffer(dPriv, surf, &rect);
+       }
+}
+
+void
+nouveau_swap_buffers(__DRIdrawablePrivate *dPriv)
+{
+       struct nouveau_framebuffer *nvfb = dPriv->driverPrivate;
+       struct pipe_surface *surf;
+
+       surf = st_get_framebuffer_surface(nvfb->stfb, ST_SURFACE_BACK_LEFT);
+       if (surf) {
+               st_notify_swapbuffers(nvfb->stfb);
+               nouveau_copy_buffer(dPriv, surf, NULL);
+       }
+}
+

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_swapbuffers.h b/src/mesa/drivers/dri/nouveau_winsys/nouveau_swapbuffers.h
new file mode 100644 (file)
index 0000000..825d3da
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_swapbuffers.h
@@ -0,0 +1,10 @@
+#ifndef __NOUVEAU_SWAPBUFFERS_H__
+#define __NOUVEAU_SWAPBUFFERS_H__
+
+extern void nouveau_copy_buffer(__DRIdrawablePrivate *, struct pipe_surface *,
+                               const drm_clip_rect_t *);
+extern void nouveau_copy_sub_buffer(__DRIdrawablePrivate *,
+                                   int x, int y, int w, int h);
+extern void nouveau_swap_buffers(__DRIdrawablePrivate *);
+
+#endif

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_winsys.c b/src/mesa/drivers/dri/nouveau_winsys/nouveau_winsys.c
new file mode 100644 (file)
index 0000000..a2e85a0
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_winsys.c
@@ -0,0 +1,90 @@
+#include "nouveau_context.h"
+#include "nouveau_winsys_pipe.h"
+
+#include "pipe/nouveau/nouveau_winsys.h"
+
+static int
+nouveau_pipe_notifier_alloc(struct nouveau_winsys *nvws, int count,
+                           struct nouveau_notifier **notify)
+{
+       struct nouveau_context *nv = nvws->nv;
+
+       return nouveau_notifier_alloc(nv->channel, nv->next_handle++,
+                                     count, notify);
+}
+
+static int
+nouveau_pipe_grobj_alloc(struct nouveau_winsys *nvws, int grclass,
+                        struct nouveau_grobj **grobj)
+{
+       struct nouveau_context *nv = nvws->nv;
+
+       return nouveau_grobj_alloc(nv->channel, nv->next_handle++,
+                                  grclass, grobj);
+}
+
+static uint32_t *
+nouveau_pipe_dma_beginp(struct nouveau_grobj *grobj, int mthd, int size)
+{
+       struct nouveau_channel_priv *chan = nouveau_channel(grobj->channel);
+       uint32_t *pushbuf;
+
+       BEGIN_RING_CH(&chan->base, grobj, mthd, size);
+       pushbuf = &chan->pushbuf[chan->dma.cur];
+       chan->dma.cur += size;
+#ifdef NOUVEAU_DMA_DEBUG
+       chan->dma.push_free -= size;
+#endif
+       return pushbuf;
+}
+
+static void
+nouveau_pipe_dma_kickoff(struct nouveau_channel *userchan)
+{
+       FIRE_RING_CH(userchan);
+}
+
+struct pipe_context *
+nouveau_pipe_create(struct nouveau_context *nv)
+{
+       struct nouveau_winsys *nvws = CALLOC_STRUCT(nouveau_winsys);
+       struct pipe_context *(*hw_create)(struct pipe_winsys *,
+                                         struct nouveau_winsys *,
+                                         unsigned);
+
+       if (!nvws)
+               return NULL;
+
+       switch (nv->chipset & 0xf0) {
+       case 0x40:
+               hw_create = nv40_create;
+               break;
+       default:
+               NOUVEAU_ERR("Unknown chipset NV%02x\n", (int)nv->chipset);
+               return NULL;
+       }
+
+       nvws->nv                = nv;
+       nvws->channel           = nv->channel;
+
+       nvws->begin_ring        = nouveau_pipe_dma_beginp;
+       nvws->out_reloc         = nouveau_bo_emit_reloc;
+       nvws->fire_ring         = nouveau_pipe_dma_kickoff;
+
+       nvws->grobj_alloc       = nouveau_pipe_grobj_alloc;
+       nvws->grobj_free        = nouveau_grobj_free;
+
+       nvws->notifier_alloc    = nouveau_pipe_notifier_alloc;
+       nvws->notifier_free     = nouveau_notifier_free;
+       nvws->notifier_reset    = nouveau_notifier_reset;
+       nvws->notifier_status   = nouveau_notifier_status;
+       nvws->notifier_retval   = nouveau_notifier_return_val;
+       nvws->notifier_wait     = nouveau_notifier_wait_status;
+
+       nvws->region_copy       = nv->region_copy;
+       nvws->region_fill       = nv->region_fill;
+       nvws->region_data       = nv->region_data;
+
+       return hw_create(nouveau_create_pipe_winsys(nv), nvws, nv->chipset);
+}
+

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_winsys_pipe.c b/src/mesa/drivers/dri/nouveau_winsys/nouveau_winsys_pipe.c
new file mode 100644 (file)
index 0000000..0dd2cec
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_winsys_pipe.c
@@ -0,0 +1,251 @@
+#include "pipe/p_winsys.h"
+#include "pipe/p_defines.h"
+
+#include "nouveau_context.h"
+#include "nouveau_device.h"
+#include "nouveau_local.h"
+#include "nouveau_screen.h"
+#include "nouveau_swapbuffers.h"
+#include "nouveau_winsys_pipe.h"
+
+static void
+nouveau_flush_frontbuffer(struct pipe_winsys *pws, struct pipe_surface *surf,
+                         void *context_private)
+{
+       struct nouveau_context *nv = context_private;
+       __DRIdrawablePrivate *dPriv = nv->dri_drawable;
+
+       nouveau_copy_buffer(dPriv, surf, NULL);
+}
+
+static void
+nouveau_printf(struct pipe_winsys *pws, const char *fmt, ...)
+{
+       va_list args;
+       va_start(args, fmt);
+       vfprintf(stderr, fmt, args);
+       va_end(args);
+}
+
+static const char *
+nouveau_get_name(struct pipe_winsys *pws)
+{
+       return "Nouveau/DRI";
+}
+
+static struct pipe_region *
+nouveau_region_alloc(struct pipe_winsys *ws, unsigned cpp,
+                    unsigned width, unsigned height, unsigned flags)
+{
+       struct pipe_region *region;
+
+       region = calloc(sizeof(*region), 1);
+       region->cpp = cpp;
+       region->pitch = ((cpp * width + 63) & ~63) / cpp;
+       region->height = height;
+       region->refcount = 1;
+       region->buffer = ws->buffer_create(ws, 64);
+
+       ws->buffer_data(ws, region->buffer, region->pitch * cpp * height, NULL,
+                       PIPE_BUFFER_USAGE_PIXEL);
+       return region;
+}
+
+static void
+nouveau_region_release(struct pipe_winsys *pws, struct pipe_region **pregion)
+{
+       struct pipe_region *region;
+
+       if (!pregion || !*pregion)
+               return;
+       region = *pregion;
+       *pregion = NULL;
+
+       assert(region->refcount > 0);
+       region->refcount--;
+
+       if (region->refcount == 0) {
+               assert(region->map_refcount == 0);
+               pws->buffer_reference(pws, &region->buffer, NULL);
+               free(region);
+       }
+}
+
+static struct pipe_surface *
+nouveau_surface_alloc(struct pipe_winsys *pws, unsigned format)
+{
+       struct pipe_surface *surf;
+       
+       surf = CALLOC_STRUCT(pipe_surface);
+       if (!surf)
+               return NULL;
+
+       surf->format = format;
+       surf->refcount = 1;
+       surf->winsys = pws;
+
+       return surf;
+}
+
+static void
+nouveau_surface_release(struct pipe_winsys *pws, struct pipe_surface **s)
+{
+       struct pipe_surface *surf = *s; *s = NULL;
+
+       if (surf->refcount-- == 0) {
+               if (surf->region)
+                       pws->region_release(pws, &surf->region);
+               free(surf);
+       }
+}
+
+static struct pipe_buffer_handle *
+nouveau_pipe_bo_create(struct pipe_winsys *pws, unsigned alignment)
+{
+       struct nouveau_pipe_winsys *nvpws = (struct nouveau_pipe_winsys *)pws;
+       struct nouveau_device *dev = nvpws->nv->nv_screen->device;
+       struct nouveau_bo *nvbo = NULL;
+
+       if (nouveau_bo_new(dev, NOUVEAU_BO_LOCAL, alignment, 0, &nvbo))
+               return NULL;
+       return (struct pipe_buffer_handle *)nvbo;
+}
+
+static struct pipe_buffer_handle *
+nouveau_pipe_bo_user_create(struct pipe_winsys *pws, void *ptr, unsigned bytes)
+{
+       struct nouveau_pipe_winsys *nvpws = (struct nouveau_pipe_winsys *)pws;
+       struct nouveau_device *dev = nvpws->nv->nv_screen->device;
+       struct nouveau_bo *nvbo = NULL;
+
+       if (nouveau_bo_user(dev, ptr, bytes, &nvbo))
+               return NULL;
+       return (struct pipe_buffer_handle *)nvbo;
+}
+
+static void *
+nouveau_pipe_bo_map(struct pipe_winsys *pws, struct pipe_buffer_handle *bo,
+                   unsigned flags)
+{
+       struct nouveau_bo *nvbo = (struct nouveau_bo *)bo;
+       uint32_t map_flags = 0;
+
+       if (flags & PIPE_BUFFER_FLAG_READ)
+               map_flags |= NOUVEAU_BO_RD;
+       if (flags & PIPE_BUFFER_FLAG_WRITE)
+               map_flags |= NOUVEAU_BO_WR;
+
+       if (nouveau_bo_map(nvbo, map_flags))
+               return NULL;
+       return nvbo->map;
+}
+
+static void
+nouveau_pipe_bo_unmap(struct pipe_winsys *pws, struct pipe_buffer_handle *bo)
+{
+       struct nouveau_bo *nvbo = (struct nouveau_bo *)bo;
+
+       nouveau_bo_unmap(nvbo);
+}
+
+static void
+nouveau_pipe_bo_reference(struct pipe_winsys *pws,
+                         struct pipe_buffer_handle **ptr,
+                         struct pipe_buffer_handle *bo)
+{
+       struct nouveau_pipe_winsys *nvpws = (struct nouveau_pipe_winsys *)pws;
+       struct nouveau_context *nv = nvpws->nv;
+       struct nouveau_device *dev = nv->nv_screen->device;
+
+       if (*ptr) {
+               struct nouveau_bo *nvbo = (struct nouveau_bo *)*ptr;
+               FIRE_RING();
+               nouveau_bo_del(&nvbo);
+               *ptr = NULL;
+       }
+
+       if (bo) {
+               struct nouveau_bo *nvbo = (struct nouveau_bo *)bo, *new = NULL;
+               nouveau_bo_ref(dev, nvbo->handle, &new);
+               *ptr = bo;
+       }
+}
+
+static void
+nouveau_pipe_bo_data(struct pipe_winsys *pws, struct pipe_buffer_handle *bo,
+                    unsigned size, const void *data, unsigned usage)
+{
+       struct nouveau_bo *nvbo = (struct nouveau_bo *)bo;
+
+       if (nvbo->size != size)
+               nouveau_bo_resize(nvbo, size);
+
+       if (data) {
+               if (nouveau_bo_map(nvbo, NOUVEAU_BO_WR))
+                       return;
+               memcpy(nvbo->map, data, size);
+               nouveau_bo_unmap(nvbo);
+       }
+}
+
+static void
+nouveau_pipe_bo_subdata(struct pipe_winsys *pws, struct pipe_buffer_handle *bo,
+                       unsigned long offset, unsigned long size,
+                       const void *data)
+{
+       struct nouveau_bo *nvbo = (struct nouveau_bo *)bo;
+
+       if (nouveau_bo_map(nvbo, NOUVEAU_BO_WR))
+               return;
+       memcpy(nvbo->map + offset, data, size);
+       nouveau_bo_unmap(nvbo);
+}
+
+static void
+nouveau_pipe_bo_get_subdata(struct pipe_winsys *pws,
+                           struct pipe_buffer_handle *bo, unsigned long offset,
+                           unsigned long size, void *data)
+{
+       struct nouveau_bo *nvbo = (struct nouveau_bo *)bo;
+
+       if (nouveau_bo_map(nvbo, NOUVEAU_BO_RD))
+               return;
+       memcpy(data, nvbo->map + offset, size);
+       nouveau_bo_unmap(nvbo);
+}
+
+struct pipe_winsys *
+nouveau_create_pipe_winsys(struct nouveau_context *nv)
+{
+       struct nouveau_pipe_winsys *nvpws;
+       struct pipe_winsys *pws;
+
+       nvpws = CALLOC_STRUCT(nouveau_pipe_winsys);
+       if (!nvpws)
+               return NULL;
+       nvpws->nv = nv;
+       pws = &nvpws->pws;
+
+       pws->flush_frontbuffer = nouveau_flush_frontbuffer;
+       pws->printf = nouveau_printf;
+
+       pws->region_alloc = nouveau_region_alloc;
+       pws->region_release = nouveau_region_release;
+
+       pws->surface_alloc = nouveau_surface_alloc;
+       pws->surface_release = nouveau_surface_release;
+
+       pws->buffer_create = nouveau_pipe_bo_create;
+       pws->user_buffer_create = nouveau_pipe_bo_user_create;
+       pws->buffer_map = nouveau_pipe_bo_map;
+       pws->buffer_unmap = nouveau_pipe_bo_unmap;
+       pws->buffer_reference = nouveau_pipe_bo_reference;
+       pws->buffer_data = nouveau_pipe_bo_data;
+       pws->buffer_subdata = nouveau_pipe_bo_subdata;
+       pws->buffer_get_subdata= nouveau_pipe_bo_get_subdata;
+
+       pws->get_name = nouveau_get_name;
+
+       return &nvpws->pws;
+}
+

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_winsys_pipe.h b/src/mesa/drivers/dri/nouveau_winsys/nouveau_winsys_pipe.h
new file mode 100644 (file)
index 0000000..bcac608
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_winsys_pipe.h
@@ -0,0 +1,23 @@
+#ifndef NOUVEAU_PIPE_WINSYS_H
+#define NOUVEAU_PIPE_WINSYS_H
+
+#include "pipe/p_context.h"
+#include "pipe/p_winsys.h"
+#include "nouveau_context.h"
+
+struct nouveau_pipe_winsys {
+       struct pipe_winsys pws;
+
+       struct nouveau_context *nv;
+};
+
+extern struct pipe_winsys *
+nouveau_create_pipe_winsys(struct nouveau_context *nv);
+
+struct pipe_context *
+nouveau_create_softpipe(struct nouveau_context *nv);
+
+struct pipe_context *
+nouveau_pipe_create(struct nouveau_context *nv);
+
+#endif

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nouveau_winsys_softpipe.c b/src/mesa/drivers/dri/nouveau_winsys/nouveau_winsys_softpipe.c
new file mode 100644 (file)
index 0000000..c86575f
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nouveau_winsys_softpipe.c
@@ -0,0 +1,82 @@
+/**************************************************************************
+ * 
+ * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
+ * All Rights Reserved.
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ * 
+ * 
+ **************************************************************************/
+/*
+ * Authors: Keith Whitwell <keithw-at-tungstengraphics-dot-com>
+ */
+
+#include "imports.h"
+
+#include "pipe/softpipe/sp_winsys.h"
+#include "pipe/p_defines.h"
+
+#include "nouveau_context.h"
+#include "nouveau_winsys_pipe.h"
+
+struct nouveau_softpipe_winsys {
+   struct softpipe_winsys sws;
+   struct nouveau_context *nv;
+};
+
+/**
+ * Return list of surface formats supported by this driver.
+ */
+static boolean
+nouveau_is_format_supported(struct softpipe_winsys *sws, uint format)
+{
+       switch (format) {
+       case PIPE_FORMAT_U_A8_R8_G8_B8:
+       case PIPE_FORMAT_U_R5_G6_B5:
+       case PIPE_FORMAT_S8_Z24:
+               return TRUE;
+       default:
+               break;
+       };
+
+       return FALSE;
+}
+
+
+
+struct pipe_context *
+nouveau_create_softpipe(struct nouveau_context *nv)
+{
+   struct nouveau_softpipe_winsys *nvsws;
+   
+   nvsws = CALLOC_STRUCT(nouveau_softpipe_winsys);
+   
+   /* Fill in this struct with callbacks that softpipe will need to
+    * communicate with the window system, buffer manager, etc. 
+    */
+   nvsws->sws.is_format_supported = nouveau_is_format_supported;
+   nvsws->nv = nv;
+
+   /* Create the softpipe context:
+    */
+   return softpipe_create(nouveau_create_pipe_winsys(nv), &nvsws->sws);
+}
+

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nv04_region.c b/src/mesa/drivers/dri/nouveau_winsys/nv04_region.c
new file mode 100644 (file)
index 0000000..cbe7098
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nv04_region.c
@@ -0,0 +1,163 @@
+#include "pipe/p_context.h"
+
+#include "nouveau_context.h"
+
+static INLINE int
+nv04_surface_format(int cpp)
+{
+       switch (cpp) {
+       case 1: return 0x1;
+       case 2: return 0x4;
+       case 4: return 0xb;
+       default:
+               return -1;
+       }
+}
+
+static INLINE int
+nv04_rect_format(int cpp)
+{
+       switch (cpp) {
+       case 1: return 0x3;
+       case 2: return 0x1;
+       case 4: return 0x3;
+       default:
+               return -1;
+       }
+}
+
+static int
+nv04_region_display(void)
+{
+       NOUVEAU_ERR("unimplemented\n");
+       return 0;
+}
+
+static int
+nv04_region_copy(struct nouveau_context *nv, struct pipe_region *dst,
+                unsigned dst_offset, unsigned dx, unsigned dy,
+                struct pipe_region *src, unsigned src_offset,
+                unsigned sx, unsigned sy, unsigned w, unsigned h)
+{
+       int format;
+
+       if (src->cpp != dst->cpp)
+               return 1;
+
+       if ((format = nv04_surface_format(dst->cpp)) < 0) {
+               NOUVEAU_ERR("Bad cpp = %d\n", dst->cpp);
+               return 1;
+       }
+
+       BEGIN_RING(NvCtxSurf2D, 0x0184, 2);
+       OUT_RELOCo(src->buffer, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
+       OUT_RELOCo(dst->buffer, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+       BEGIN_RING(NvCtxSurf2D, 0x0300, 4);
+       OUT_RING  (format);
+       OUT_RING  (((dst->pitch * dst->cpp) << 16) | (src->pitch * src->cpp));
+       OUT_RELOCl(src->buffer, src_offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
+       OUT_RELOCl(dst->buffer, dst_offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+
+       BEGIN_RING(NvImageBlit, 0x0300, 3);
+       OUT_RING  ((sy << 16) | sx);
+       OUT_RING  ((dy << 16) | dx);
+       OUT_RING  (( h << 16) |  w);
+
+       return 0;
+}
+
+static int
+nv04_region_fill(struct nouveau_context *nv,
+                struct pipe_region *dst, unsigned dst_offset,
+                unsigned dx, unsigned dy, unsigned w, unsigned h,
+                unsigned value)
+{
+       int cs2d_format, gdirect_format;
+
+       if ((cs2d_format = nv04_surface_format(dst->cpp)) < 0) {
+               NOUVEAU_ERR("Bad cpp = %d\n", dst->cpp);
+               return 1;
+       }
+
+       if ((gdirect_format = nv04_rect_format(dst->cpp)) < 0) {
+               NOUVEAU_ERR("Bad cpp = %d\n", dst->cpp);
+               return 1;
+       }
+
+       BEGIN_RING(NvCtxSurf2D, 0x0184, 2);
+       OUT_RELOCo(dst->buffer, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+       OUT_RELOCo(dst->buffer, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+       BEGIN_RING(NvCtxSurf2D, 0x0300, 4);
+       OUT_RING  (cs2d_format);
+       OUT_RING  (((dst->pitch * dst->cpp) << 16) | (dst->pitch * dst->cpp));
+       OUT_RELOCl(dst->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+       OUT_RELOCl(dst->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+
+       BEGIN_RING(NvGdiRect, 0x0300, 1);
+       OUT_RING  (gdirect_format);
+       BEGIN_RING(NvGdiRect, 0x03fc, 1);
+       OUT_RING  (value);
+       BEGIN_RING(NvGdiRect, 0x0400, 2);
+       OUT_RING  ((dx << 16) | dy);
+       OUT_RING  (( w << 16) |  h);
+
+       return 0;
+}
+
+static int
+nv04_region_data(struct nouveau_context *nv, struct pipe_region *dst,
+                unsigned dst_offset, unsigned dx, unsigned dy,
+                const void *src, unsigned src_pitch,
+                unsigned sx, unsigned sy, unsigned w, unsigned h)
+{
+       NOUVEAU_ERR("unimplemented!!\n");
+       return 0;
+}
+
+int
+nouveau_region_init_nv04(struct nouveau_context *nv)
+{
+       int ret;
+
+       if ((ret = nouveau_grobj_alloc(nv->channel, nv->next_handle++, 0x62,
+                                      &nv->NvCtxSurf2D))) {
+               NOUVEAU_ERR("Error creating 2D surface object: %d\n", ret);
+               return 1;
+       }
+       BEGIN_RING(NvCtxSurf2D, 0x0184, 2);
+       OUT_RING  (nv->channel->vram->handle);
+       OUT_RING  (nv->channel->vram->handle);
+
+       if ((ret = nouveau_grobj_alloc(nv->channel, nv->next_handle++, 0x9f,
+                                      &nv->NvImageBlit))) {
+               NOUVEAU_ERR("Error creating blit object: %d\n", ret);
+               return 1;
+       }
+       BEGIN_RING(NvImageBlit, 0x0180, 1);
+       OUT_RING  (nv->sync_notifier->handle);
+       BEGIN_RING(NvImageBlit, 0x019c, 1);
+       OUT_RING  (nv->NvCtxSurf2D->handle);
+       BEGIN_RING(NvImageBlit, 0x02fc, 1);
+       OUT_RING  (3);
+
+       if ((ret = nouveau_grobj_alloc(nv->channel, nv->next_handle++, 0x4a,
+                                      &nv->NvGdiRect))) {
+               NOUVEAU_ERR("Error creating rect object: %d\n", ret);
+               return 1;
+       }
+       BEGIN_RING(NvGdiRect, 0x0180, 1);
+       OUT_RING  (nv->sync_notifier->handle);
+       BEGIN_RING(NvGdiRect, 0x0198, 1);
+       OUT_RING  (nv->NvCtxSurf2D->handle);
+       BEGIN_RING(NvGdiRect, 0x02fc, 1);
+       OUT_RING  (3);
+       BEGIN_RING(NvGdiRect, 0x0304, 1);
+       OUT_RING  (2);
+
+       nv->region_display = nv04_region_display;
+       nv->region_copy = nv04_region_copy;
+       nv->region_fill = nv04_region_fill;
+       nv->region_data = nv04_region_data;
+       return 0;
+}
+

diff --git a/src/mesa/drivers/dri/nouveau_winsys/nv50_region.c b/src/mesa/drivers/dri/nouveau_winsys/nv50_region.c
new file mode 100644 (file)
index 0000000..c7450c5
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau_winsys/nv50_region.c
@@ -0,0 +1,51 @@
+#include "pipe/p_context.h"
+
+#include "nouveau_context.h"
+
+static int
+nv50_region_display(void)
+{
+       NOUVEAU_ERR("unimplemented\n");
+       return 0;
+}
+
+static int
+nv50_region_copy(struct nouveau_context *nv, struct pipe_region *dst,
+                unsigned dst_offset, unsigned dx, unsigned dy,
+                struct pipe_region *src, unsigned src_offset,
+                unsigned sx, unsigned sy, unsigned w, unsigned h)
+{
+       NOUVEAU_ERR("unimplemented!!\n");
+       return 0;
+}
+
+static int
+nv50_region_fill(struct nouveau_context *nv,
+                struct pipe_region *dst, unsigned dst_offset,
+                unsigned dx, unsigned dy, unsigned w, unsigned h,
+                unsigned value)
+{
+       NOUVEAU_ERR("unimplemented!!\n");
+       return 0;
+}
+
+static int
+nv50_region_data(struct nouveau_context *nv, struct pipe_region *dst,
+                unsigned dst_offset, unsigned dx, unsigned dy,
+                const void *src, unsigned src_pitch,
+                unsigned sx, unsigned sy, unsigned w, unsigned h)
+{
+       NOUVEAU_ERR("unimplemented!!\n");
+       return 0;
+}
+
+int
+nouveau_region_init_nv50(struct nouveau_context *nv)
+{
+       nv->region_display = nv50_region_display;
+       nv->region_copy = nv50_region_copy;
+       nv->region_fill = nv50_region_fill;
+       nv->region_data = nv50_region_data;
+       return 0;
+}
+

diff --git a/src/mesa/pipe/Makefile b/src/mesa/pipe/Makefile
index d448f3f5a6a286aa3355c14e9a850e5273fb32e1..135f1fd19d702ea1bf2d661741c3b19749a692e7 100644 (file)
--- a/src/mesa/pipe/Makefile
+++ b/src/mesa/pipe/Makefile
@@ -2,6 +2,7 @@ default:
        cd softpipe ; make
        cd i915simple ; make
        cd failover ; make
+       cd nv40; make
 
 clean:
-       rm -f `find . -name \*.[oa]`
\ No newline at end of file
+       rm -f `find . -name \*.[oa]`

diff --git a/src/mesa/pipe/nouveau/nouveau_bo.h b/src/mesa/pipe/nouveau/nouveau_bo.h
new file mode 100644 (file)
index 0000000..2b57ee9
--- /dev/null
+++ b/src/mesa/pipe/nouveau/nouveau_bo.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2007 Nouveau Project
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef __NOUVEAU_BO_H__
+#define __NOUVEAU_BO_H__
+
+/* Relocation/Buffer type flags */
+#define NOUVEAU_BO_VRAM  (1 << 0)
+#define NOUVEAU_BO_GART  (1 << 1)
+#define NOUVEAU_BO_RD    (1 << 2)
+#define NOUVEAU_BO_WR    (1 << 3)
+#define NOUVEAU_BO_RDWR  (NOUVEAU_BO_RD | NOUVEAU_BO_WR)
+#define NOUVEAU_BO_MAP   (1 << 4)
+#define NOUVEAU_BO_PIN   (1 << 5)
+#define NOUVEAU_BO_LOW   (1 << 6)
+#define NOUVEAU_BO_HIGH  (1 << 7)
+#define NOUVEAU_BO_OR    (1 << 8)
+#define NOUVEAU_BO_LOCAL (1 << 9)
+
+struct nouveau_bo {
+       struct nouveau_device *device;
+       uint64_t handle;
+
+       uint64_t size;
+       void *map;
+
+       uint32_t flags;
+       uint64_t offset;
+};
+
+#endif

diff --git a/src/mesa/pipe/nouveau/nouveau_channel.h b/src/mesa/pipe/nouveau/nouveau_channel.h
new file mode 100644 (file)
index 0000000..eccc7b3
--- /dev/null
+++ b/src/mesa/pipe/nouveau/nouveau_channel.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2007 Nouveau Project
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef __NOUVEAU_CHANNEL_H__
+#define __NOUVEAU_CHANNEL_H__
+
+struct nouveau_channel {
+       struct nouveau_device *device;
+       int id;
+
+       struct nouveau_grobj *vram;
+       struct nouveau_grobj *gart;
+
+       void *user_private;
+       void (*hang_notify)(struct nouveau_channel *);
+};
+
+#endif

diff --git a/src/mesa/pipe/nouveau/nouveau_class.h b/src/mesa/pipe/nouveau/nouveau_class.h
new file mode 100644 (file)
index 0000000..94b667e
--- /dev/null
+++ b/src/mesa/pipe/nouveau/nouveau_class.h
@@ -0,0 +1,5261 @@
+#ifndef NOUVEAU_REG_H
+#define NOUVEAU_REG_H 1
+
+
+#define NV01_ROOT                                                              0x00000001
+
+
+
+#define NV01_CONTEXT_DMA                                                       0x00000002
+
+
+
+#define NV01_DEVICE                                                            0x00000003
+
+
+
+#define NV01_TIMER                                                             0x00000004
+
+#define  NV01_TIMER_SYNCHRONIZE                                                        0x00000100
+#define  NV01_TIMER_STOP_ALARM                                                 0x00000104
+#define  NV01_TIMER_DMA_NOTIFY                                                 0x00000180
+#define  NV01_TIMER_TIME(x)                                                    (0x00000300+((x)*4))
+#define  NV01_TIMER_TIME__SIZE                                                 0x00000002
+#define  NV01_TIMER_ALARM_NOTIFY                                               0x00000308
+
+
+#define NV_IMAGE_STENCIL                                                       0x00000010
+
+#define  NV_IMAGE_STENCIL_NOTIFY                                               0x00000104
+#define  NV_IMAGE_STENCIL_DMA_NOTIFY                                           0x00000180
+#define  NV_IMAGE_STENCIL_IMAGE_OUTPUT                                         0x00000200
+#define  NV_IMAGE_STENCIL_IMAGE_INPUT(x)                                       (0x00000204+((x)*4))
+#define  NV_IMAGE_STENCIL_IMAGE_INPUT__SIZE                                    0x00000002
+
+
+#define NV_IMAGE_BLEND_AND                                                     0x00000011
+
+#define  NV_IMAGE_BLEND_AND_NOP                                                        0x00000100
+#define  NV_IMAGE_BLEND_AND_NOTIFY                                             0x00000104
+#define  NV_IMAGE_BLEND_AND_DMA_NOTIFY                                         0x00000180
+#define  NV_IMAGE_BLEND_AND_IMAGE_OUTPUT                                       0x00000200
+#define  NV_IMAGE_BLEND_AND_BETA_INPUT                                         0x00000204
+#define  NV_IMAGE_BLEND_AND_IMAGE_INPUT                                                0x00000208
+
+
+#define NV01_CONTEXT_BETA1                                                     0x00000012
+
+#define  NV01_CONTEXT_BETA1_NOP                                                        0x00000100
+#define  NV01_CONTEXT_BETA1_NOTIFY                                             0x00000104
+#define  NV01_CONTEXT_BETA1_DMA_NOTIFY                                         0x00000180
+#define  NV01_CONTEXT_BETA1_BETA_1D31                                          0x00000300
+
+
+#define NV_IMAGE_ROP_AND                                                       0x00000013
+
+#define  NV_IMAGE_ROP_AND_NOTIFY                                               0x00000104
+#define  NV_IMAGE_ROP_AND_DMA_NOTIFY                                           0x00000180
+#define  NV_IMAGE_ROP_AND_IMAGE_OUTPUT                                         0x00000200
+#define  NV_IMAGE_ROP_AND_ROP_INPUT                                            0x00000204
+#define  NV_IMAGE_ROP_AND_IMAGE_INPUT(x)                                       (0x00000208+((x)*4))
+#define  NV_IMAGE_ROP_AND_IMAGE_INPUT__SIZE                                    0x00000002
+
+
+#define NV_IMAGE_COLOR_KEY                                                     0x00000015
+
+
+
+#define NV01_CONTEXT_COLOR_KEY                                                 0x00000017
+
+#define  NV01_CONTEXT_COLOR_KEY_NOTIFY                                         0x00000104
+#define  NV01_CONTEXT_COLOR_KEY_DMA_NOTIFY                                     0x00000180
+#define  NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT                                   0x00000300
+#define  NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X16A8Y8                           0x00000001
+#define  NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X24Y8                             0x00000002
+#define  NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X16A1R5G5B5                       0x00000003
+#define  NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X17R5G5B5                         0x00000004
+#define  NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_A8R8G8B8                          0x00000005
+#define  NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X8R8G8B8                          0x00000006
+#define  NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_A16Y16                            0x00000007
+#define  NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X16Y16                            0x00000008
+#define  NV01_CONTEXT_COLOR_KEY_COLOR                                          0x00000304
+
+
+#define NV01_CONTEXT_PATTERN                                                   0x00000018
+
+#define  NV01_CONTEXT_PATTERN_NOTIFY                                           0x00000104
+#define  NV01_CONTEXT_PATTERN_DMA_NOTIFY                                       0x00000180
+#define  NV01_CONTEXT_PATTERN_COLOR_FORMAT                                     0x00000300
+#define  NV01_CONTEXT_PATTERN_MONOCHROME_FORMAT                                        0x00000304
+#define  NV01_CONTEXT_PATTERN_SHAPE                                            0x00000308
+#define  NV01_CONTEXT_PATTERN_COLOR(x)                                         (0x00000310+((x)*4))
+#define  NV01_CONTEXT_PATTERN_COLOR__SIZE                                      0x00000002
+#define  NV01_CONTEXT_PATTERN_PATTERN(x)                                       (0x00000318+((x)*4))
+#define  NV01_CONTEXT_PATTERN_PATTERN__SIZE                                    0x00000002
+
+
+#define NV01_CONTEXT_CLIP_RECTANGLE                                            0x00000019
+
+#define  NV01_CONTEXT_CLIP_RECTANGLE_NOP                                       0x00000104
+#define  NV01_CONTEXT_CLIP_RECTANGLE_NOTIFY                                    0x00000104
+#define  NV01_CONTEXT_CLIP_RECTANGLE_DMA_NOTIFY                                        0x00000180
+#define  NV01_CONTEXT_CLIP_RECTANGLE_POINT                                     0x00000300
+#define   NV01_CONTEXT_CLIP_RECTANGLE_POINT_X_SHIFT                            0
+#define   NV01_CONTEXT_CLIP_RECTANGLE_POINT_X_MASK                             0x0000ffff
+#define   NV01_CONTEXT_CLIP_RECTANGLE_POINT_Y_SHIFT                            16
+#define   NV01_CONTEXT_CLIP_RECTANGLE_POINT_Y_MASK                             0xffff0000
+#define  NV01_CONTEXT_CLIP_RECTANGLE_SIZE                                      0x00000304
+#define   NV01_CONTEXT_CLIP_RECTANGLE_SIZE_W_SHIFT                             0
+#define   NV01_CONTEXT_CLIP_RECTANGLE_SIZE_W_MASK                              0x0000ffff
+#define   NV01_CONTEXT_CLIP_RECTANGLE_SIZE_H_SHIFT                             16
+#define   NV01_CONTEXT_CLIP_RECTANGLE_SIZE_H_MASK                              0xffff0000
+
+
+#define NV01_RENDER_SOLID_LINE                                                 0x0000001c
+
+#define  NV01_RENDER_SOLID_LINE_NOP                                            0x00000104
+#define  NV01_RENDER_SOLID_LINE_NOTIFY                                         0x00000104
+#define  NV01_RENDER_SOLID_LINE_PATCH                                          0x0000010c
+#define  NV01_RENDER_SOLID_LINE_DMA_NOTIFY                                     0x00000180
+#define  NV01_RENDER_SOLID_LINE_CLIP_RECTANGLE                                 0x00000184
+#define  NV01_RENDER_SOLID_LINE_PATTERN                                                0x00000188
+#define  NV01_RENDER_SOLID_LINE_ROP                                            0x0000018c
+#define  NV01_RENDER_SOLID_LINE_BETA1                                          0x00000190
+#define  NV01_RENDER_SOLID_LINE_SURFACE                                                0x00000194
+#define  NV01_RENDER_SOLID_LINE_OPERATION                                      0x000002fc
+#define  NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY_AND                          0x00000000
+#define  NV01_RENDER_SOLID_LINE_OPERATION_ROP_AND                              0x00000001
+#define  NV01_RENDER_SOLID_LINE_OPERATION_BLEND_AND                            0x00000002
+#define  NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY_PREMULT                      0x00000003
+#define  NV01_RENDER_SOLID_LINE_OPERATION_BLEND_PREMULT                                0x00000004
+#define  NV01_RENDER_SOLID_LINE_COLOR_FORMAT                                   0x00000300
+#define  NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X16A8Y8                           0x00000001
+#define  NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X24Y8                             0x00000002
+#define  NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X16A1R5G5B5                       0x00000003
+#define  NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X17R5G5B5                         0x00000004
+#define  NV01_RENDER_SOLID_LINE_COLOR_FORMAT_A8R8G8B8                          0x00000005
+#define  NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X8R8G8B8                          0x00000006
+#define  NV01_RENDER_SOLID_LINE_COLOR_FORMAT_A16Y16                            0x00000007
+#define  NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X16Y16                            0x00000008
+#define  NV01_RENDER_SOLID_LINE_COLOR                                          0x00000304
+#define  NV01_RENDER_SOLID_LINE_LINE_POINT0(x)                                 (0x00000400+((x)*8))
+#define  NV01_RENDER_SOLID_LINE_LINE_POINT0__SIZE                              0x00000010
+#define   NV01_RENDER_SOLID_LINE_LINE_POINT0_X_SHIFT                           0
+#define   NV01_RENDER_SOLID_LINE_LINE_POINT0_X_MASK                            0x0000ffff
+#define   NV01_RENDER_SOLID_LINE_LINE_POINT0_Y_SHIFT                           16
+#define   NV01_RENDER_SOLID_LINE_LINE_POINT0_Y_MASK                            0xffff0000
+#define  NV01_RENDER_SOLID_LINE_LINE_POINT1(x)                                 (0x00000404+((x)*8))
+#define  NV01_RENDER_SOLID_LINE_LINE_POINT1__SIZE                              0x00000010
+#define   NV01_RENDER_SOLID_LINE_LINE_POINT1_X_SHIFT                           0
+#define   NV01_RENDER_SOLID_LINE_LINE_POINT1_X_MASK                            0x0000ffff
+#define   NV01_RENDER_SOLID_LINE_LINE_POINT1_Y_SHIFT                           16
+#define   NV01_RENDER_SOLID_LINE_LINE_POINT1_Y_MASK                            0xffff0000
+#define  NV01_RENDER_SOLID_LINE_LINE32_POINT0_X(x)                             (0x00000480+((x)*16))
+#define  NV01_RENDER_SOLID_LINE_LINE32_POINT0_X__SIZE                          0x00000010
+#define  NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y(x)                             (0x00000484+((x)*16))
+#define  NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y__SIZE                          0x00000010
+#define  NV01_RENDER_SOLID_LINE_LINE32_POINT1_X(x)                             (0x00000488+((x)*16))
+#define  NV01_RENDER_SOLID_LINE_LINE32_POINT1_X__SIZE                          0x00000010
+#define  NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y(x)                             (0x0000048c+((x)*16))
+#define  NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y__SIZE                          0x00000010
+#define  NV01_RENDER_SOLID_LINE_POLYLINE(x)                                    (0x00000500+((x)*4))
+#define  NV01_RENDER_SOLID_LINE_POLYLINE__SIZE                                 0x00000020
+#define   NV01_RENDER_SOLID_LINE_POLYLINE_X_SHIFT                              0
+#define   NV01_RENDER_SOLID_LINE_POLYLINE_X_MASK                               0x0000ffff
+#define   NV01_RENDER_SOLID_LINE_POLYLINE_Y_SHIFT                              16
+#define   NV01_RENDER_SOLID_LINE_POLYLINE_Y_MASK                               0xffff0000
+#define  NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X(x)                          (0x00000580+((x)*8))
+#define  NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X__SIZE                       0x00000010
+#define  NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y(x)                          (0x00000584+((x)*8))
+#define  NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y__SIZE                       0x00000010
+#define  NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR(x)                             (0x00000600+((x)*8))
+#define  NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR__SIZE                          0x00000010
+#define  NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT(x)                             (0x00000604+((x)*8))
+#define  NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT__SIZE                          0x00000010
+#define   NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_X_SHIFT                       0
+#define   NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_X_MASK                                0x0000ffff
+#define   NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_Y_SHIFT                       16
+#define   NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_Y_MASK                                0xffff0000
+
+
+#define NV01_RENDER_SOLID_TRIANGLE                                             0x0000001d
+
+#define  NV01_RENDER_SOLID_TRIANGLE_NOP                                                0x00000100
+#define  NV01_RENDER_SOLID_TRIANGLE_NOTIFY                                     0x00000104
+#define  NV01_RENDER_SOLID_TRIANGLE_PATCH                                      0x0000010c
+#define  NV01_RENDER_SOLID_TRIANGLE_DMA_NOTIFY                                 0x00000180
+#define  NV01_RENDER_SOLID_TRIANGLE_CLIP_RECTANGLE                             0x00000184
+#define  NV01_RENDER_SOLID_TRIANGLE_PATTERN                                    0x00000188
+#define  NV01_RENDER_SOLID_TRIANGLE_ROP                                                0x0000018c
+#define  NV01_RENDER_SOLID_TRIANGLE_BETA1                                      0x00000190
+#define  NV01_RENDER_SOLID_TRIANGLE_SURFACE                                    0x00000194
+#define  NV01_RENDER_SOLID_TRIANGLE_OPERATION                                  0x000002fc
+#define  NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY_AND                      0x00000000
+#define  NV01_RENDER_SOLID_TRIANGLE_OPERATION_ROP_AND                          0x00000001
+#define  NV01_RENDER_SOLID_TRIANGLE_OPERATION_BLEND_AND                                0x00000002
+#define  NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY_PREMULT                  0x00000003
+#define  NV01_RENDER_SOLID_TRIANGLE_OPERATION_BLEND_PREMULT                    0x00000004
+#define  NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT                               0x00000300
+#define  NV01_RENDER_SOLID_TRIANGLE_COLOR                                      0x00000304
+#define  NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0                            0x00000310
+#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_X_SHIFT                   0
+#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_X_MASK                    0x0000ffff
+#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_Y_SHIFT                   16
+#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_Y_MASK                    0xffff0000
+#define  NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1                            0x00000314
+#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_X_SHIFT                   0
+#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_X_MASK                    0x0000ffff
+#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_Y_SHIFT                   16
+#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_Y_MASK                    0xffff0000
+#define  NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2                            0x00000318
+#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_X_SHIFT                   0
+#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_X_MASK                    0x0000ffff
+#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_Y_SHIFT                   16
+#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_Y_MASK                    0xffff0000
+#define  NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT0_X                                0x00000320
+#define  NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT0_Y                                0x00000324
+#define  NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT1_X                                0x00000328
+#define  NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT1_Y                                0x0000032c
+#define  NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT2_X                                0x00000330
+#define  NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT2_Y                                0x00000334
+#define  NV01_RENDER_SOLID_TRIANGLE_TRIMESH(x)                                 (0x00000400+((x)*4))
+#define  NV01_RENDER_SOLID_TRIANGLE_TRIMESH__SIZE                              0x00000020
+#define   NV01_RENDER_SOLID_TRIANGLE_TRIMESH_X_SHIFT                           0
+#define   NV01_RENDER_SOLID_TRIANGLE_TRIMESH_X_MASK                            0x0000ffff
+#define   NV01_RENDER_SOLID_TRIANGLE_TRIMESH_Y_SHIFT                           16
+#define   NV01_RENDER_SOLID_TRIANGLE_TRIMESH_Y_MASK                            0xffff0000
+#define  NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X(x)                       (0x00000480+((x)*8))
+#define  NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X__SIZE                    0x00000010
+#define  NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y(x)                       (0x00000484+((x)*8))
+#define  NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y__SIZE                    0x00000010
+#define  NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR(x)                         (0x00000500+((x)*16))
+#define  NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR__SIZE                      0x00000008
+#define  NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0(x)                                (0x00000504+((x)*16))
+#define  NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0__SIZE                     0x00000008
+#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_X_SHIFT                  0
+#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_X_MASK                   0x0000ffff
+#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_Y_SHIFT                  16
+#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_Y_MASK                   0xffff0000
+#define  NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1(x)                                (0x00000508+((x)*16))
+#define  NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1__SIZE                     0x00000008
+#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_X_SHIFT                  0
+#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_X_MASK                   0x0000ffff
+#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_Y_SHIFT                  16
+#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_Y_MASK                   0xffff0000
+#define  NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2(x)                                (0x0000050c+((x)*16))
+#define  NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2__SIZE                     0x00000008
+#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_X_SHIFT                  0
+#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_X_MASK                   0x0000ffff
+#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_Y_SHIFT                  16
+#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_Y_MASK                   0xffff0000
+#define  NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR(x)                          (0x00000580+((x)*8))
+#define  NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR__SIZE                       0x00000010
+#define  NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT(x)                          (0x00000584+((x)*8))
+#define  NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT__SIZE                       0x00000010
+#define   NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_X_SHIFT                    0
+#define   NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_X_MASK                     0x0000ffff
+#define   NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_Y_SHIFT                    16
+#define   NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_Y_MASK                     0xffff0000
+
+
+#define NV01_RENDER_SOLID_RECTANGLE                                            0x0000001e
+
+#define  NV01_RENDER_SOLID_RECTANGLE_NOP                                       0x00000100
+#define  NV01_RENDER_SOLID_RECTANGLE_NOTIFY                                    0x00000104
+#define  NV01_RENDER_SOLID_RECTANGLE_PATCH                                     0x0000010c
+#define  NV01_RENDER_SOLID_RECTANGLE_DMA_NOTIFY                                        0x00000180
+#define  NV01_RENDER_SOLID_RECTANGLE_CLIP_RECTANGLE                            0x00000184
+#define  NV01_RENDER_SOLID_RECTANGLE_PATTERN                                   0x00000188
+#define  NV01_RENDER_SOLID_RECTANGLE_ROP                                       0x0000018c
+#define  NV01_RENDER_SOLID_RECTANGLE_BETA1                                     0x00000190
+#define  NV01_RENDER_SOLID_RECTANGLE_SURFACE                                   0x00000194
+#define  NV01_RENDER_SOLID_RECTANGLE_OPERATION                                 0x000002fc
+#define  NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY_AND                     0x00000000
+#define  NV01_RENDER_SOLID_RECTANGLE_OPERATION_ROP_AND                         0x00000001
+#define  NV01_RENDER_SOLID_RECTANGLE_OPERATION_BLEND_AND                       0x00000002
+#define  NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY_PREMULT                 0x00000003
+#define  NV01_RENDER_SOLID_RECTANGLE_OPERATION_BLEND_PREMULT                   0x00000004
+#define  NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT                              0x00000300
+#define  NV01_RENDER_SOLID_RECTANGLE_COLOR                                     0x00000304
+#define  NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT(x)                                (0x00000400+((x)*8))
+#define  NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT__SIZE                     0x00000010
+#define   NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_X_SHIFT                  0
+#define   NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_X_MASK                   0x0000ffff
+#define   NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_Y_SHIFT                  16
+#define   NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_Y_MASK                   0xffff0000
+#define  NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE(x)                         (0x00000404+((x)*8))
+#define  NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE__SIZE                      0x00000010
+#define   NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_W_SHIFT                   0
+#define   NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_W_MASK                    0x0000ffff
+#define   NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_H_SHIFT                   16
+#define   NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_H_MASK                    0xffff0000
+
+
+#define NV01_IMAGE_BLIT                                                                0x0000001f
+
+#define  NV01_IMAGE_BLIT_NOP                                                   0x00000100
+#define  NV01_IMAGE_BLIT_NOTIFY                                                        0x00000104
+#define  NV01_IMAGE_BLIT_PATCH                                                 0x0000010c
+#define  NV01_IMAGE_BLIT_DMA_NOTIFY                                            0x00000180
+#define  NV01_IMAGE_BLIT_COLOR_KEY                                             0x00000184
+#define  NV01_IMAGE_BLIT_CLIP_RECTANGLE                                                0x00000188
+#define  NV01_IMAGE_BLIT_PATTERN                                               0x0000018c
+#define  NV01_IMAGE_BLIT_ROP                                                   0x00000190
+#define  NV01_IMAGE_BLIT_BETA1                                                 0x00000194
+#define  NV01_IMAGE_BLIT_SURFACE                                               0x0000019c
+#define  NV01_IMAGE_BLIT_OPERATION                                             0x000002fc
+#define  NV01_IMAGE_BLIT_IMAGE_INPUT                                           0x00000204
+#define  NV01_IMAGE_BLIT_POINT_IN                                              0x00000300
+#define   NV01_IMAGE_BLIT_POINT_IN_X_SHIFT                                     0
+#define   NV01_IMAGE_BLIT_POINT_IN_X_MASK                                      0x0000ffff
+#define   NV01_IMAGE_BLIT_POINT_IN_Y_SHIFT                                     16
+#define   NV01_IMAGE_BLIT_POINT_IN_Y_MASK                                      0xffff0000
+#define  NV01_IMAGE_BLIT_POINT_OUT                                             0x00000304
+#define   NV01_IMAGE_BLIT_POINT_OUT_X_SHIFT                                    0
+#define   NV01_IMAGE_BLIT_POINT_OUT_X_MASK                                     0x0000ffff
+#define   NV01_IMAGE_BLIT_POINT_OUT_Y_SHIFT                                    16
+#define   NV01_IMAGE_BLIT_POINT_OUT_Y_MASK                                     0xffff0000
+#define  NV01_IMAGE_BLIT_SIZE                                                  0x00000308
+#define   NV01_IMAGE_BLIT_SIZE_W_SHIFT                                         0
+#define   NV01_IMAGE_BLIT_SIZE_W_MASK                                          0x0000ffff
+#define   NV01_IMAGE_BLIT_SIZE_H_SHIFT                                         16
+#define   NV01_IMAGE_BLIT_SIZE_H_MASK                                          0xffff0000
+
+
+#define NV01_IMAGE_FROM_CPU                                                    0x00000021
+
+#define  NV01_IMAGE_FROM_CPU_NOP                                               0x00000100
+#define  NV01_IMAGE_FROM_CPU_NOTIFY                                            0x00000104
+#define  NV01_IMAGE_FROM_CPU_PATCH                                             0x0000010c
+#define  NV01_IMAGE_FROM_CPU_DMA_NOTIFY                                                0x00000180
+#define  NV01_IMAGE_FROM_CPU_COLOR_KEY                                         0x00000184
+#define  NV01_IMAGE_FROM_CPU_CLIP_RECTANGLE                                    0x00000188
+#define  NV01_IMAGE_FROM_CPU_PATTERN                                           0x0000018c
+#define  NV01_IMAGE_FROM_CPU_ROP                                               0x00000190
+#define  NV01_IMAGE_FROM_CPU_BETA1                                             0x00000194
+#define  NV01_IMAGE_FROM_CPU_SURFACE                                           0x00000198
+#define  NV01_IMAGE_FROM_CPU_OPERATION                                         0x000002fc
+#define  NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY_AND                             0x00000000
+#define  NV01_IMAGE_FROM_CPU_OPERATION_ROP_AND                                 0x00000001
+#define  NV01_IMAGE_FROM_CPU_OPERATION_BLEND_AND                               0x00000002
+#define  NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY_PREMULT                         0x00000003
+#define  NV01_IMAGE_FROM_CPU_OPERATION_BLEND_PREMULT                           0x00000004
+#define  NV01_IMAGE_FROM_CPU_COLOR_FORMAT                                      0x00000300
+#define  NV01_IMAGE_FROM_CPU_COLOR_FORMAT_Y8                                   0x00000001
+#define  NV01_IMAGE_FROM_CPU_COLOR_FORMAT_A1R5G5B5                             0x00000002
+#define  NV01_IMAGE_FROM_CPU_COLOR_FORMAT_X1R5G5B5                             0x00000003
+#define  NV01_IMAGE_FROM_CPU_COLOR_FORMAT_A8R8G8B8                             0x00000004
+#define  NV01_IMAGE_FROM_CPU_COLOR_FORMAT_X8R8G8B8                             0x00000005
+#define  NV01_IMAGE_FROM_CPU_POINT                                             0x00000304
+#define   NV01_IMAGE_FROM_CPU_POINT_X_SHIFT                                    0
+#define   NV01_IMAGE_FROM_CPU_POINT_X_MASK                                     0x0000ffff
+#define   NV01_IMAGE_FROM_CPU_POINT_Y_SHIFT                                    16
+#define   NV01_IMAGE_FROM_CPU_POINT_Y_MASK                                     0xffff0000
+#define  NV01_IMAGE_FROM_CPU_SIZE_OUT                                          0x00000308
+#define   NV01_IMAGE_FROM_CPU_SIZE_OUT_W_SHIFT                                 0
+#define   NV01_IMAGE_FROM_CPU_SIZE_OUT_W_MASK                                  0x0000ffff
+#define   NV01_IMAGE_FROM_CPU_SIZE_OUT_H_SHIFT                                 16
+#define   NV01_IMAGE_FROM_CPU_SIZE_OUT_H_MASK                                  0xffff0000
+#define  NV01_IMAGE_FROM_CPU_SIZE_IN                                           0x0000030c
+#define   NV01_IMAGE_FROM_CPU_SIZE_IN_W_SHIFT                                  0
+#define   NV01_IMAGE_FROM_CPU_SIZE_IN_W_MASK                                   0x0000ffff
+#define   NV01_IMAGE_FROM_CPU_SIZE_IN_H_SHIFT                                  16
+#define   NV01_IMAGE_FROM_CPU_SIZE_IN_H_MASK                                   0xffff0000
+#define  NV01_IMAGE_FROM_CPU_COLOR(x)                                          (0x00000400+((x)*4))
+#define  NV01_IMAGE_FROM_CPU_COLOR__SIZE                                       0x00000020
+
+
+#define NV01_NULL                                                              0x00000030
+
+
+
+#define NV03_STRETCHED_IMAGE_FROM_CPU                                          0x00000036
+
+#define  NV03_STRETCHED_IMAGE_FROM_CPU_NOP                                     0x00000100
+#define  NV03_STRETCHED_IMAGE_FROM_CPU_NOTIFY                                  0x00000104
+#define  NV03_STRETCHED_IMAGE_FROM_CPU_PATCH                                   0x0000010c
+#define  NV03_STRETCHED_IMAGE_FROM_CPU_DMA_NOTIFY                              0x00000180
+#define  NV03_STRETCHED_IMAGE_FROM_CPU_COLOR_KEY                               0x00000184
+#define  NV03_STRETCHED_IMAGE_FROM_CPU_PATTERN                                 0x00000188
+#define  NV03_STRETCHED_IMAGE_FROM_CPU_ROP                                     0x0000018c
+#define  NV03_STRETCHED_IMAGE_FROM_CPU_BETA1                                   0x00000190
+#define  NV03_STRETCHED_IMAGE_FROM_CPU_SURFACE                                 0x00000194
+#define  NV03_STRETCHED_IMAGE_FROM_CPU_OPERATION                               0x000002fc
+#define  NV03_STRETCHED_IMAGE_FROM_CPU_COLOR_FORMAT                            0x00000300
+#define  NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN                                 0x00000304
+#define   NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_W_SHIFT                                0
+#define   NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_W_MASK                         0x0000ffff
+#define   NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_H_SHIFT                                16
+#define   NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_H_MASK                         0xffff0000
+#define  NV03_STRETCHED_IMAGE_FROM_CPU_DX_DU                                   0x00000308
+#define  NV03_STRETCHED_IMAGE_FROM_CPU_DY_DV                                   0x0000030c
+#define  NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT                              0x00000310
+#define   NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_X_SHIFT                     0
+#define   NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_X_MASK                      0x0000ffff
+#define   NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_Y_SHIFT                     16
+#define   NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_Y_MASK                      0xffff0000
+#define  NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE                               0x00000314
+#define   NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_W_SHIFT                      0
+#define   NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_W_MASK                       0x0000ffff
+#define   NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_H_SHIFT                      16
+#define   NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_H_MASK                       0xffff0000
+#define  NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4                               0x00000318
+#define   NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_X_SHIFT                      0
+#define   NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_X_MASK                       0x0000ffff
+#define   NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_Y_SHIFT                      16
+#define   NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_Y_MASK                       0xffff0000
+#define  NV03_STRETCHED_IMAGE_FROM_CPU_COLOR(x)                                        (0x00000400+((x)*4))
+#define  NV03_STRETCHED_IMAGE_FROM_CPU_COLOR__SIZE                             0x00000020
+
+
+#define NV03_SCALED_IMAGE_FROM_MEMORY                                          0x00000037
+
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_NOP                                     0x00000100
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_NOTIFY                                  0x00000104
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_DMA_NOTIFY                              0x00000180
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE                               0x00000184
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_PATTERN                                 0x00000188
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_ROP                                     0x0000018c
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_BETA1                                   0x00000190
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_SURFACE                                 0x00000194
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT                            0x00000300
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5                   0x00000001
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X1R5G5B5                   0x00000002
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8                   0x00000003
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8                   0x00000004
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_V8YB8U8YA8                 0x00000005
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_YB8V8YA8U8                 0x00000006
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5                     0x00000007
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8                         0x00000008
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_AY8                                0x00000009
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION                               0x00000304
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_AND                   0x00000000
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_ROP_AND                       0x00000001
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_AND                     0x00000002
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_PREMULT               0x00000003
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_PREMULT                 0x00000004
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT                              0x00000308
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X_SHIFT                     0
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X_MASK                      0x0000ffff
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_SHIFT                     16
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_MASK                      0xffff0000
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE                               0x0000030c
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W_SHIFT                      0
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W_MASK                       0x0000ffff
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_SHIFT                      16
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_MASK                       0xffff0000
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_POINT                         0x00000310
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_POINT_X_SHIFT                        0
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_POINT_X_MASK                 0x0000ffff
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_POINT_Y_SHIFT                        16
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_POINT_Y_MASK                 0xffff0000
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_SIZE                          0x00000314
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_SIZE_W_SHIFT                 0
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_SIZE_W_MASK                  0x0000ffff
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_SIZE_H_SHIFT                 16
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_SIZE_H_MASK                  0xffff0000
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_DELTA_DU_DX                             0x00000318
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_DELTA_DV_DY                             0x0000031c
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_SIZE                           0x00000400
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_SIZE_W_SHIFT                  0
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_SIZE_W_MASK                   0x0000ffff
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_SIZE_H_SHIFT                  16
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_SIZE_H_MASK                   0xffff0000
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT                         0x00000404
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_PITCH_SHIFT            0
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_PITCH_MASK             0x0000ffff
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_ORIGIN_SHIFT           16
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_ORIGIN_MASK            0x00ff0000
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_ORIGIN_CENTER          0x00000001
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_ORIGIN_CORNER          0x00000002
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_INTERPOLATOR_SHIFT     24
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_INTERPOLATOR_MASK      0xff000000
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_OFFSET                         0x00000408
+#define  NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_POINT                          0x0000040c
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_POINT_U_SHIFT                 0
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_POINT_U_MASK                  0x0000ffff
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_POINT_V_SHIFT                 16
+#define   NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_POINT_V_MASK                  0xffff0000
+
+
+#define NV04_DVD_SUBPICTURE                                                    0x00000038
+
+#define  NV04_DVD_SUBPICTURE_NOP                                               0x00000100
+#define  NV04_DVD_SUBPICTURE_NOTIFY                                            0x00000104
+#define  NV04_DVD_SUBPICTURE_WAIT_FOR_IDLE                                     0x00000108
+#define  NV04_DVD_SUBPICTURE_DMA_NOTIFY                                                0x00000180
+#define  NV04_DVD_SUBPICTURE_DMA_OVERLAY                                       0x00000184
+#define  NV04_DVD_SUBPICTURE_DMA_IMAGEIN                                       0x00000188
+#define  NV04_DVD_SUBPICTURE_DMA_IMAGEOUT                                      0x0000018c
+#define  NV04_DVD_SUBPICTURE_IMAGEOUT_POINT                                    0x00000300
+#define   NV04_DVD_SUBPICTURE_IMAGEOUT_POINT_X_SHIFT                           0
+#define   NV04_DVD_SUBPICTURE_IMAGEOUT_POINT_X_MASK                            0x0000ffff
+#define   NV04_DVD_SUBPICTURE_IMAGEOUT_POINT_Y_SHIFT                           16
+#define   NV04_DVD_SUBPICTURE_IMAGEOUT_POINT_Y_MASK                            0xffff0000
+#define  NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE                                     0x00000304
+#define   NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE_W_SHIFT                            0
+#define   NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE_W_MASK                             0x0000ffff
+#define   NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE_H_SHIFT                            16
+#define   NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE_H_MASK                             0xffff0000
+#define  NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT                                   0x00000308
+#define   NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT_PITCH_SHIFT                      0
+#define   NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT_PITCH_MASK                       0x0000ffff
+#define   NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT_COLOR_SHIFT                      16
+#define   NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT_COLOR_MASK                       0xffff0000
+#define  NV04_DVD_SUBPICTURE_IMAGEOUT_OFFSET                                   0x0000030c
+#define  NV04_DVD_SUBPICTURE_IMAGEIN_DELTA_DU_DX                               0x00000310
+#define  NV04_DVD_SUBPICTURE_IMAGEIN_DELTA_DV_DY                               0x00000314
+#define  NV04_DVD_SUBPICTURE_IMAGEIN_SIZE                                      0x00000318
+#define   NV04_DVD_SUBPICTURE_IMAGEIN_SIZE_W_SHIFT                             0
+#define   NV04_DVD_SUBPICTURE_IMAGEIN_SIZE_W_MASK                              0x0000ffff
+#define   NV04_DVD_SUBPICTURE_IMAGEIN_SIZE_H_SHIFT                             16
+#define   NV04_DVD_SUBPICTURE_IMAGEIN_SIZE_H_MASK                              0xffff0000
+#define  NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT                                    0x0000031c
+#define   NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT_PITCH_SHIFT                       0
+#define   NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT_PITCH_MASK                                0x0000ffff
+#define   NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT_COLOR_SHIFT                       16
+#define   NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT_COLOR_MASK                                0xffff0000
+#define  NV04_DVD_SUBPICTURE_IMAGEIN_OFFSET                                    0x00000320
+#define  NV04_DVD_SUBPICTURE_IMAGEIN_POINT                                     0x00000324
+#define   NV04_DVD_SUBPICTURE_IMAGEIN_POINT_U_SHIFT                            0
+#define   NV04_DVD_SUBPICTURE_IMAGEIN_POINT_U_MASK                             0x0000ffff
+#define   NV04_DVD_SUBPICTURE_IMAGEIN_POINT_V_SHIFT                            16
+#define   NV04_DVD_SUBPICTURE_IMAGEIN_POINT_V_MASK                             0xffff0000
+#define  NV04_DVD_SUBPICTURE_OVERLAY_DELTA_DU_DX                               0x00000328
+#define  NV04_DVD_SUBPICTURE_OVERLAY_DELTA_DV_DY                               0x0000032c
+#define  NV04_DVD_SUBPICTURE_OVERLAY_SIZE                                      0x00000330
+#define   NV04_DVD_SUBPICTURE_OVERLAY_SIZE_W_SHIFT                             0
+#define   NV04_DVD_SUBPICTURE_OVERLAY_SIZE_W_MASK                              0x0000ffff
+#define   NV04_DVD_SUBPICTURE_OVERLAY_SIZE_H_SHIFT                             16
+#define   NV04_DVD_SUBPICTURE_OVERLAY_SIZE_H_MASK                              0xffff0000
+#define  NV04_DVD_SUBPICTURE_OVERLAY_FORMAT                                    0x00000334
+#define   NV04_DVD_SUBPICTURE_OVERLAY_FORMAT_PITCH_SHIFT                       0
+#define   NV04_DVD_SUBPICTURE_OVERLAY_FORMAT_PITCH_MASK                                0x0000ffff
+#define   NV04_DVD_SUBPICTURE_OVERLAY_FORMAT_COLOR_SHIFT                       16
+#define   NV04_DVD_SUBPICTURE_OVERLAY_FORMAT_COLOR_MASK                                0xffff0000
+#define  NV04_DVD_SUBPICTURE_OVERLAY_OFFSET                                    0x00000338
+#define  NV04_DVD_SUBPICTURE_OVERLAY_POINT                                     0x0000033c
+#define   NV04_DVD_SUBPICTURE_OVERLAY_POINT_U_SHIFT                            0
+#define   NV04_DVD_SUBPICTURE_OVERLAY_POINT_U_MASK                             0x0000ffff
+#define   NV04_DVD_SUBPICTURE_OVERLAY_POINT_V_SHIFT                            16
+#define   NV04_DVD_SUBPICTURE_OVERLAY_POINT_V_MASK                             0xffff0000
+
+
+#define NV_MEMORY_TO_MEMORY_FORMAT                                             0x00000039
+
+#define  NV_MEMORY_TO_MEMORY_FORMAT_NOP                                                0x00000100
+#define  NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY                                     0x00000104
+#define  NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY                                 0x00000180
+#define  NV_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN                              0x00000184
+#define  NV_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_OUT                             0x00000188
+#define  NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN                                  0x0000030c
+#define  NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT                                 0x00000310
+#define  NV_MEMORY_TO_MEMORY_FORMAT_PITCH_IN                                   0x00000314
+#define  NV_MEMORY_TO_MEMORY_FORMAT_PITCH_OUT                                  0x00000318
+#define  NV_MEMORY_TO_MEMORY_FORMAT_LINE_LENGTH_IN                             0x0000031c
+#define  NV_MEMORY_TO_MEMORY_FORMAT_LINE_COUNT                                 0x00000320
+#define  NV_MEMORY_TO_MEMORY_FORMAT_FORMAT                                     0x00000324
+#define   NV_MEMORY_TO_MEMORY_FORMAT_FORMAT_INPUT_INC_SHIFT                    0
+#define   NV_MEMORY_TO_MEMORY_FORMAT_FORMAT_INPUT_INC_MASK                     0x0000000f
+#define   NV_MEMORY_TO_MEMORY_FORMAT_FORMAT_OUTPUT_INC_SHIFT                   8
+#define   NV_MEMORY_TO_MEMORY_FORMAT_FORMAT_OUTPUT_INC_MASK                    0x00000f00
+#define  NV_MEMORY_TO_MEMORY_FORMAT_BUF_NOTIFY                                 0x00000328
+
+
+#define NV01_MEMORY_LOCAL_BANKED                                               0x0000003d
+
+
+
+#define NV01_MAPPING_SYSTEM                                                    0x0000003e
+
+
+
+#define NV03_MEMORY_LOCAL_CURSOR                                               0x0000003f
+
+
+
+#define NV01_MEMORY_LOCAL_LINEAR                                               0x00000040
+
+
+
+#define NV01_MAPPING_LOCAL                                                     0x00000041
+
+
+
+#define NV04_CONTEXT_SURFACES_2D                                               0x00000042
+
+#define  NV04_CONTEXT_SURFACES_2D_NOP                                          0x00000100
+#define  NV04_CONTEXT_SURFACES_2D_NOTIFY                                       0x00000104
+#define  NV04_CONTEXT_SURFACES_2D_PM_TRIGGER                                   0x00000140
+#define  NV04_CONTEXT_SURFACES_2D_DMA_NOTIFY                                   0x00000180
+#define  NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE                             0x00000184
+#define  NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_DESTIN                             0x00000188
+#define  NV04_CONTEXT_SURFACES_2D_FORMAT                                       0x00000300
+#define  NV04_CONTEXT_SURFACES_2D_FORMAT_Y8                                    0x00000001
+#define  NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_Z1R5G5B5                     0x00000002
+#define  NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_X1R5G5B5                     0x00000003
+#define  NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5                                        0x00000004
+#define  NV04_CONTEXT_SURFACES_2D_FORMAT_Y16                                   0x00000005
+#define  NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_Z8R8G8B8                     0x00000006
+#define  NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_X8R8G8B8                     0x00000007
+#define  NV04_CONTEXT_SURFACES_2D_FORMAT_X1A7R8G8B8_Z1A7R8G8B8                 0x00000008
+#define  NV04_CONTEXT_SURFACES_2D_FORMAT_X1A7R8G8B8_X1A7R8G8B8                 0x00000009
+#define  NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8                              0x0000000a
+#define  NV04_CONTEXT_SURFACES_2D_FORMAT_Y32                                   0x0000000b
+#define  NV04_CONTEXT_SURFACES_2D_PITCH                                                0x00000304
+#define   NV04_CONTEXT_SURFACES_2D_PITCH_SOURCE_SHIFT                          0
+#define   NV04_CONTEXT_SURFACES_2D_PITCH_SOURCE_MASK                           0x0000ffff
+#define   NV04_CONTEXT_SURFACES_2D_PITCH_DESTIN_SHIFT                          16
+#define   NV04_CONTEXT_SURFACES_2D_PITCH_DESTIN_MASK                           0xffff0000
+#define  NV04_CONTEXT_SURFACES_2D_OFFSET_SOURCE                                        0x00000308
+#define  NV04_CONTEXT_SURFACES_2D_OFFSET_DESTIN                                        0x0000030c
+
+
+#define NV03_CONTEXT_ROP                                                       0x00000043
+
+#define  NV03_CONTEXT_ROP_NOP                                                  0x00000100
+#define  NV03_CONTEXT_ROP_NOTIFY                                               0x00000104
+#define  NV03_CONTEXT_ROP_DMA_NOTIFY                                           0x00000180
+#define  NV03_CONTEXT_ROP_ROP                                                  0x00000300
+#define   NV03_CONTEXT_ROP_ROP_VALUE0_SHIFT                                    0
+#define   NV03_CONTEXT_ROP_ROP_VALUE0_MASK                                     0x0000000f
+#define   NV03_CONTEXT_ROP_ROP_VALUE0_CLEAR                                    0x00000000
+#define   NV03_CONTEXT_ROP_ROP_VALUE0_NOR                                      0x00000001
+#define   NV03_CONTEXT_ROP_ROP_VALUE0_AND_INVERTED                             0x00000002
+#define   NV03_CONTEXT_ROP_ROP_VALUE0_COPY_INVERTED                            0x00000003
+#define   NV03_CONTEXT_ROP_ROP_VALUE0_AND_REVERSE                              0x00000004
+#define   NV03_CONTEXT_ROP_ROP_VALUE0_INVERT                                   0x00000005
+#define   NV03_CONTEXT_ROP_ROP_VALUE0_XOR                                      0x00000006
+#define   NV03_CONTEXT_ROP_ROP_VALUE0_NAND                                     0x00000007
+#define   NV03_CONTEXT_ROP_ROP_VALUE0_AND                                      0x00000008
+#define   NV03_CONTEXT_ROP_ROP_VALUE0_EQUI                                     0x00000009
+#define   NV03_CONTEXT_ROP_ROP_VALUE0_NOOP                                     0x0000000a
+#define   NV03_CONTEXT_ROP_ROP_VALUE0_OR_INVERTED                              0x0000000b
+#define   NV03_CONTEXT_ROP_ROP_VALUE0_COPY                                     0x0000000c
+#define   NV03_CONTEXT_ROP_ROP_VALUE0_OR_REVERSE                               0x0000000d
+#define   NV03_CONTEXT_ROP_ROP_VALUE0_OR                                       0x0000000e
+#define   NV03_CONTEXT_ROP_ROP_VALUE0_SET                                      0x0000000f
+#define   NV03_CONTEXT_ROP_ROP_VALUE1_SHIFT                                    4
+#define   NV03_CONTEXT_ROP_ROP_VALUE1_MASK                                     0x000000f0
+#define   NV03_CONTEXT_ROP_ROP_VALUE1_CLEAR                                    0x00000000
+#define   NV03_CONTEXT_ROP_ROP_VALUE1_NOR                                      0x00000001
+#define   NV03_CONTEXT_ROP_ROP_VALUE1_AND_INVERTED                             0x00000002
+#define   NV03_CONTEXT_ROP_ROP_VALUE1_COPY_INVERTED                            0x00000003
+#define   NV03_CONTEXT_ROP_ROP_VALUE1_AND_REVERSE                              0x00000004
+#define   NV03_CONTEXT_ROP_ROP_VALUE1_INVERT                                   0x00000005
+#define   NV03_CONTEXT_ROP_ROP_VALUE1_XOR                                      0x00000006
+#define   NV03_CONTEXT_ROP_ROP_VALUE1_NAND                                     0x00000007
+#define   NV03_CONTEXT_ROP_ROP_VALUE1_AND                                      0x00000008
+#define   NV03_CONTEXT_ROP_ROP_VALUE1_EQUI                                     0x00000009
+#define   NV03_CONTEXT_ROP_ROP_VALUE1_NOOP                                     0x0000000a
+#define   NV03_CONTEXT_ROP_ROP_VALUE1_OR_INVERTED                              0x0000000b
+#define   NV03_CONTEXT_ROP_ROP_VALUE1_COPY                                     0x0000000c
+#define   NV03_CONTEXT_ROP_ROP_VALUE1_OR_REVERSE                               0x0000000d
+#define   NV03_CONTEXT_ROP_ROP_VALUE1_OR                                       0x0000000e
+#define   NV03_CONTEXT_ROP_ROP_VALUE1_SET                                      0x0000000f
+
+
+#define NV04_IMAGE_PATTERN                                                     0x00000044
+
+#define  NV04_IMAGE_PATTERN_NOP                                                        0x00000100
+#define  NV04_IMAGE_PATTERN_NOTIFY                                             0x00000104
+#define  NV04_IMAGE_PATTERN_DMA_NOTIFY                                         0x00000180
+#define  NV04_IMAGE_PATTERN_COLOR_FORMAT                                       0x00000300
+#define  NV04_IMAGE_PATTERN_COLOR_FORMAT_A16R5G6B5                             0x00000001
+#define  NV04_IMAGE_PATTERN_COLOR_FORMAT_X16A1R5G5B5                           0x00000002
+#define  NV04_IMAGE_PATTERN_COLOR_FORMAT_A8R8G8B8                              0x00000003
+#define  NV04_IMAGE_PATTERN_MONOCHROME_FORMAT                                  0x00000304
+#define  NV04_IMAGE_PATTERN_MONOCHROME_FORMAT_CGA6                             0x00000001
+#define  NV04_IMAGE_PATTERN_MONOCHROME_FORMAT_LE                               0x00000002
+#define  NV04_IMAGE_PATTERN_MONOCHROME_SHAPE                                   0x00000308
+#define  NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_8X8                               0x00000000
+#define  NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_64X1                              0x00000001
+#define  NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_1X64                              0x00000002
+#define  NV04_IMAGE_PATTERN_PATTERN_SELECT                                     0x0000030c
+#define  NV04_IMAGE_PATTERN_PATTERN_SELECT_MONO                                        0x00000001
+#define  NV04_IMAGE_PATTERN_PATTERN_SELECT_COLOR                               0x00000002
+#define  NV04_IMAGE_PATTERN_MONOCHROME_COLOR0                                  0x00000310
+#define  NV04_IMAGE_PATTERN_MONOCHROME_COLOR1                                  0x00000314
+#define  NV04_IMAGE_PATTERN_MONOCHROME_PATTERN0                                        0x00000318
+#define  NV04_IMAGE_PATTERN_MONOCHROME_PATTERN1                                        0x0000031c
+#define  NV04_IMAGE_PATTERN_PATTERN_Y8(x)                                      (0x00000400+((x)*4))
+#define  NV04_IMAGE_PATTERN_PATTERN_Y8__SIZE                                   0x00000010
+#define   NV04_IMAGE_PATTERN_PATTERN_Y8_Y0_SHIFT                               0
+#define   NV04_IMAGE_PATTERN_PATTERN_Y8_Y0_MASK                                        0x000000ff
+#define   NV04_IMAGE_PATTERN_PATTERN_Y8_Y1_SHIFT                               8
+#define   NV04_IMAGE_PATTERN_PATTERN_Y8_Y1_MASK                                        0x0000ff00
+#define   NV04_IMAGE_PATTERN_PATTERN_Y8_Y2_SHIFT                               16
+#define   NV04_IMAGE_PATTERN_PATTERN_Y8_Y2_MASK                                        0x00ff0000
+#define   NV04_IMAGE_PATTERN_PATTERN_Y8_Y3_SHIFT                               24
+#define   NV04_IMAGE_PATTERN_PATTERN_Y8_Y3_MASK                                        0xff000000
+#define  NV04_IMAGE_PATTERN_PATTERN_R5G6B5(x)                                  (0x00000500+((x)*4))
+#define  NV04_IMAGE_PATTERN_PATTERN_R5G6B5__SIZE                               0x00000020
+#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B0_SHIFT                           0
+#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B0_MASK                            0x0000001f
+#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G0_SHIFT                           5
+#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G0_MASK                            0x000007e0
+#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R0_SHIFT                           11
+#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R0_MASK                            0x0000f800
+#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B1_SHIFT                           16
+#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B1_MASK                            0x001f0000
+#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G1_SHIFT                           21
+#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G1_MASK                            0x07e00000
+#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R1_SHIFT                           27
+#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R1_MASK                            0xf8000000
+#define  NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5(x)                                        (0x00000600+((x)*4))
+#define  NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5__SIZE                             0x00000020
+#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B0_SHIFT                         0
+#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B0_MASK                          0x0000001f
+#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G0_SHIFT                         5
+#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G0_MASK                          0x000003e0
+#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R0_SHIFT                         10
+#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R0_MASK                          0x00007c00
+#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B1_SHIFT                         16
+#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B1_MASK                          0x001f0000
+#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G1_SHIFT                         21
+#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G1_MASK                          0x03e00000
+#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R1_SHIFT                         26
+#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R1_MASK                          0x7c000000
+#define  NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8(x)                                        (0x00000700+((x)*4))
+#define  NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8__SIZE                             0x00000040
+#define   NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_B_SHIFT                          0
+#define   NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_B_MASK                           0x000000ff
+#define   NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_G_SHIFT                          8
+#define   NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_G_MASK                           0x0000ff00
+#define   NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_R_SHIFT                          16
+#define   NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_R_MASK                           0x00ff0000
+
+
+#define NV03_VIDEO_LUT_CURSOR_DAC                                              0x00000046
+
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SYNCHRONIZE                                 0x00000100
+#define  NV03_VIDEO_LUT_CURSOR_DAC_STOP_IMAGE                                  0x00000104
+#define  NV03_VIDEO_LUT_CURSOR_DAC_STOP_CURSOR                                 0x00000108
+#define  NV03_VIDEO_LUT_CURSOR_DAC_STOP_DAC                                    0x0000010c
+#define  NV03_VIDEO_LUT_CURSOR_DAC_DMA_NOTIFY                                  0x00000180
+#define  NV03_VIDEO_LUT_CURSOR_DAC_DMA_IMAGE(x)                                        (0x00000184+((x)*4))
+#define  NV03_VIDEO_LUT_CURSOR_DAC_DMA_IMAGE__SIZE                             0x00000002
+#define  NV03_VIDEO_LUT_CURSOR_DAC_DMA_LUT(x)                                  (0x0000018c+((x)*4))
+#define  NV03_VIDEO_LUT_CURSOR_DAC_DMA_LUT__SIZE                               0x00000002
+#define  NV03_VIDEO_LUT_CURSOR_DAC_DMA_CURSOR(x)                               (0x00000194+((x)*4))
+#define  NV03_VIDEO_LUT_CURSOR_DAC_DMA_CURSOR__SIZE                            0x00000002
+#define  NV03_VIDEO_LUT_CURSOR_DAC_GET                                         0x000002fc
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_OFFSET(x)                         (0x00000300+((x)*8))
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_OFFSET__SIZE                      0x00000002
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT(x)                         (0x00000304+((x)*8))
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT__SIZE                      0x00000002
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_PITCH_SHIFT               0
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_PITCH_MASK                        0x0000ffff
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_COLOR_SHIFT               16
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_COLOR_MASK                        0x0fff0000
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_NOTIFY_SHIFT              28
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_NOTIFY_MASK               0xf0000000
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_OFFSET(x)                                (0x00000340+((x)*12))
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_OFFSET__SIZE                     0x00000002
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT(x)                     (0x00000344+((x)*12))
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT__SIZE                  0x00000002
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_X_SHIFT               0
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_X_MASK                        0x0000ffff
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_Y_SHIFT               16
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_Y_MASK                        0xffff0000
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_FORMAT(x)                                (0x00000348+((x)*12))
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_FORMAT__SIZE                     0x00000002
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A                      0x00000358
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A_X_SHIFT             0
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A_X_MASK              0x0000ffff
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A_Y_SHIFT             16
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A_Y_MASK              0xffff0000
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE(x)                       (0x00000380+((x)*16))
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE__SIZE                    0x00000002
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE_W_SHIFT                 0
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE_W_MASK                  0x0000ffff
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE_H_SHIFT                 16
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE_H_MASK                  0xffff0000
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC(x)                            (0x00000384+((x)*16))
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC__SIZE                         0x00000002
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_START_SHIFT                  0
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_START_MASK                   0x0000ffff
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_WIDTH_SHIFT                  16
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_WIDTH_MASK                   0x0fff0000
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_POLARITY_SHIFT               28
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_POLARITY_MASK                        0xf0000000
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC(x)                            (0x00000388+((x)*16))
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC__SIZE                         0x00000002
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_START_SHIFT                  0
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_START_MASK                   0x0000ffff
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_WIDTH_SHIFT                  16
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_WIDTH_MASK                   0x0fff0000
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_POLARITY_SHIFT               28
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_POLARITY_MASK                        0xf0000000
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE(x)                       (0x0000038c+((x)*16))
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE__SIZE                    0x00000002
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_WIDTH_SHIFT             0
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_WIDTH_MASK              0x0000ffff
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_HEIGHT_SHIFT            16
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_HEIGHT_MASK             0x0fff0000
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_NOTIFY_SHIFT            28
+#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_NOTIFY_MASK             0xf0000000
+#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_PIXEL_CLOCK                             0x000003a0
+
+
+#define NV03_DX3_TEXTURED_TRIANGLE                                             0x00000048
+
+#define  NV03_DX3_TEXTURED_TRIANGLE_NOP                                                0x00000100
+#define  NV03_DX3_TEXTURED_TRIANGLE_NOTIFY                                     0x00000104
+#define  NV03_DX3_TEXTURED_TRIANGLE_PATCH                                      0x0000010c
+#define  NV03_DX3_TEXTURED_TRIANGLE_DMA_NOTIFY                                 0x00000180
+#define  NV03_DX3_TEXTURED_TRIANGLE_DMA_TEXTURE                                        0x00000184
+#define  NV03_DX3_TEXTURED_TRIANGLE_CLIP_RECTANGLE                             0x00000188
+#define  NV03_DX3_TEXTURED_TRIANGLE_SURFACE                                    0x0000018c
+#define  NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_OFFSET                             0x00000304
+#define  NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT                             0x00000308
+#define   NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_MASK_SHIFT       0
+#define   NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_MASK_MASK                0x0000ffff
+#define   NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_ENABLE_SHIFT     16
+#define   NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_ENABLE_MASK      0x000f0000
+#define   NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_SHIFT                        20
+#define   NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_MASK                 0x00f00000
+#define   NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MIN_SHIFT             24
+#define   NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MIN_MASK              0x0f000000
+#define   NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MAX_SHIFT             28
+#define   NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MAX_MASK              0xf0000000
+#define  NV03_DX3_TEXTURED_TRIANGLE_FILTER                                     0x0000030c
+#define   NV03_DX3_TEXTURED_TRIANGLE_FILTER_SPREAD_X_SHIFT                     0
+#define   NV03_DX3_TEXTURED_TRIANGLE_FILTER_SPREAD_X_MASK                      0x0000001f
+#define   NV03_DX3_TEXTURED_TRIANGLE_FILTER_SPREAD_Y_SHIFT                     8
+#define   NV03_DX3_TEXTURED_TRIANGLE_FILTER_SPREAD_Y_MASK                      0x00001f00
+#define   NV03_DX3_TEXTURED_TRIANGLE_FILTER_SIZE_ADJUST_SHIFT                  16
+#define   NV03_DX3_TEXTURED_TRIANGLE_FILTER_SIZE_ADJUST_MASK                   0x00ff0000
+#define  NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR                                  0x00000310
+#define   NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR_B_SHIFT                         0
+#define   NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR_B_MASK                          0x000000ff
+#define   NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR_G_SHIFT                         8
+#define   NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR_G_MASK                          0x0000ff00
+#define   NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR_R_SHIFT                         16
+#define   NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR_R_MASK                          0x00ff0000
+#define  NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT                                        0x00000314
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_INTERPOLATOR_SHIFT            0
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_INTERPOLATOR_MASK             0x0000000f
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_U_SHIFT                  4
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_U_MASK                   0x00000030
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_V_SHIFT                  6
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_V_MASK                   0x000000c0
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_SOURCE_COLOR_SHIFT            8
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_SOURCE_COLOR_MASK             0x00000f00
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_CULLING_SHIFT                 12
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_CULLING_MASK                  0x00007000
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_Z_PERSPECTIVE_ENABLE          (1 << 15)
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_Z_FUNC_SHIFT                  16
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_Z_FUNC_MASK                   0x000f0000
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_Z_WRITE_ENABLE_SHIFT          20
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_Z_WRITE_ENABLE_MASK           0x00f00000
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_COLOR_WRITE_ENABLE_SHIFT      24
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_COLOR_WRITE_ENABLE_MASK       0x07000000
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_ROP_SHIFT                     27
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_ROP_MASK                      0x18000000
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_BETA                          (1 << 29)
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_DST_BLEND                     (1 << 30)
+#define   NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_SRC_BLEND                     (1 << 31)
+#define  NV03_DX3_TEXTURED_TRIANGLE_ALPHA_CONTROL                              0x00000318
+#define   NV03_DX3_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_REF_SHIFT             0
+#define   NV03_DX3_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_REF_MASK              0x000000ff
+#define   NV03_DX3_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_FUNC_SHIFT            8
+#define   NV03_DX3_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_FUNC_MASK             0xffffff00
+#define  NV03_DX3_TEXTURED_TRIANGLE_SPECULAR(x)                                        (0x00001000+((x)*32))
+#define  NV03_DX3_TEXTURED_TRIANGLE_SPECULAR__SIZE                             0x00000040
+#define   NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I0_SHIFT                         0
+#define   NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I0_MASK                          0x0000000f
+#define   NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I1_SHIFT                         4
+#define   NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I1_MASK                          0x000000f0
+#define   NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I2_SHIFT                         8
+#define   NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I2_MASK                          0x00000f00
+#define   NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I3_SHIFT                         12
+#define   NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I3_MASK                          0x0000f000
+#define   NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I4_SHIFT                         16
+#define   NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I4_MASK                          0x000f0000
+#define   NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I5_SHIFT                         20
+#define   NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I5_MASK                          0x00f00000
+#define   NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_FOG_SHIFT                                24
+#define   NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_FOG_MASK                         0xff000000
+#define  NV03_DX3_TEXTURED_TRIANGLE_COLOR(x)                                   (0x00001004+((x)*32))
+#define  NV03_DX3_TEXTURED_TRIANGLE_COLOR__SIZE                                        0x00000040
+#define  NV03_DX3_TEXTURED_TRIANGLE_X(x)                                       (0x00001008+((x)*32))
+#define  NV03_DX3_TEXTURED_TRIANGLE_X__SIZE                                    0x00000040
+#define  NV03_DX3_TEXTURED_TRIANGLE_Y(x)                                       (0x0000100c+((x)*32))
+#define  NV03_DX3_TEXTURED_TRIANGLE_Y__SIZE                                    0x00000040
+#define  NV03_DX3_TEXTURED_TRIANGLE_Z(x)                                       (0x00001010+((x)*32))
+#define  NV03_DX3_TEXTURED_TRIANGLE_Z__SIZE                                    0x00000040
+#define  NV03_DX3_TEXTURED_TRIANGLE_M(x)                                       (0x00001014+((x)*32))
+#define  NV03_DX3_TEXTURED_TRIANGLE_M__SIZE                                    0x00000040
+#define  NV03_DX3_TEXTURED_TRIANGLE_U(x)                                       (0x00001018+((x)*32))
+#define  NV03_DX3_TEXTURED_TRIANGLE_U__SIZE                                    0x00000040
+#define  NV03_DX3_TEXTURED_TRIANGLE_V(x)                                       (0x0000101c+((x)*32))
+#define  NV03_DX3_TEXTURED_TRIANGLE_V__SIZE                                    0x00000040
+
+
+#define NV04_GDI_RECTANGLE_TEXT                                                        0x0000004a
+
+#define  NV04_GDI_RECTANGLE_TEXT_NOP                                           0x00000100
+#define  NV04_GDI_RECTANGLE_TEXT_NOTIFY                                                0x00000104
+#define  NV04_GDI_RECTANGLE_TEXT_PATCH                                         0x0000010c
+#define  NV04_GDI_RECTANGLE_TEXT_PM_TRIGGER                                    0x00000140
+#define  NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY                                    0x00000180
+#define  NV04_GDI_RECTANGLE_TEXT_DMA_FONTS                                     0x00000184
+#define  NV04_GDI_RECTANGLE_TEXT_PATTERN                                       0x00000188
+#define  NV04_GDI_RECTANGLE_TEXT_ROP                                           0x0000018c
+#define  NV04_GDI_RECTANGLE_TEXT_BETA1                                         0x00000190
+#define  NV04_GDI_RECTANGLE_TEXT_BETA4                                         0x00000194
+#define  NV04_GDI_RECTANGLE_TEXT_SURFACE                                       0x00000198
+#define  NV04_GDI_RECTANGLE_TEXT_OPERATION                                     0x000002fc
+#define  NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT                                  0x00000300
+#define  NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5                                0x00000001
+#define  NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_X16A1R5G5B5                      0x00000002
+#define  NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8                         0x00000003
+#define  NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT                             0x00000304
+#define  NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_CGA6                                0x00000001
+#define  NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE                          0x00000002
+#define  NV04_GDI_RECTANGLE_TEXT_COLOR1_A                                      0x000003fc
+#define  NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(x)                  (0x00000400+((x)*8))
+#define  NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT__SIZE               0x00000020
+#define   NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y_SHIFT            0
+#define   NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y_MASK             0x0000ffff
+#define   NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X_SHIFT            16
+#define   NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X_MASK             0xffff0000
+#define  NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE(x)                   (0x00000404+((x)*8))
+#define  NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE__SIZE                        0x00000020
+#define   NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H_SHIFT             0
+#define   NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H_MASK              0x0000ffff
+#define   NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W_SHIFT             16
+#define   NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W_MASK              0xffff0000
+#define  NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0                                 0x000005f4
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_L_SHIFT                                0
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_L_MASK                         0x0000ffff
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_T_SHIFT                                16
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_T_MASK                         0xffff0000
+#define  NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1                                 0x000005f8
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_R_SHIFT                                0
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_R_MASK                         0x0000ffff
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_B_SHIFT                                16
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_B_MASK                         0xffff0000
+#define  NV04_GDI_RECTANGLE_TEXT_COLOR1_B                                      0x000005fc
+#define  NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0(x)                  (0x00000600+((x)*8))
+#define  NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0__SIZE               0x00000020
+#define   NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L_SHIFT            0
+#define   NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L_MASK             0x0000ffff
+#define   NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T_SHIFT            16
+#define   NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T_MASK             0xffff0000
+#define  NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1(x)                  (0x00000604+((x)*8))
+#define  NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1__SIZE               0x00000020
+#define   NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R_SHIFT            0
+#define   NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R_MASK             0x0000ffff
+#define   NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B_SHIFT            16
+#define   NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B_MASK             0xffff0000
+#define  NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0                                 0x000007ec
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L_SHIFT                                0
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L_MASK                         0x0000ffff
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T_SHIFT                                16
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T_MASK                         0xffff0000
+#define  NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1                                 0x000007f0
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R_SHIFT                                0
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R_MASK                         0x0000ffff
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B_SHIFT                                16
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B_MASK                         0xffff0000
+#define  NV04_GDI_RECTANGLE_TEXT_COLOR1_C                                      0x000007f4
+#define  NV04_GDI_RECTANGLE_TEXT_SIZE_C                                                0x000007f8
+#define   NV04_GDI_RECTANGLE_TEXT_SIZE_C_W_SHIFT                               0
+#define   NV04_GDI_RECTANGLE_TEXT_SIZE_C_W_MASK                                        0x0000ffff
+#define   NV04_GDI_RECTANGLE_TEXT_SIZE_C_H_SHIFT                               16
+#define   NV04_GDI_RECTANGLE_TEXT_SIZE_C_H_MASK                                        0xffff0000
+#define  NV04_GDI_RECTANGLE_TEXT_POINT_C                                       0x000007fc
+#define   NV04_GDI_RECTANGLE_TEXT_POINT_C_X_SHIFT                              0
+#define   NV04_GDI_RECTANGLE_TEXT_POINT_C_X_MASK                               0x0000ffff
+#define   NV04_GDI_RECTANGLE_TEXT_POINT_C_Y_SHIFT                              16
+#define   NV04_GDI_RECTANGLE_TEXT_POINT_C_Y_MASK                               0xffff0000
+#define  NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C(x)                                (0x00000800+((x)*4))
+#define  NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__SIZE                     0x00000080
+#define  NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0                                 0x00000be4
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L_SHIFT                                0
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L_MASK                         0x0000ffff
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T_SHIFT                                16
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T_MASK                         0xffff0000
+#define  NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1                                 0x00000be8
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R_SHIFT                                0
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R_MASK                         0x0000ffff
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B_SHIFT                                16
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B_MASK                         0xffff0000
+#define  NV04_GDI_RECTANGLE_TEXT_COLOR0_E                                      0x00000bec
+#define  NV04_GDI_RECTANGLE_TEXT_COLOR1_E                                      0x00000bf0
+#define  NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E                                     0x00000bf4
+#define   NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_W_SHIFT                            0
+#define   NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_W_MASK                             0x0000ffff
+#define   NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_H_SHIFT                            16
+#define   NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_H_MASK                             0xffff0000
+#define  NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E                                    0x00000bf8
+#define   NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W_SHIFT                           0
+#define   NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W_MASK                            0x0000ffff
+#define   NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H_SHIFT                           16
+#define   NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H_MASK                            0xffff0000
+#define  NV04_GDI_RECTANGLE_TEXT_POINT_E                                       0x00000bfc
+#define   NV04_GDI_RECTANGLE_TEXT_POINT_E_X_SHIFT                              0
+#define   NV04_GDI_RECTANGLE_TEXT_POINT_E_X_MASK                               0x0000ffff
+#define   NV04_GDI_RECTANGLE_TEXT_POINT_E_Y_SHIFT                              16
+#define   NV04_GDI_RECTANGLE_TEXT_POINT_E_Y_MASK                               0xffff0000
+#define  NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E(x)                       (0x00000c00+((x)*4))
+#define  NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__SIZE                    0x00000080
+#define  NV04_GDI_RECTANGLE_TEXT_FONT_F                                                0x00000ff0
+#define   NV04_GDI_RECTANGLE_TEXT_FONT_F_OFFSET_SHIFT                          0
+#define   NV04_GDI_RECTANGLE_TEXT_FONT_F_OFFSET_MASK                           0x0fffffff
+#define   NV04_GDI_RECTANGLE_TEXT_FONT_F_PITCH_SHIFT                           28
+#define   NV04_GDI_RECTANGLE_TEXT_FONT_F_PITCH_MASK                            0xf0000000
+#define  NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0                                 0x00000ff4
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_L_SHIFT                                0
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_L_MASK                         0x0000ffff
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_T_SHIFT                                16
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_T_MASK                         0xffff0000
+#define  NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1                                 0x00000ff8
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_R_SHIFT                                0
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_R_MASK                         0x0000ffff
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_B_SHIFT                                16
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_B_MASK                         0xffff0000
+#define  NV04_GDI_RECTANGLE_TEXT_COLOR1_F                                      0x00000ffc
+#define  NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F(x)                         (0x00001000+((x)*4))
+#define  NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F__SIZE                      0x00000100
+#define   NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_INDEX_SHIFT               0
+#define   NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_INDEX_MASK                        0x000000ff
+#define   NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_X_SHIFT                   8
+#define   NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_X_MASK                    0x000fff00
+#define   NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_Y_SHIFT                   20
+#define   NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_Y_MASK                    0xfff00000
+#define  NV04_GDI_RECTANGLE_TEXT_FONT_G                                                0x000017f0
+#define   NV04_GDI_RECTANGLE_TEXT_FONT_G_OFFSET_SHIFT                          0
+#define   NV04_GDI_RECTANGLE_TEXT_FONT_G_OFFSET_MASK                           0x0fffffff
+#define   NV04_GDI_RECTANGLE_TEXT_FONT_G_PITCH_SHIFT                           28
+#define   NV04_GDI_RECTANGLE_TEXT_FONT_G_PITCH_MASK                            0xf0000000
+#define  NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0                                 0x000017f4
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_L_SHIFT                                0
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_L_MASK                         0x0000ffff
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_T_SHIFT                                16
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_T_MASK                         0xffff0000
+#define  NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1                                 0x000017f8
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_R_SHIFT                                0
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_R_MASK                         0x0000ffff
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_B_SHIFT                                16
+#define   NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_B_MASK                         0xffff0000
+#define  NV04_GDI_RECTANGLE_TEXT_COLOR1_G                                      0x000017fc
+#define  NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT(x)                   (0x00001800+((x)*8))
+#define  NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT__SIZE                        0x00000100
+#define   NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_X_SHIFT             0
+#define   NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_X_MASK              0x0000ffff
+#define   NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_Y_SHIFT             16
+#define   NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_Y_MASK              0xffff0000
+#define  NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX(x)                   (0x00001804+((x)*8))
+#define  NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX__SIZE                        0x00000100
+
+
+#define NV03_GDI_RECTANGLE_TEXT                                                        0x0000004b
+
+#define  NV03_GDI_RECTANGLE_TEXT_NOP                                           0x00000100
+#define  NV03_GDI_RECTANGLE_TEXT_NOTIFY                                                0x00000104
+#define  NV03_GDI_RECTANGLE_TEXT_DMA_NOTIFY                                    0x00000180
+#define  NV03_GDI_RECTANGLE_TEXT_PATTERN                                       0x00000184
+#define  NV03_GDI_RECTANGLE_TEXT_ROP                                           0x00000188
+#define  NV03_GDI_RECTANGLE_TEXT_BETA1                                         0x0000018c
+#define  NV03_GDI_RECTANGLE_TEXT_SURFACE                                       0x00000190
+#define  NV03_GDI_RECTANGLE_TEXT_OPERATION                                     0x000002fc
+#define  NV03_GDI_RECTANGLE_TEXT_COLOR_FORMAT                                  0x00000300
+#define  NV03_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT                             0x00000304
+#define  NV03_GDI_RECTANGLE_TEXT_COLOR1_A                                      0x000003fc
+#define  NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT                     0x00000400
+#define   NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y_SHIFT            0
+#define   NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y_MASK             0x0000ffff
+#define   NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X_SHIFT            16
+#define   NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X_MASK             0xffff0000
+#define  NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE                      0x00000404
+#define   NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H_SHIFT             0
+#define   NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H_MASK              0x0000ffff
+#define   NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W_SHIFT             16
+#define   NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W_MASK              0xffff0000
+#define  NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B                                 0x000007f4
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_L_SHIFT                                0
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_L_MASK                         0x0000ffff
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_T_SHIFT                                16
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_T_MASK                         0xffff0000
+#define  NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B                                 0x000007f8
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_R_SHIFT                                0
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_R_MASK                         0x0000ffff
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_B_SHIFT                                16
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_B_MASK                         0xffff0000
+#define  NV03_GDI_RECTANGLE_TEXT_COLOR1_B                                      0x000007fc
+#define  NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0                     0x00000800
+#define   NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L_SHIFT            0
+#define   NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L_MASK             0x0000ffff
+#define   NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T_SHIFT            16
+#define   NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T_MASK             0xffff0000
+#define  NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1                     0x00000804
+#define   NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R_SHIFT            0
+#define   NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R_MASK             0x0000ffff
+#define   NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B_SHIFT            16
+#define   NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B_MASK             0xffff0000
+#define  NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0                                 0x00000bec
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L_SHIFT                                0
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L_MASK                         0x0000ffff
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T_SHIFT                                16
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T_MASK                         0xffff0000
+#define  NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1                                 0x00000bf0
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R_SHIFT                                0
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R_MASK                         0x0000ffff
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B_SHIFT                                16
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B_MASK                         0xffff0000
+#define  NV03_GDI_RECTANGLE_TEXT_COLOR1_C                                      0x00000bf4
+#define  NV03_GDI_RECTANGLE_TEXT_SIZE_C                                                0x00000bf8
+#define   NV03_GDI_RECTANGLE_TEXT_SIZE_C_W_SHIFT                               0
+#define   NV03_GDI_RECTANGLE_TEXT_SIZE_C_W_MASK                                        0x0000ffff
+#define   NV03_GDI_RECTANGLE_TEXT_SIZE_C_H_SHIFT                               16
+#define   NV03_GDI_RECTANGLE_TEXT_SIZE_C_H_MASK                                        0xffff0000
+#define  NV03_GDI_RECTANGLE_TEXT_POINT_C                                       0x00000bfc
+#define   NV03_GDI_RECTANGLE_TEXT_POINT_C_X_SHIFT                              0
+#define   NV03_GDI_RECTANGLE_TEXT_POINT_C_X_MASK                               0x0000ffff
+#define   NV03_GDI_RECTANGLE_TEXT_POINT_C_Y_SHIFT                              16
+#define   NV03_GDI_RECTANGLE_TEXT_POINT_C_Y_MASK                               0xffff0000
+#define  NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C(x)                                (0x00000c00+((x)*4))
+#define  NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__SIZE                     0x00000020
+#define  NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0                                 0x00000fe8
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_L_SHIFT                                0
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_L_MASK                         0x0000ffff
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_T_SHIFT                                16
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_T_MASK                         0xffff0000
+#define  NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1                                 0x00000fec
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_R_SHIFT                                0
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_R_MASK                         0x0000ffff
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_B_SHIFT                                16
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_B_MASK                         0xffff0000
+#define  NV03_GDI_RECTANGLE_TEXT_COLOR1_D                                      0x00000ff0
+#define  NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D                                     0x00000ff4
+#define   NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_W_SHIFT                            0
+#define   NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_W_MASK                             0x0000ffff
+#define   NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_H_SHIFT                            16
+#define   NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_H_MASK                             0xffff0000
+#define  NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D                                    0x00000ff8
+#define   NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_W_SHIFT                           0
+#define   NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_W_MASK                            0x0000ffff
+#define   NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_H_SHIFT                           16
+#define   NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_H_MASK                            0xffff0000
+#define  NV03_GDI_RECTANGLE_TEXT_POINT_D                                       0x00000ffc
+#define   NV03_GDI_RECTANGLE_TEXT_POINT_D_X_SHIFT                              0
+#define   NV03_GDI_RECTANGLE_TEXT_POINT_D_X_MASK                               0x0000ffff
+#define   NV03_GDI_RECTANGLE_TEXT_POINT_D_Y_SHIFT                              16
+#define   NV03_GDI_RECTANGLE_TEXT_POINT_D_Y_MASK                               0xffff0000
+#define  NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D(x)                                (0x00001000+((x)*4))
+#define  NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D__SIZE                     0x00000020
+#define  NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0                                 0x000013e4
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L_SHIFT                                0
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L_MASK                         0x0000ffff
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T_SHIFT                                16
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T_MASK                         0xffff0000
+#define  NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1                                 0x000013e8
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R_SHIFT                                0
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R_MASK                         0x0000ffff
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B_SHIFT                                16
+#define   NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B_MASK                         0xffff0000
+#define  NV03_GDI_RECTANGLE_TEXT_COLOR0_E                                      0x000013ec
+#define  NV03_GDI_RECTANGLE_TEXT_COLOR1_E                                      0x000013f0
+#define  NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E                                     0x000013f4
+#define   NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_W_SHIFT                            0
+#define   NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_W_MASK                             0x0000ffff
+#define   NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_H_SHIFT                            16
+#define   NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_H_MASK                             0xffff0000
+#define  NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E                                    0x000013f8
+#define   NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W_SHIFT                           0
+#define   NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W_MASK                            0x0000ffff
+#define   NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H_SHIFT                           16
+#define   NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H_MASK                            0xffff0000
+#define  NV03_GDI_RECTANGLE_TEXT_POINT_E                                       0x000013fc
+#define   NV03_GDI_RECTANGLE_TEXT_POINT_E_X_SHIFT                              0
+#define   NV03_GDI_RECTANGLE_TEXT_POINT_E_X_MASK                               0x0000ffff
+#define   NV03_GDI_RECTANGLE_TEXT_POINT_E_Y_SHIFT                              16
+#define   NV03_GDI_RECTANGLE_TEXT_POINT_E_Y_MASK                               0xffff0000
+#define  NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E(x)                       (0x00001400+((x)*4))
+#define  NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__SIZE                    0x00000020
+
+
+#define NV04_SWIZZLED_SURFACE                                                  0x00000052
+
+#define  NV04_SWIZZLED_SURFACE_NOP                                             0x00000100
+#define  NV04_SWIZZLED_SURFACE_NOTIFY                                          0x00000104
+#define  NV04_SWIZZLED_SURFACE_DMA_NOTIFY                                      0x00000180
+#define  NV04_SWIZZLED_SURFACE_DMA_IMAGE                                       0x00000184
+#define  NV04_SWIZZLED_SURFACE_FORMAT                                          0x00000300
+#define   NV04_SWIZZLED_SURFACE_FORMAT_COLOR_SHIFT                             0
+#define   NV04_SWIZZLED_SURFACE_FORMAT_COLOR_MASK                              0x000000ff
+#define   NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y8                                        0x00000001
+#define   NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1R5G5B5_Z1R5G5B5                 0x00000002
+#define   NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1R5G5B5_X1R5G5B5                 0x00000003
+#define   NV04_SWIZZLED_SURFACE_FORMAT_COLOR_R5G6B5                            0x00000004
+#define   NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y16                               0x00000005
+#define   NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X8R8G8B8_Z8R8G8B8                 0x00000006
+#define   NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X8R8G8B8_X8R8G8B8                 0x00000007
+#define   NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1A7R8G8B8_Z1A7R8G8B8             0x00000008
+#define   NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1A7R8G8B8_X1A7R8G8B8             0x00000009
+#define   NV04_SWIZZLED_SURFACE_FORMAT_COLOR_A8R8G8B8                          0x0000000a
+#define   NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y32                               0x0000000b
+#define   NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT                       16
+#define   NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_MASK                                0x00ff0000
+#define   NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT                       24
+#define   NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_MASK                                0xff000000
+#define  NV04_SWIZZLED_SURFACE_OFFSET                                          0x00000304
+
+
+#define NV04_CONTEXT_SURFACES_3D                                               0x00000053
+
+#define  NV04_CONTEXT_SURFACES_3D_NOP                                          0x00000100
+#define  NV04_CONTEXT_SURFACES_3D_NOTIFY                                       0x00000104
+#define  NV04_CONTEXT_SURFACES_3D_DMA_NOTIFY                                   0x00000180
+#define  NV04_CONTEXT_SURFACES_3D_DMA_COLOR                                    0x00000184
+#define  NV04_CONTEXT_SURFACES_3D_DMA_ZETA                                     0x00000188
+#define  NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL                              0x000002f8
+#define   NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_X_SHIFT                     0
+#define   NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_X_MASK                      0x0000ffff
+#define   NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_W_SHIFT                     16
+#define   NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_W_MASK                      0xffff0000
+#define  NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL                                        0x000002fc
+#define   NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_Y_SHIFT                       0
+#define   NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_Y_MASK                                0x0000ffff
+#define   NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_H_SHIFT                       16
+#define   NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_H_MASK                                0xffff0000
+#define  NV04_CONTEXT_SURFACES_3D_FORMAT                                       0x00000300
+#define   NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_SHIFT                          0
+#define   NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_MASK                           0x000000ff
+#define   NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1R5G5B5_Z1R5G5B5              0x00000001
+#define   NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1R5G5B5_X1R5G5B5              0x00000002
+#define   NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_R5G6B5                         0x00000003
+#define   NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X8R8G8B8_Z8R8G8B8              0x00000004
+#define   NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X8R8G8B8_X8R8G8B8              0x00000005
+#define   NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1A7R8G8B8_Z1A7R8G8B8          0x00000006
+#define   NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1A7R8G8B8_X1A7R8G8B8          0x00000007
+#define   NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_A8R8G8B8                       0x00000008
+#define   NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_SHIFT                           8
+#define   NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_MASK                            0x0000ff00
+#define   NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_PITCH                           0x00000001
+#define   NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_SWIZZLE                         0x00000002
+#define   NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_U_SHIFT                    16
+#define   NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_U_MASK                     0x00ff0000
+#define   NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_V_SHIFT                    24
+#define   NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_V_MASK                     0xff000000
+#define  NV04_CONTEXT_SURFACES_3D_CLIP_SIZE                                    0x00000304
+#define   NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_W_SHIFT                           0
+#define   NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_W_MASK                            0x0000ffff
+#define   NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_H_SHIFT                           16
+#define   NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_H_MASK                            0xffff0000
+#define  NV04_CONTEXT_SURFACES_3D_PITCH                                                0x00000308
+#define   NV04_CONTEXT_SURFACES_3D_PITCH_COLOR_SHIFT                           0
+#define   NV04_CONTEXT_SURFACES_3D_PITCH_COLOR_MASK                            0x0000ffff
+#define   NV04_CONTEXT_SURFACES_3D_PITCH_ZETA_SHIFT                            16
+#define   NV04_CONTEXT_SURFACES_3D_PITCH_ZETA_MASK                             0xffff0000
+#define  NV04_CONTEXT_SURFACES_3D_OFFSET_COLOR                                 0x0000030c
+#define  NV04_CONTEXT_SURFACES_3D_OFFSET_ZETA                                  0x00000310
+
+
+#define NV04_DX5_TEXTURED_TRIANGLE                                             0x00000054
+
+#define  NV04_DX5_TEXTURED_TRIANGLE_NOP                                                0x00000100
+#define  NV04_DX5_TEXTURED_TRIANGLE_NOTIFY                                     0x00000104
+#define  NV04_DX5_TEXTURED_TRIANGLE_DMA_NOTIFY                                 0x00000180
+#define  NV04_DX5_TEXTURED_TRIANGLE_DMA_A                                      0x00000184
+#define  NV04_DX5_TEXTURED_TRIANGLE_DMA_B                                      0x00000188
+#define  NV04_DX5_TEXTURED_TRIANGLE_SURFACE                                    0x0000018c
+#define  NV04_DX5_TEXTURED_TRIANGLE_COLORKEY                                   0x00000300
+#define  NV04_DX5_TEXTURED_TRIANGLE_OFFSET                                     0x00000304
+#define  NV04_DX5_TEXTURED_TRIANGLE_FORMAT                                     0x00000308
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_DMA_SHIFT                          0
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_DMA_MASK                           0x00000003
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_KEY_MATCH_SHIFT              2
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_KEY_MATCH_MASK               0x0000000c
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_SHIFT                   4
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_MASK                    0x00000030
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_CENTER                  0x00000001
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_CORNER                  0x00000002
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_SHIFT                   6
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_MASK                    0x000000c0
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_CENTER                  0x00000001
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_CORNER                  0x00000002
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_SHIFT                                8
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_MASK                         0x00000f00
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_Y8                           0x00000001
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_A1R5G5B5                     0x00000002
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_X1R5G5B5                     0x00000003
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_A4R4G4B4                     0x00000004
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_R5G6B5                       0x00000005
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_A8R8G8B8                     0x00000006
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_X8R8G8B8                     0x00000007
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_MIPMAP_LEVELS_SHIFT                        12
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_MIPMAP_LEVELS_MASK                 0x0000f000
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_U_SHIFT                  16
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_U_MASK                   0x000f0000
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_V_SHIFT                  20
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_V_MASK                   0x00f00000
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_SHIFT                     24
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_MASK                      0x07000000
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_REPEAT                    0x00000001
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_MIRRORED_REPEAT           0x00000002
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_EDGE             0x00000003
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_BORDER           0x00000004
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP                     0x00000005
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_WRAPU                              (1 << 27)
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_SHIFT                     28
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_MASK                      0x70000000
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_REPEAT                    0x00000001
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_MIRRORED_REPEAT           0x00000002
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_EDGE             0x00000003
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_BORDER           0x00000004
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP                     0x00000005
+#define   NV04_DX5_TEXTURED_TRIANGLE_FORMAT_WRAPV                              (1 << 31)
+#define  NV04_DX5_TEXTURED_TRIANGLE_FILTER                                     0x0000030c
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_X_SHIFT                        0
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_X_MASK                 0x000000ff
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_Y_SHIFT                        8
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_Y_MASK                 0x00007f00
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_MIPMAP_DITHER_ENABLE               (1 << 15)
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_MIPMAP_LODBIAS_SHIFT               16
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_MIPMAP_LODBIAS_MASK                        0x00ff0000
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_SHIFT                       24
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_MASK                                0x07000000
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST                     0x00000001
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR                      0x00000002
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST      0x00000003
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST       0x00000004
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR       0x00000005
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR                0x00000006
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MINIFY_ENABLE          (1 << 27)
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_MAGNIFY_SHIFT                      28
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_MAGNIFY_MASK                       0x70000000
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_MAGNIFY_NEAREST                    0x00000001
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_MAGNIFY_LINEAR                     0x00000002
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_MAGNIFY_NEAREST_MIPMAP_NEAREST     0x00000003
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_MAGNIFY_LINEAR_MIPMAP_NEAREST      0x00000004
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_MAGNIFY_NEAREST_MIPMAP_LINEAR      0x00000005
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_MAGNIFY_LINEAR_MIPMAP_LINEAR       0x00000006
+#define   NV04_DX5_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MAGNIFY_ENABLE         (1 << 31)
+#define  NV04_DX5_TEXTURED_TRIANGLE_BLEND                                      0x00000310
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_SHIFT                   0
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_MASK                    0x0000000f
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_MASK_BIT_SHIFT                      4
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_MASK_BIT_MASK                       0x00000030
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_SHIFT                    6
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_MASK                     0x000000c0
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_FLAT                     0x00000001
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_GOURAUD                  0x00000002
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_PHONG                    0x00000003
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE_SHIFT    8
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE_MASK     0x00000f00
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_SPECULAR_ENABLE_SHIFT               12
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_SPECULAR_ENABLE_MASK                        0x0000f000
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_FOG_ENABLE_SHIFT                    16
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_FOG_ENABLE_MASK                     0x000f0000
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_ALPHA_ENABLE_SHIFT                  20
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_ALPHA_ENABLE_MASK                   0x00f00000
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_SHIFT                           24
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_MASK                            0x0f000000
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_SHIFT                           28
+#define   NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_MASK                            0xf0000000
+#define  NV04_DX5_TEXTURED_TRIANGLE_CONTROL                                    0x00000314
+#define   NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHA_REF_SHIFT                   0
+#define   NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHA_REF_MASK                    0x000000ff
+#define   NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_SHIFT                  8
+#define   NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_MASK                   0x00000f00
+#define   NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHA_TEST_ENABLE                 (1 << 12)
+#define   NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ORIGIN                            (1 << 13)
+#define   NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_ENABLE_SHIFT                    14
+#define   NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_ENABLE_MASK                     0x0000c000
+#define   NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_SHIFT                      16
+#define   NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_MASK                       0x000f0000
+#define   NV04_DX5_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_SHIFT                   20
+#define   NV04_DX5_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_MASK                    0x00300000
+#define   NV04_DX5_TEXTURED_TRIANGLE_CONTROL_DITHER_ENABLE                     (1 << 22)
+#define   NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_PERSPECTIVE_ENABLE              (1 << 23)
+#define   NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_WRITE_ENABLE_SHIFT              24
+#define   NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_WRITE_ENABLE_MASK               0x3f000000
+#define   NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT_SHIFT                    30
+#define   NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT_MASK                     0xc0000000
+#define  NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR                                   0x00000318
+#define   NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_B_SHIFT                          0
+#define   NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_B_MASK                           0x000000ff
+#define   NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_G_SHIFT                          8
+#define   NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_G_MASK                           0x0000ff00
+#define   NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_R_SHIFT                          16
+#define   NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_R_MASK                           0x00ff0000
+#define   NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_A_SHIFT                          24
+#define   NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_A_MASK                           0xff000000
+#define  NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(x)                             (0x00000400+((x)*32))
+#define  NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX__SIZE                          0x00000010
+#define  NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SY(x)                             (0x00000404+((x)*32))
+#define  NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SY__SIZE                          0x00000010
+#define  NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SZ(x)                             (0x00000408+((x)*32))
+#define  NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SZ__SIZE                          0x00000010
+#define  NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_RHW(x)                            (0x0000040c+((x)*32))
+#define  NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_RHW__SIZE                         0x00000010
+#define  NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR(x)                          (0x00000410+((x)*32))
+#define  NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR__SIZE                       0x00000010
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_B_SHIFT                    0
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_B_MASK                     0x000000ff
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_G_SHIFT                    8
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_G_MASK                     0x0000ff00
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_R_SHIFT                    16
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_R_MASK                     0x00ff0000
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_A_SHIFT                    24
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_A_MASK                     0xff000000
+#define  NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR(x)                       (0x00000414+((x)*32))
+#define  NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR__SIZE                    0x00000010
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_B_SHIFT                 0
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_B_MASK                  0x000000ff
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_G_SHIFT                 8
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_G_MASK                  0x0000ff00
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_R_SHIFT                 16
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_R_MASK                  0x00ff0000
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_SHIFT               24
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_MASK                        0xff000000
+#define  NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_TU(x)                             (0x00000418+((x)*32))
+#define  NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_TU__SIZE                          0x00000010
+#define  NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_TV(x)                             (0x0000041c+((x)*32))
+#define  NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_TV__SIZE                          0x00000010
+#define  NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE(x)                  (0x00000600+((x)*4))
+#define  NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE__SIZE               0x00000040
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I0_SHIFT           0
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I0_MASK            0x0000000f
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I1_SHIFT           4
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I1_MASK            0x000000f0
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I2_SHIFT           8
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I2_MASK            0x00000f00
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I3_SHIFT           12
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I3_MASK            0x0000f000
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I4_SHIFT           16
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I4_MASK            0x000f0000
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I5_SHIFT           20
+#define   NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I5_MASK            0x00f00000
+
+
+#define NV04_DX6_MULTITEX_TRIANGLE                                             0x00000055
+
+#define  NV04_DX6_MULTITEX_TRIANGLE_NOP                                                0x00000100
+#define  NV04_DX6_MULTITEX_TRIANGLE_NOTIFY                                     0x00000104
+#define  NV04_DX6_MULTITEX_TRIANGLE_DMA_NOTIFY                                 0x00000180
+#define  NV04_DX6_MULTITEX_TRIANGLE_DMA_A                                      0x00000184
+#define  NV04_DX6_MULTITEX_TRIANGLE_DMA_B                                      0x00000188
+#define  NV04_DX6_MULTITEX_TRIANGLE_SURFACE                                    0x0000018c
+#define  NV04_DX6_MULTITEX_TRIANGLE_OFFSET(x)                                  (0x00000308+((x)*4))
+#define  NV04_DX6_MULTITEX_TRIANGLE_OFFSET__SIZE                               0x00000002
+#define  NV04_DX6_MULTITEX_TRIANGLE_FORMAT(x)                                  (0x00000310+((x)*4))
+#define  NV04_DX6_MULTITEX_TRIANGLE_FORMAT__SIZE                               0x00000002
+#define   NV04_DX6_MULTITEX_TRIANGLE_FORMAT_DMA_SHIFT                          0
+#define   NV04_DX6_MULTITEX_TRIANGLE_FORMAT_DMA_MASK                           0x0000000f
+#define   NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ORIGIN_ZOH_SHIFT                   4
+#define   NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ORIGIN_ZOH_MASK                    0x00000030
+#define   NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ORIGIN_FOH_SHIFT                   6
+#define   NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ORIGIN_FOH_MASK                    0x000000c0
+#define   NV04_DX6_MULTITEX_TRIANGLE_FORMAT_COLOR_SHIFT                                8
+#define   NV04_DX6_MULTITEX_TRIANGLE_FORMAT_COLOR_MASK                         0x00000f00
+#define   NV04_DX6_MULTITEX_TRIANGLE_FORMAT_MIPMAP_LEVELS_SHIFT                        12
+#define   NV04_DX6_MULTITEX_TRIANGLE_FORMAT_MIPMAP_LEVELS_MASK                 0x0000f000
+#define   NV04_DX6_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_U_SHIFT                  16
+#define   NV04_DX6_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_U_MASK                   0x000f0000
+#define   NV04_DX6_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_V_SHIFT                  20
+#define   NV04_DX6_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_V_MASK                   0x00f00000
+#define   NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ADDRESSU_SHIFT                     24
+#define   NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ADDRESSU_MASK                      0x07000000
+#define   NV04_DX6_MULTITEX_TRIANGLE_FORMAT_WRAPU                              (1 << 27)
+#define   NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ADDRESSV_SHIFT                     28
+#define   NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ADDRESSV_MASK                      0x70000000
+#define   NV04_DX6_MULTITEX_TRIANGLE_FORMAT_WRAPV                              (1 << 31)
+#define  NV04_DX6_MULTITEX_TRIANGLE_FILTER(x)                                  (0x00000318+((x)*4))
+#define  NV04_DX6_MULTITEX_TRIANGLE_FILTER__SIZE                               0x00000002
+#define   NV04_DX6_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_X_SHIFT                        0
+#define   NV04_DX6_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_X_MASK                 0x000000ff
+#define   NV04_DX6_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_Y_SHIFT                        8
+#define   NV04_DX6_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_Y_MASK                 0x00007f00
+#define   NV04_DX6_MULTITEX_TRIANGLE_FILTER_MIPMAP_DITHER_ENABLE               (1 << 15)
+#define   NV04_DX6_MULTITEX_TRIANGLE_FILTER_MIPMAP_LODBIAS_SHIFT               16
+#define   NV04_DX6_MULTITEX_TRIANGLE_FILTER_MIPMAP_LODBIAS_MASK                        0x00ff0000
+#define   NV04_DX6_MULTITEX_TRIANGLE_FILTER_MINIFY_SHIFT                       24
+#define   NV04_DX6_MULTITEX_TRIANGLE_FILTER_MINIFY_MASK                                0x07000000
+#define   NV04_DX6_MULTITEX_TRIANGLE_FILTER_ANISOTROPIC_MINIFY_ENABLE          (1 << 27)
+#define   NV04_DX6_MULTITEX_TRIANGLE_FILTER_MAGNIFY_SHIFT                      28
+#define   NV04_DX6_MULTITEX_TRIANGLE_FILTER_MAGNIFY_MASK                       0x70000000
+#define   NV04_DX6_MULTITEX_TRIANGLE_FILTER_ANISOTROPIC_MAGNIFY_ENABLE         (1 << 31)
+#define  NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA                            0x00000320
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_INVERSE0                  (1 <<  0)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ALPHA0                    (1 <<  1)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT0_SHIFT           2
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT0_MASK            0x000000fc
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_INVERSE1                  (1 <<  8)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ALPHA1                    (1 <<  9)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT1_SHIFT           10
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT1_MASK            0x0000fc00
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_INVERSE2                  (1 << 16)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ALPHA2                    (1 << 17)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT2_SHIFT           18
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT2_MASK            0x00fc0000
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_INVERSE3                  (1 << 24)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ALPHA3                    (1 << 25)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT3_SHIFT           26
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT3_MASK            0x1c000000
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_OPERATION_SHIFT           29
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_OPERATION_MASK            0xe0000000
+#define  NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR                            0x00000324
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_INVERSE0                  (1 <<  0)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ALPHA0                    (1 <<  1)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT0_SHIFT           2
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT0_MASK            0x000000fc
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_INVERSE1                  (1 <<  8)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ALPHA1                    (1 <<  9)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT1_SHIFT           10
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT1_MASK            0x0000fc00
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_INVERSE2                  (1 << 16)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ALPHA2                    (1 << 17)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT2_SHIFT           18
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT2_MASK            0x00fc0000
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_INVERSE3                  (1 << 24)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ALPHA3                    (1 << 25)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT3_SHIFT           26
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT3_MASK            0x1c000000
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_OPERATION_SHIFT           29
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_OPERATION_MASK            0xe0000000
+#define  NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA                            0x0000032c
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_INVERSE0                  (1 <<  0)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ALPHA0                    (1 <<  1)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT0_SHIFT           2
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT0_MASK            0x000000fc
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_INVERSE1                  (1 <<  8)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ALPHA1                    (1 <<  9)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT1_SHIFT           10
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT1_MASK            0x0000fc00
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_INVERSE2                  (1 << 16)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ALPHA2                    (1 << 17)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT2_SHIFT           18
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT2_MASK            0x00fc0000
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_INVERSE3                  (1 << 24)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ALPHA3                    (1 << 25)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT3_SHIFT           26
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT3_MASK            0x1c000000
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_OPERATION_SHIFT           29
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_OPERATION_MASK            0xe0000000
+#define  NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR                            0x00000330
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_INVERSE0                  (1 <<  0)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ALPHA0                    (1 <<  1)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT0_SHIFT           2
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT0_MASK            0x000000fc
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_INVERSE1                  (1 <<  8)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ALPHA1                    (1 <<  9)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT1_SHIFT           10
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT1_MASK            0x0000fc00
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_INVERSE2                  (1 << 16)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ALPHA2                    (1 << 17)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT2_SHIFT           18
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT2_MASK            0x00fc0000
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_INVERSE3                  (1 << 24)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ALPHA3                    (1 << 25)
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT3_SHIFT           26
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT3_MASK            0x1c000000
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_OPERATION_SHIFT           29
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_OPERATION_MASK            0xe0000000
+#define  NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR                             0x00000334
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_B_SHIFT                    0
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_B_MASK                     0x000000ff
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_G_SHIFT                    8
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_G_MASK                     0x0000ff00
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_R_SHIFT                    16
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_R_MASK                     0x00ff0000
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_A_SHIFT                    24
+#define   NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_A_MASK                     0xff000000
+#define  NV04_DX6_MULTITEX_TRIANGLE_BLEND                                      0x00000338
+#define   NV04_DX6_MULTITEX_TRIANGLE_BLEND_MASK_BIT_SHIFT                      4
+#define   NV04_DX6_MULTITEX_TRIANGLE_BLEND_MASK_BIT_MASK                       0x00000030
+#define   NV04_DX6_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_SHIFT                    6
+#define   NV04_DX6_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_MASK                     0x000000c0
+#define   NV04_DX6_MULTITEX_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE_SHIFT    8
+#define   NV04_DX6_MULTITEX_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE_MASK     0x00000f00
+#define   NV04_DX6_MULTITEX_TRIANGLE_BLEND_SPECULAR_ENABLE_SHIFT               12
+#define   NV04_DX6_MULTITEX_TRIANGLE_BLEND_SPECULAR_ENABLE_MASK                        0x0000f000
+#define   NV04_DX6_MULTITEX_TRIANGLE_BLEND_FOG_ENABLE_SHIFT                    16
+#define   NV04_DX6_MULTITEX_TRIANGLE_BLEND_FOG_ENABLE_MASK                     0x000f0000
+#define   NV04_DX6_MULTITEX_TRIANGLE_BLEND_ALPHA_ENABLE_SHIFT                  20
+#define   NV04_DX6_MULTITEX_TRIANGLE_BLEND_ALPHA_ENABLE_MASK                   0x00f00000
+#define   NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_SHIFT                           24
+#define   NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_MASK                            0x0f000000
+#define   NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_SHIFT                           28
+#define   NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_MASK                            0xf0000000
+#define  NV04_DX6_MULTITEX_TRIANGLE_CONTROL0                                   0x0000033c
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_REF_SHIFT                  0
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_REF_MASK                   0x000000ff
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_SHIFT                 8
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_MASK                  0x00000f00
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_TEST_ENABLE                        (1 << 12)
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ORIGIN                           (1 << 13)
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_ENABLE_SHIFT                   14
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_ENABLE_MASK                    0x0000c000
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_SHIFT                     16
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_MASK                      0x000f0000
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_SHIFT                  20
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_MASK                   0x00300000
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_DITHER_ENABLE                    (1 << 22)
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_PERSPECTIVE_ENABLE             (1 << 23)
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_WRITE_ENABLE                   (1 << 24)
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_STENCIL_WRITE_ENABLE             (1 << 25)
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE_ENABLE               (1 << 26)
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_RED_WRITE_ENABLE                 (1 << 27)
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_GREEN_WRITE_ENABLE               (1 << 28)
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_BLUE_WRITE_ENABLE                        (1 << 29)
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_FORMAT_SHIFT                   30
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_FORMAT_MASK                    0xc0000000
+#define  NV04_DX6_MULTITEX_TRIANGLE_CONTROL1                                   0x00000340
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_TEST_ENABLE_SHIFT                0
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_TEST_ENABLE_MASK         0x0000000f
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_FUNC_SHIFT               4
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_FUNC_MASK                        0x000000f0
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_REF_SHIFT                        8
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_REF_MASK                 0x0000ff00
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_READ_SHIFT          16
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_READ_MASK           0x00ff0000
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_WRITE_SHIFT         24
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_WRITE_MASK          0xff000000
+#define  NV04_DX6_MULTITEX_TRIANGLE_CONTROL2                                   0x00000344
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_FAIL_SHIFT            0
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_FAIL_MASK             0x0000000f
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZFAIL_SHIFT           4
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZFAIL_MASK            0x000000f0
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZPASS_SHIFT           8
+#define   NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZPASS_MASK            0x00000f00
+#define  NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR                                   0x00000348
+#define   NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_B_SHIFT                          0
+#define   NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_B_MASK                           0x000000ff
+#define   NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_G_SHIFT                          8
+#define   NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_G_MASK                           0x0000ff00
+#define   NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_R_SHIFT                          16
+#define   NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_R_MASK                           0x00ff0000
+#define   NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_A_SHIFT                          24
+#define   NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_A_MASK                           0xff000000
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SX(x)                           (0x00000400+((x)*40))
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SX__SIZE                                0x00000008
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SY(x)                           (0x00000404+((x)*40))
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SY__SIZE                                0x00000008
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SZ(x)                           (0x00000408+((x)*40))
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SZ__SIZE                                0x00000008
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_RHW(x)                          (0x0000040c+((x)*40))
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_RHW__SIZE                       0x00000008
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR(x)                                (0x00000410+((x)*40))
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR__SIZE                     0x00000008
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_B_SHIFT                  0
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_B_MASK                   0x000000ff
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_G_SHIFT                  8
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_G_MASK                   0x0000ff00
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_R_SHIFT                  16
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_R_MASK                   0x00ff0000
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_A_SHIFT                  24
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_A_MASK                   0xff000000
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR(x)                     (0x00000414+((x)*40))
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR__SIZE                  0x00000008
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_B_SHIFT               0
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_B_MASK                        0x000000ff
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_G_SHIFT               8
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_G_MASK                        0x0000ff00
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_R_SHIFT               16
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_R_MASK                        0x00ff0000
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_FOG_SHIFT             24
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_FOG_MASK              0xff000000
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TU0(x)                          (0x00000418+((x)*40))
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TU0__SIZE                       0x00000008
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TV0(x)                          (0x0000041c+((x)*40))
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TV0__SIZE                       0x00000008
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TU1(x)                          (0x00000420+((x)*40))
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TU1__SIZE                       0x00000008
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TV1(x)                          (0x00000424+((x)*40))
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TV1__SIZE                       0x00000008
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE(x)                        (0x00000540+((x)*4))
+#define  NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE__SIZE             0x00000030
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I0_SHIFT         0
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I0_MASK          0x0000000f
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I1_SHIFT         4
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I1_MASK          0x000000f0
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I2_SHIFT         8
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I2_MASK          0x00000f00
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I3_SHIFT         12
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I3_MASK          0x0000f000
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I4_SHIFT         16
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I4_MASK          0x000f0000
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I5_SHIFT         20
+#define   NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I5_MASK          0x00f00000
+
+
+#define NV10_TCL_PRIMITIVE_3D                                                  0x00000056
+
+#define  NV10_TCL_PRIMITIVE_3D_NOP                                             0x00000100
+#define  NV10_TCL_PRIMITIVE_3D_NOTIFY                                          0x00000104
+#define  NV10_TCL_PRIMITIVE_3D_DMA_NOTIFY                                      0x00000180
+#define  NV10_TCL_PRIMITIVE_3D_DMA_IN_MEMORY0                                  0x00000184
+#define  NV10_TCL_PRIMITIVE_3D_DMA_IN_MEMORY1                                  0x00000188
+#define  NV10_TCL_PRIMITIVE_3D_DISPLAY_LIST                                    0x0000018c
+#define  NV10_TCL_PRIMITIVE_3D_DMA_IN_MEMORY2                                  0x00000194
+#define  NV10_TCL_PRIMITIVE_3D_DMA_IN_MEMORY3                                  0x00000198
+#define  NV10_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ                                  0x00000200
+#define   NV10_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ_X_SHIFT                         0
+#define   NV10_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ_X_MASK                          0x0000ffff
+#define   NV10_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ_W_SHIFT                         16
+#define   NV10_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ_W_MASK                          0xffff0000
+#define  NV10_TCL_PRIMITIVE_3D_VIEWPORT_VERT                                   0x00000204
+#define   NV10_TCL_PRIMITIVE_3D_VIEWPORT_VERT_Y_SHIFT                          0
+#define   NV10_TCL_PRIMITIVE_3D_VIEWPORT_VERT_Y_MASK                           0x0000ffff
+#define   NV10_TCL_PRIMITIVE_3D_VIEWPORT_VERT_H_SHIFT                          16
+#define   NV10_TCL_PRIMITIVE_3D_VIEWPORT_VERT_H_MASK                           0xffff0000
+#define  NV10_TCL_PRIMITIVE_3D_BUFFER_FORMAT                                   0x00000208
+#define  NV10_TCL_PRIMITIVE_3D_BUFFER_PITCH                                    0x0000020c
+#define   NV10_TCL_PRIMITIVE_3D_BUFFER_PITCH_COLOR_PITCH_SHIFT                 0
+#define   NV10_TCL_PRIMITIVE_3D_BUFFER_PITCH_COLOR_PITCH_MASK                  0x0000ffff
+#define   NV10_TCL_PRIMITIVE_3D_BUFFER_PITCH_ZETA_PITCH_SHIFT                  16
+#define   NV10_TCL_PRIMITIVE_3D_BUFFER_PITCH_ZETA_PITCH_MASK                   0xffff0000
+#define  NV10_TCL_PRIMITIVE_3D_COLOR_OFFSET                                    0x00000210
+#define  NV10_TCL_PRIMITIVE_3D_ZETA_OFFSET                                     0x00000214
+#define  NV10_TCL_PRIMITIVE_3D_TX_OFFSET(x)                                    (0x00000218+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_TX_OFFSET__SIZE                                 0x00000002
+#define  NV10_TCL_PRIMITIVE_3D_TX_FORMAT(x)                                    (0x00000220+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_TX_FORMAT__SIZE                                 0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_CUBE_MAP                             (1 <<  2)
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_SHIFT                         7
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_MASK                          0x00000780
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_L8                            0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_A8                            0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R5G5B5A1                      0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_A8_RECT                       0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R4G4B4A4                      0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R8G8B8A8                      0x00000006
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_INDEX8                                0x0000000b
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_DXT1                          0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_DXT3                          0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_DXT5                          0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R5G5B5A1_RECT                 0x00000010
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R8G8B8A8_RECT                 0x00000012
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_L8_RECT                       0x00000013
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_L8A8                          0x0000001a
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_A8_RECT_2                     0x0000001b
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R4G4B4A4_RECT                 0x0000001d
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_L8A8_RECT                     0x00000020
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_NPOT                                 (1 << 11)
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_MIPMAP_LEVELS_SHIFT                  12
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_MIPMAP_LEVELS_MASK                   0x0000f000
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_BASE_SIZE_U_SHIFT                    16
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_BASE_SIZE_U_MASK                     0x000f0000
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_BASE_SIZE_V_SHIFT                    20
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_BASE_SIZE_V_MASK                     0x00f00000
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_SHIFT                         24
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_MASK                          0x0f000000
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_REPEAT                                0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_MIRRORED_REPEAT               0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_CLAMP_TO_EDGE                 0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_CLAMP_TO_BORDER               0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_CLAMP                         0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_SHIFT                         28
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_MASK                          0xf0000000
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_REPEAT                                0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_MIRRORED_REPEAT               0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_CLAMP_TO_EDGE                 0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_CLAMP_TO_BORDER               0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_CLAMP                         0x00000005
+#define  NV10_TCL_PRIMITIVE_3D_TX_ENABLE(x)                                    (0x00000228+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_TX_ENABLE__SIZE                                 0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_SHIFT                     4
+#define   NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_MASK                      0x00000030
+#define   NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ENABLE                               (1 << 30)
+#define  NV10_TCL_PRIMITIVE_3D_TX_NPOT_PITCH(x)                                        (0x00000230+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_TX_NPOT_PITCH__SIZE                             0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_TX_NPOT_PITCH_PITCH_SHIFT                      16
+#define   NV10_TCL_PRIMITIVE_3D_TX_NPOT_PITCH_PITCH_MASK                       0xffff0000
+#define  NV10_TCL_PRIMITIVE_3D_TX_NPOT_SIZE(x)                                 (0x00000240+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_TX_NPOT_SIZE__SIZE                              0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_TX_NPOT_SIZE_H_SHIFT                           0
+#define   NV10_TCL_PRIMITIVE_3D_TX_NPOT_SIZE_H_MASK                            0x0000ffff
+#define   NV10_TCL_PRIMITIVE_3D_TX_NPOT_SIZE_W_SHIFT                           16
+#define   NV10_TCL_PRIMITIVE_3D_TX_NPOT_SIZE_W_MASK                            0xffff0000
+#define  NV10_TCL_PRIMITIVE_3D_TX_FILTER(x)                                    (0x00000248+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_TX_FILTER__SIZE                                 0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_TX_FILTER_MINIFY_SHIFT                         24
+#define   NV10_TCL_PRIMITIVE_3D_TX_FILTER_MINIFY_MASK                          0x0f000000
+#define   NV10_TCL_PRIMITIVE_3D_TX_FILTER_MINIFY_NEAREST                       0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_TX_FILTER_MINIFY_LINEAR                                0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST                0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST         0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR         0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR          0x00000006
+#define   NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAGNIFY_SHIFT                                28
+#define   NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAGNIFY_MASK                         0xf0000000
+#define   NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAGNIFY_NEAREST                      0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAGNIFY_LINEAR                       0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAGNIFY_NEAREST_MIPMAP_NEAREST       0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAGNIFY_LINEAR_MIPMAP_NEAREST                0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAGNIFY_NEAREST_MIPMAP_LINEAR                0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAGNIFY_LINEAR_MIPMAP_LINEAR         0x00000006
+#define  NV10_TCL_PRIMITIVE_3D_TX_PALETTE_OFFSET(x)                            (0x00000250+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_TX_PALETTE_OFFSET__SIZE                         0x00000002
+#define  NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA(x)                                  (0x00000260+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA__SIZE                               0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_INPUT_SHIFT                      0
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_INPUT_MASK                       0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_INPUT_ZERO                       0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0_NV         0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1_NV         0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_INPUT_FOG                                0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR_NV           0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR_NV         0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_INPUT_TEXTURE1_ARB               0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_INPUT_TEXTURE0_ARB               0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_INPUT_SPARE0_NV                  0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_INPUT_SPARE1_NV                  0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_INPUT_E_TIMES_F_NV               0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_COMPONENT_USAGE                  (1 <<  4)
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_COMPONENT_USAGE_BLUE             0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_COMPONENT_USAGE_ALPHA            0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_MAPPING_SHIFT                    5
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_MAPPING_MASK                     0x000000e0
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY_NV     0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT_NV       0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL_NV         0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE_NV         0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL_NV      0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE_NV      0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY_NV       0x00000006
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE_NV         0x00000007
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_INPUT_SHIFT                      8
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_INPUT_MASK                       0x00000f00
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_INPUT_ZERO                       0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0_NV         0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1_NV         0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_INPUT_FOG                                0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR_NV           0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR_NV         0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_INPUT_TEXTURE1_ARB               0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_INPUT_TEXTURE0_ARB               0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_INPUT_SPARE0_NV                  0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_INPUT_SPARE1_NV                  0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_INPUT_E_TIMES_F_NV               0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_COMPONENT_USAGE                  (1 << 12)
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_COMPONENT_USAGE_BLUE             0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_COMPONENT_USAGE_ALPHA            0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_MAPPING_SHIFT                    13
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_MAPPING_MASK                     0x0000e000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY_NV     0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT_NV       0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL_NV         0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE_NV         0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL_NV      0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE_NV      0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY_NV       0x00000006
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE_NV         0x00000007
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_INPUT_SHIFT                      16
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_INPUT_MASK                       0x000f0000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_INPUT_ZERO                       0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0_NV         0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1_NV         0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_INPUT_FOG                                0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR_NV           0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR_NV         0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_INPUT_TEXTURE1_ARB               0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_INPUT_TEXTURE0_ARB               0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_INPUT_SPARE0_NV                  0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_INPUT_SPARE1_NV                  0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_INPUT_E_TIMES_F_NV               0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_COMPONENT_USAGE                  (1 << 20)
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_COMPONENT_USAGE_BLUE             0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_COMPONENT_USAGE_ALPHA            0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_MAPPING_SHIFT                    21
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_MAPPING_MASK                     0x00e00000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY_NV     0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT_NV       0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL_NV         0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE_NV         0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL_NV      0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE_NV      0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY_NV       0x00000006
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE_NV         0x00000007
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_INPUT_SHIFT                      24
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_INPUT_MASK                       0x0f000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_INPUT_ZERO                       0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0_NV         0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1_NV         0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_INPUT_FOG                                0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR_NV           0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR_NV         0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_INPUT_TEXTURE1_ARB               0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_INPUT_TEXTURE0_ARB               0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_INPUT_SPARE0_NV                  0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_INPUT_SPARE1_NV                  0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_INPUT_E_TIMES_F_NV               0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_COMPONENT_USAGE                  (1 << 28)
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_COMPONENT_USAGE_BLUE             0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_COMPONENT_USAGE_ALPHA            0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_MAPPING_SHIFT                    29
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_MAPPING_MASK                     0xe0000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY_NV     0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT_NV       0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL_NV         0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE_NV         0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL_NV      0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE_NV      0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY_NV       0x00000006
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE_NV         0x00000007
+#define  NV10_TCL_PRIMITIVE_3D_RC_IN_RGB(x)                                    (0x00000268+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_RC_IN_RGB__SIZE                                 0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_INPUT_SHIFT                                0
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_INPUT_MASK                         0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_INPUT_ZERO                         0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0_NV           0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_INPUT_FOG                          0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_INPUT_PRIMARY_COLOR_NV             0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_INPUT_SECONDARY_COLOR_NV           0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_INPUT_TEXTURE1_ARB                 0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_INPUT_TEXTURE0_ARB                 0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_INPUT_SPARE0_NV                    0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_INPUT_SPARE1_NV                    0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_INPUT_E_TIMES_F_NV                 0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_COMPONENT_USAGE                    (1 <<  4)
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_COMPONENT_USAGE_RGB                        0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_COMPONENT_USAGE_ALPHA              0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_MAPPING_SHIFT                      5
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_MAPPING_MASK                       0x000000e0
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY_NV       0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT_NV         0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE_NV           0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL_NV                0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE_NV                0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY_NV         0x00000006
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE_NV           0x00000007
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_INPUT_SHIFT                                8
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_INPUT_MASK                         0x00000f00
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_INPUT_ZERO                         0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0_NV           0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_INPUT_FOG                          0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_INPUT_PRIMARY_COLOR_NV             0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_INPUT_SECONDARY_COLOR_NV           0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_INPUT_TEXTURE1_ARB                 0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_INPUT_TEXTURE0_ARB                 0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_INPUT_SPARE0_NV                    0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_INPUT_SPARE1_NV                    0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_INPUT_E_TIMES_F_NV                 0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_COMPONENT_USAGE                    (1 << 12)
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_COMPONENT_USAGE_RGB                        0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_COMPONENT_USAGE_ALPHA              0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_MAPPING_SHIFT                      13
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_MAPPING_MASK                       0x0000e000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY_NV       0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT_NV         0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE_NV           0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL_NV                0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE_NV                0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY_NV         0x00000006
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE_NV           0x00000007
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_INPUT_SHIFT                                16
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_INPUT_MASK                         0x000f0000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_INPUT_ZERO                         0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0_NV           0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_INPUT_FOG                          0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_INPUT_PRIMARY_COLOR_NV             0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_INPUT_SECONDARY_COLOR_NV           0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_INPUT_TEXTURE1_ARB                 0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_INPUT_TEXTURE0_ARB                 0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_INPUT_SPARE0_NV                    0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_INPUT_SPARE1_NV                    0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_INPUT_E_TIMES_F_NV                 0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_COMPONENT_USAGE                    (1 << 20)
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_COMPONENT_USAGE_RGB                        0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_COMPONENT_USAGE_ALPHA              0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_MAPPING_SHIFT                      21
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_MAPPING_MASK                       0x00e00000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY_NV       0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT_NV         0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE_NV           0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL_NV                0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE_NV                0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY_NV         0x00000006
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE_NV           0x00000007
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_INPUT_SHIFT                                24
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_INPUT_MASK                         0x0f000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_INPUT_ZERO                         0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0_NV           0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_INPUT_FOG                          0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_INPUT_PRIMARY_COLOR_NV             0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_INPUT_SECONDARY_COLOR_NV           0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_INPUT_TEXTURE1_ARB                 0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_INPUT_TEXTURE0_ARB                 0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_INPUT_SPARE0_NV                    0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_INPUT_SPARE1_NV                    0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_INPUT_E_TIMES_F_NV                 0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_COMPONENT_USAGE                    (1 << 28)
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_COMPONENT_USAGE_RGB                        0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_COMPONENT_USAGE_ALPHA              0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_MAPPING_SHIFT                      29
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_MAPPING_MASK                       0xe0000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY_NV       0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT_NV         0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE_NV           0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL_NV                0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE_NV                0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY_NV         0x00000006
+#define   NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE_NV           0x00000007
+#define  NV10_TCL_PRIMITIVE_3D_RC_COLOR(x)                                     (0x00000270+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_RC_COLOR__SIZE                                  0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_COLOR_B_SHIFT                               0
+#define   NV10_TCL_PRIMITIVE_3D_RC_COLOR_B_MASK                                        0x000000ff
+#define   NV10_TCL_PRIMITIVE_3D_RC_COLOR_G_SHIFT                               8
+#define   NV10_TCL_PRIMITIVE_3D_RC_COLOR_G_MASK                                        0x0000ff00
+#define   NV10_TCL_PRIMITIVE_3D_RC_COLOR_R_SHIFT                               16
+#define   NV10_TCL_PRIMITIVE_3D_RC_COLOR_R_MASK                                        0x00ff0000
+#define   NV10_TCL_PRIMITIVE_3D_RC_COLOR_A_SHIFT                               24
+#define   NV10_TCL_PRIMITIVE_3D_RC_COLOR_A_MASK                                        0xff000000
+#define  NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA(x)                                 (0x00000278+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA__SIZE                              0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_OUTPUT_SHIFT                   0
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_OUTPUT_MASK                    0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_OUTPUT_ZERO                    0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0_NV      0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1_NV      0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_OUTPUT_FOG                     0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR_NV                0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR_NV      0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1_ARB            0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0_ARB            0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_NV               0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_OUTPUT_SPARE1_NV               0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F_NV            0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SHIFT                   4
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_MASK                    0x000000f0
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_ZERO                    0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0_NV      0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1_NV      0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_FOG                     0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR_NV                0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR_NV      0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1_ARB            0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0_ARB            0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_NV               0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE1_NV               0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F_NV            0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SHIFT                  8
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_MASK                   0x00000f00
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_ZERO                   0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0_NV     0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1_NV     0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_FOG                    0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR_NV       0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR_NV     0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1_ARB           0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0_ARB           0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_NV              0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1_NV              0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F_NV           0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT                    (1 << 12)
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT                    (1 << 13)
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM                           (1 << 14)
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS                              (1 << 15)
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS_NONE                         0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SHIFT                       17
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_MASK                                0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_NONE                                0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO_NV             0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR_NV            0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF_NV                0x00000003
+#define  NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB(x)                                   (0x00000280+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB__SIZE                                        0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_OUTPUT_SHIFT                     0
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_OUTPUT_MASK                      0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_OUTPUT_ZERO                      0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0_NV                0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1_NV                0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_OUTPUT_FOG                       0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR_NV          0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR_NV                0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE1_ARB              0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE0_ARB              0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_OUTPUT_SPARE0_NV                 0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_OUTPUT_SPARE1_NV                 0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F_NV              0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SHIFT                     4
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_MASK                      0x000000f0
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_ZERO                      0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0_NV                0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1_NV                0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_FOG                       0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR_NV          0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR_NV                0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE1_ARB              0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE0_ARB              0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0_NV                 0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE1_NV                 0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F_NV              0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SHIFT                    8
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_MASK                     0x00000f00
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_ZERO                     0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0_NV       0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1_NV       0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_FOG                      0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR_NV         0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR_NV       0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1_ARB             0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0_ARB             0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0_NV                        0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE1_NV                        0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F_NV             0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT                      (1 << 12)
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT                      (1 << 13)
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM                             (1 << 14)
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS                                        (1 << 15)
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS_NONE                           0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV   0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SHIFT                         17
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_MASK                          0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_NONE                          0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_TWO_NV               0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_FOUR_NV              0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF_NV          0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_OPERATION_SHIFT                     27
+#define   NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_OPERATION_MASK                      0x38000000
+#define  NV10_TCL_PRIMITIVE_3D_RC_FINAL0                                       0x00000288
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_INPUT_SHIFT                                0
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_INPUT_MASK                         0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_INPUT_ZERO                         0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_INPUT_CONSTANT_COLOR0_NV           0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_INPUT_CONSTANT_COLOR1_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_INPUT_FOG                          0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_INPUT_PRIMARY_COLOR_NV             0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_INPUT_SECONDARY_COLOR_NV           0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_INPUT_TEXTURE1_ARB                 0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_INPUT_TEXTURE0_ARB                 0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_INPUT_SPARE0_NV                    0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_INPUT_SPARE1_NV                    0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_INPUT_E_TIMES_F_NV                 0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_COMPONENT_USAGE                    (1 <<  4)
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_COMPONENT_USAGE_RGB                        0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_COMPONENT_USAGE_ALPHA              0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_MAPPING_SHIFT                      5
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_MAPPING_MASK                       0x000000e0
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY_NV       0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT_NV         0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_MAPPING_EXPAND_NORMAL_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_MAPPING_EXPAND_NEGATE_NV           0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL_NV                0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE_NV                0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY_NV         0x00000006
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_D_MAPPING_SIGNED_NEGATE_NV           0x00000007
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_INPUT_SHIFT                                8
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_INPUT_MASK                         0x00000f00
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_INPUT_ZERO                         0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_INPUT_CONSTANT_COLOR0_NV           0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_INPUT_CONSTANT_COLOR1_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_INPUT_FOG                          0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_INPUT_PRIMARY_COLOR_NV             0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_INPUT_SECONDARY_COLOR_NV           0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_INPUT_TEXTURE1_ARB                 0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_INPUT_TEXTURE0_ARB                 0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_INPUT_SPARE0_NV                    0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_INPUT_SPARE1_NV                    0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_INPUT_E_TIMES_F_NV                 0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_COMPONENT_USAGE                    (1 << 12)
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_COMPONENT_USAGE_RGB                        0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_COMPONENT_USAGE_ALPHA              0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_MAPPING_SHIFT                      13
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_MAPPING_MASK                       0x0000e000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY_NV       0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT_NV         0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_MAPPING_EXPAND_NORMAL_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_MAPPING_EXPAND_NEGATE_NV           0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL_NV                0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE_NV                0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY_NV         0x00000006
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_C_MAPPING_SIGNED_NEGATE_NV           0x00000007
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_INPUT_SHIFT                                16
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_INPUT_MASK                         0x000f0000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_INPUT_ZERO                         0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_INPUT_CONSTANT_COLOR0_NV           0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_INPUT_CONSTANT_COLOR1_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_INPUT_FOG                          0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_INPUT_PRIMARY_COLOR_NV             0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_INPUT_SECONDARY_COLOR_NV           0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_INPUT_TEXTURE1_ARB                 0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_INPUT_TEXTURE0_ARB                 0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_INPUT_SPARE0_NV                    0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_INPUT_SPARE1_NV                    0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_INPUT_E_TIMES_F_NV                 0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_COMPONENT_USAGE                    (1 << 20)
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_COMPONENT_USAGE_RGB                        0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_COMPONENT_USAGE_ALPHA              0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_MAPPING_SHIFT                      21
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_MAPPING_MASK                       0x00e00000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY_NV       0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT_NV         0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_MAPPING_EXPAND_NORMAL_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_MAPPING_EXPAND_NEGATE_NV           0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL_NV                0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE_NV                0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY_NV         0x00000006
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_B_MAPPING_SIGNED_NEGATE_NV           0x00000007
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_INPUT_SHIFT                                24
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_INPUT_MASK                         0x0f000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_INPUT_ZERO                         0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_INPUT_CONSTANT_COLOR0_NV           0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_INPUT_CONSTANT_COLOR1_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_INPUT_FOG                          0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_INPUT_PRIMARY_COLOR_NV             0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_INPUT_SECONDARY_COLOR_NV           0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_INPUT_TEXTURE1_ARB                 0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_INPUT_TEXTURE0_ARB                 0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_INPUT_SPARE0_NV                    0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_INPUT_SPARE1_NV                    0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_INPUT_E_TIMES_F_NV                 0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_COMPONENT_USAGE                    (1 << 28)
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_COMPONENT_USAGE_RGB                        0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_COMPONENT_USAGE_ALPHA              0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_MAPPING_SHIFT                      29
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_MAPPING_MASK                       0xe0000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY_NV       0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT_NV         0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_MAPPING_EXPAND_NORMAL_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_MAPPING_EXPAND_NEGATE_NV           0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL_NV                0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE_NV                0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY_NV         0x00000006
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL0_A_MAPPING_SIGNED_NEGATE_NV           0x00000007
+#define  NV10_TCL_PRIMITIVE_3D_RC_FINAL1                                       0x0000028c
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP                      (1 <<  7)
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_INPUT_SHIFT                                8
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_INPUT_MASK                         0x00000f00
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_INPUT_ZERO                         0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_INPUT_CONSTANT_COLOR0_NV           0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_INPUT_CONSTANT_COLOR1_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_INPUT_FOG                          0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_INPUT_PRIMARY_COLOR_NV             0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_INPUT_SECONDARY_COLOR_NV           0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_INPUT_TEXTURE1_ARB                 0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_INPUT_TEXTURE0_ARB                 0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_INPUT_SPARE0_NV                    0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_INPUT_SPARE1_NV                    0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_INPUT_E_TIMES_F_NV                 0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_COMPONENT_USAGE                    (1 << 12)
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_COMPONENT_USAGE_RGB                        0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_COMPONENT_USAGE_ALPHA              0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_MAPPING_SHIFT                      13
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_MAPPING_MASK                       0x0000e000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY_NV       0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT_NV         0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_MAPPING_EXPAND_NORMAL_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_MAPPING_EXPAND_NEGATE_NV           0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL_NV                0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE_NV                0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY_NV         0x00000006
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_G_MAPPING_SIGNED_NEGATE_NV           0x00000007
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_INPUT_SHIFT                                16
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_INPUT_MASK                         0x000f0000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_INPUT_ZERO                         0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_INPUT_CONSTANT_COLOR0_NV           0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_INPUT_CONSTANT_COLOR1_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_INPUT_FOG                          0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_INPUT_PRIMARY_COLOR_NV             0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_INPUT_SECONDARY_COLOR_NV           0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_INPUT_TEXTURE1_ARB                 0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_INPUT_TEXTURE0_ARB                 0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_INPUT_SPARE0_NV                    0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_INPUT_SPARE1_NV                    0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_INPUT_E_TIMES_F_NV                 0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_COMPONENT_USAGE                    (1 << 20)
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_COMPONENT_USAGE_RGB                        0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_COMPONENT_USAGE_ALPHA              0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_MAPPING_SHIFT                      21
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_MAPPING_MASK                       0x00e00000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY_NV       0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT_NV         0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_MAPPING_EXPAND_NORMAL_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_MAPPING_EXPAND_NEGATE_NV           0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL_NV                0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE_NV                0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY_NV         0x00000006
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_F_MAPPING_SIGNED_NEGATE_NV           0x00000007
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_INPUT_SHIFT                                24
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_INPUT_MASK                         0x0f000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_INPUT_ZERO                         0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_INPUT_CONSTANT_COLOR0_NV           0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_INPUT_CONSTANT_COLOR1_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_INPUT_FOG                          0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_INPUT_PRIMARY_COLOR_NV             0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_INPUT_SECONDARY_COLOR_NV           0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_INPUT_TEXTURE1_ARB                 0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_INPUT_TEXTURE0_ARB                 0x00000009
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_INPUT_SPARE0_NV                    0x0000000c
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_INPUT_SPARE1_NV                    0x0000000d
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV0x0000000e
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_INPUT_E_TIMES_F_NV                 0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_COMPONENT_USAGE                    (1 << 28)
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_COMPONENT_USAGE_RGB                        0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_COMPONENT_USAGE_ALPHA              0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_MAPPING_SHIFT                      29
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_MAPPING_MASK                       0xe0000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY_NV       0x00000000
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT_NV         0x00000001
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_MAPPING_EXPAND_NORMAL_NV           0x00000002
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_MAPPING_EXPAND_NEGATE_NV           0x00000003
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL_NV                0x00000004
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE_NV                0x00000005
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY_NV         0x00000006
+#define   NV10_TCL_PRIMITIVE_3D_RC_FINAL1_E_MAPPING_SIGNED_NEGATE_NV           0x00000007
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL                                     0x00000294
+#define   NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_COLOR_CONTROL                      (1 <<  1)
+#define   NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_LOCAL_VIEWER                       (1 << 16)
+#define  NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE                           0x00000298
+#define   NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_SPECULAR                 (1 <<  0)
+#define   NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_DIFFUSE                  (1 <<  1)
+#define   NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_AMBIENT                  (1 <<  2)
+#define   NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_EMISSION                 (1 <<  3)
+#define  NV10_TCL_PRIMITIVE_3D_FOG_MODE                                                0x0000029c
+#define  NV10_TCL_PRIMITIVE_3D_FOG_MODE_EXP                                    0x00000800
+#define  NV10_TCL_PRIMITIVE_3D_FOG_MODE_EXP_2                                  0x00000802
+#define  NV10_TCL_PRIMITIVE_3D_FOG_MODE_EXP2                                   0x00000803
+#define  NV10_TCL_PRIMITIVE_3D_FOG_MODE_LINEAR                                 0x00000804
+#define  NV10_TCL_PRIMITIVE_3D_FOG_MODE_LINEAR_2                               0x00002601
+#define  NV10_TCL_PRIMITIVE_3D_FOG_COORD_DIST                                  0x000002a0
+#define  NV10_TCL_PRIMITIVE_3D_FOG_ENABLE                                      0x000002a4
+#define  NV10_TCL_PRIMITIVE_3D_FOG_COLOR                                       0x000002a8
+#define   NV10_TCL_PRIMITIVE_3D_FOG_COLOR_R_SHIFT                              0
+#define   NV10_TCL_PRIMITIVE_3D_FOG_COLOR_R_MASK                               0x000000ff
+#define   NV10_TCL_PRIMITIVE_3D_FOG_COLOR_G_SHIFT                              8
+#define   NV10_TCL_PRIMITIVE_3D_FOG_COLOR_G_MASK                               0x0000ff00
+#define   NV10_TCL_PRIMITIVE_3D_FOG_COLOR_B_SHIFT                              16
+#define   NV10_TCL_PRIMITIVE_3D_FOG_COLOR_B_MASK                               0x00ff0000
+#define   NV10_TCL_PRIMITIVE_3D_FOG_COLOR_A_SHIFT                              24
+#define   NV10_TCL_PRIMITIVE_3D_FOG_COLOR_A_MASK                               0xff000000
+#define  NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_MODE                              0x000002b4
+#define  NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(x)                          (0x000002c0+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ__SIZE                       0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_CLIP_L_SHIFT               0
+#define   NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_CLIP_L_MASK                        0x000007ff
+#define   NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_CLIP_LEFT_ENABLE           (1 << 11)
+#define   NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_CLIP_R_SHIFT               16
+#define   NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_CLIP_R_MASK                        0x07ff0000
+#define   NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_CLIP_RIGHT_ENABLE          (1 << 27)
+#define  NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT(x)                           (0x000002e0+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT__SIZE                                0x00000008
+#define   NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_CLIP_T_SHIFT                        0
+#define   NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_CLIP_T_MASK                 0x000007ff
+#define   NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_CLIP_TOP_ENABLE             (1 << 11)
+#define   NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_CLIP_B_SHIFT                        16
+#define   NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_CLIP_B_MASK                 0x07ff0000
+#define   NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_CLIP_BOTTOM_ENABLE          (1 << 27)
+#define  NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_ENABLE                               0x00000300
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_ENABLE                               0x00000304
+#define  NV10_TCL_PRIMITIVE_3D_CULL_FACE_ENABLE                                        0x00000308
+#define  NV10_TCL_PRIMITIVE_3D_DEPTH_TEST_ENABLE                               0x0000030c
+#define  NV10_TCL_PRIMITIVE_3D_DITHER_ENABLE                                   0x00000310
+#define  NV10_TCL_PRIMITIVE_3D_LIGHTING_ENABLE                                 0x00000314
+#define  NV10_TCL_PRIMITIVE_3D_POINT_PARAMETERS_ENABLE                         0x00000318
+#define  NV10_TCL_PRIMITIVE_3D_POINT_SMOOTH_ENABLE                             0x0000031c
+#define  NV10_TCL_PRIMITIVE_3D_LINE_SMOOTH_ENABLE                              0x00000320
+#define  NV10_TCL_PRIMITIVE_3D_POLYGON_SMOOTH_ENABLE                           0x00000324
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_WEIGHT_ENABLE                            0x00000328
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_ENABLE                                  0x0000032c
+#define  NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_POINT_ENABLE                     0x00000330
+#define  NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_LINE_ENABLE                      0x00000334
+#define  NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FILL_ENABLE                      0x00000338
+#define  NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC                                 0x0000033c
+#define  NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_NEVER                           0x00000200
+#define  NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_LESS                            0x00000201
+#define  NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_EQUAL                           0x00000202
+#define  NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_LEQUAL                          0x00000203
+#define  NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_GREATER                         0x00000204
+#define  NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_GREATER                         0x00000204
+#define  NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_NOTEQUAL                                0x00000205
+#define  NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_GEQUAL                          0x00000206
+#define  NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_ALWAYS                          0x00000207
+#define  NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_REF                                  0x00000340
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC                                  0x00000344
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ZERO                             0x00000000
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ONE                              0x00000001
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_SRC_COLOR                                0x00000300
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ONE_MINUS_SRC_COLOR              0x00000301
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_SRC_ALPHA                                0x00000302
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ONE_MINUS_SRC_ALPHA              0x00000303
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_DST_ALPHA                                0x00000304
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ONE_MINUS_DST_ALPHA              0x00000305
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_DST_COLOR                                0x00000306
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ONE_MINUS_DST_COLOR              0x00000307
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_SRC_ALPHA_SATURATE               0x00000308
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_CONSTANT_COLOR                   0x00008001
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_COLOR         0x00008002
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_CONSTANT_ALPHA                   0x00008003
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_ALPHA         0x00008004
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_DST                                  0x00000348
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ZERO                             0x00000000
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ONE                              0x00000001
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_SRC_COLOR                                0x00000300
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ONE_MINUS_SRC_COLOR              0x00000301
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_SRC_ALPHA                                0x00000302
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ONE_MINUS_SRC_ALPHA              0x00000303
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_DST_ALPHA                                0x00000304
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ONE_MINUS_DST_ALPHA              0x00000305
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_DST_COLOR                                0x00000306
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ONE_MINUS_DST_COLOR              0x00000307
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_SRC_ALPHA_SATURATE               0x00000308
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_CONSTANT_COLOR                   0x00008001
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_COLOR         0x00008002
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_CONSTANT_ALPHA                   0x00008003
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_ALPHA         0x00008004
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_COLOR                                     0x0000034c
+#define   NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_B_SHIFT                            0
+#define   NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_B_MASK                             0x000000ff
+#define   NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_G_SHIFT                            8
+#define   NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_G_MASK                             0x0000ff00
+#define   NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_R_SHIFT                            16
+#define   NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_R_MASK                             0x00ff0000
+#define   NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_A_SHIFT                            24
+#define   NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_A_MASK                             0xff000000
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_EQUATION                                  0x00000350
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_EQUATION_FUNC_ADD                         0x00008006
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_EQUATION_MIN                              0x00008007
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_EQUATION_MAX                              0x00008008
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_EQUATION_FUNC_SUBTRACT                    0x0000800a
+#define  NV10_TCL_PRIMITIVE_3D_BLEND_EQUATION_FUNC_REVERSE_SUBTRACT            0x0000800b
+#define  NV10_TCL_PRIMITIVE_3D_DEPTH_FUNC                                      0x00000354
+#define  NV10_TCL_PRIMITIVE_3D_COLOR_MASK                                      0x00000358
+#define   NV10_TCL_PRIMITIVE_3D_COLOR_MASK_B                                   (1 <<  0)
+#define   NV10_TCL_PRIMITIVE_3D_COLOR_MASK_G                                   (1 <<  8)
+#define   NV10_TCL_PRIMITIVE_3D_COLOR_MASK_R                                   (1 << 16)
+#define   NV10_TCL_PRIMITIVE_3D_COLOR_MASK_A                                   (1 << 24)
+#define  NV10_TCL_PRIMITIVE_3D_DEPTH_WRITE_ENABLE                              0x0000035c
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_MASK                                    0x00000360
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC                               0x00000364
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC_NEVER                         0x00000200
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC_LESS                          0x00000201
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC_EQUAL                         0x00000202
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC_LEQUAL                                0x00000203
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC_GREATER                       0x00000204
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC_GREATER                       0x00000204
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC_NOTEQUAL                      0x00000205
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC_GEQUAL                                0x00000206
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC_ALWAYS                                0x00000207
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_FUNC_REF                                        0x00000368
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_FUNC_MASK                               0x0000036c
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL                                 0x00000370
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL_ZERO                            0x00000000
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL_INVERT                          0x0000150a
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL_KEEP                            0x00001e00
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL_REPLACE                         0x00001e01
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL_INCR                            0x00001e02
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL_DECR                            0x00001e03
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL_INCR_WRAP                       0x00008507
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL_DECR_WRAP                       0x00008508
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL                                        0x00000374
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL_ZERO                           0x00000000
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL_INVERT                         0x0000150a
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL_KEEP                           0x00001e00
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL_REPLACE                                0x00001e01
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL_INCR                           0x00001e02
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL_DECR                           0x00001e03
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL_INCR_WRAP                      0x00008507
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL_DECR_WRAP                      0x00008508
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS                                        0x00000378
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS_ZERO                           0x00000000
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS_INVERT                         0x0000150a
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS_KEEP                           0x00001e00
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS_REPLACE                                0x00001e01
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS_INCR                           0x00001e02
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS_DECR                           0x00001e03
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS_INCR_WRAP                      0x00008507
+#define  NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS_DECR_WRAP                      0x00008508
+#define  NV10_TCL_PRIMITIVE_3D_SHADE_MODEL                                     0x0000037c
+#define  NV10_TCL_PRIMITIVE_3D_SHADE_MODEL_FLAT                                        0x00001d00
+#define  NV10_TCL_PRIMITIVE_3D_SHADE_MODEL_SMOOTH                              0x00001d01
+#define  NV10_TCL_PRIMITIVE_3D_LINE_WIDTH                                      0x00000380
+#define  NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FACTOR                           0x00000384
+#define  NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_UNITS                            0x00000388
+#define  NV10_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT                              0x0000038c
+#define  NV10_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT_POINT                                0x00001b00
+#define  NV10_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT_LINE                         0x00001b01
+#define  NV10_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT_FILL                         0x00001b02
+#define  NV10_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK                               0x00000390
+#define  NV10_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK_POINT                         0x00001b00
+#define  NV10_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK_LINE                          0x00001b01
+#define  NV10_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK_FILL                          0x00001b02
+#define  NV10_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR                                        0x00000394
+#define  NV10_TCL_PRIMITIVE_3D_DEPTH_RANGE_FAR                                 0x00000398
+#define  NV10_TCL_PRIMITIVE_3D_CULL_FACE                                       0x0000039c
+#define  NV10_TCL_PRIMITIVE_3D_CULL_FACE_FRONT                                 0x00000404
+#define  NV10_TCL_PRIMITIVE_3D_CULL_FACE_BACK                                  0x00000405
+#define  NV10_TCL_PRIMITIVE_3D_CULL_FACE_FRONT_AND_BACK                                0x00000408
+#define  NV10_TCL_PRIMITIVE_3D_FRONT_FACE                                      0x000003a0
+#define  NV10_TCL_PRIMITIVE_3D_FRONT_FACE_CW                                   0x00000900
+#define  NV10_TCL_PRIMITIVE_3D_FRONT_FACE_CCW                                  0x00000901
+#define  NV10_TCL_PRIMITIVE_3D_NORMALIZE_ENABLE                                        0x000003a4
+#define  NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_R                                        0x000003a8
+#define  NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_G                                        0x000003ac
+#define  NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_B                                        0x000003b0
+#define  NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_A                                        0x000003b4
+#define  NV10_TCL_PRIMITIVE_3D_COLOR_CONTROL                                   0x000003b8
+#define  NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS                                  0x000003bc
+#define   NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT0                          (1 <<  0)
+#define   NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT1                          (1 <<  2)
+#define   NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT2                          (1 <<  4)
+#define   NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT3                          (1 <<  6)
+#define   NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT4                          (1 <<  8)
+#define   NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT5                          (1 << 10)
+#define   NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT6                          (1 << 12)
+#define   NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT7                          (1 << 14)
+#define  NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE(x)                            (0x000003c0+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE__SIZE                         0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE_FALSE                         0x00000000
+#define  NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE_EYE_LINEAR                    0x00002400
+#define  NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE_OBJECT_LINEAR                 0x00002401
+#define  NV10_TCL_PRIMITIVE_3D_TX_MATRIX_ENABLE(x)                             (0x000003e0+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_TX_MATRIX_ENABLE__SIZE                          0x00000002
+#define  NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE                              0x000003e8
+#define   NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_MODELVIEW1                  (1 <<  0)
+#define   NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_MODELVIEW0                  (1 <<  1)
+#define   NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_PROJECTION                  (1 <<  2)
+#define  NV10_TCL_PRIMITIVE_3D_POINT_SIZE                                      0x000003ec
+#define  NV10_TCL_PRIMITIVE_3D_MODELVIEW0_MATRIX(x)                            (0x00000400+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_MODELVIEW0_MATRIX__SIZE                         0x00000010
+#define  NV10_TCL_PRIMITIVE_3D_MODELVIEW1_MATRIX(x)                            (0x00000440+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_MODELVIEW1_MATRIX__SIZE                         0x00000010
+#define  NV10_TCL_PRIMITIVE_3D_INVERSE_MODELVIEW0_MATRIX(x)                    (0x00000480+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_INVERSE_MODELVIEW0_MATRIX__SIZE                 0x00000010
+#define  NV10_TCL_PRIMITIVE_3D_INVERSE_MODELVIEW1_MATRIX(x)                    (0x000004c0+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_INVERSE_MODELVIEW1_MATRIX__SIZE                 0x00000010
+#define  NV10_TCL_PRIMITIVE_3D_PROJECTION_MATRIX(x)                            (0x00000500+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_PROJECTION_MATRIX__SIZE                         0x00000010
+#define  NV10_TCL_PRIMITIVE_3D_TX0_MATRIX(x)                                   (0x00000540+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_TX0_MATRIX__SIZE                                        0x00000010
+#define  NV10_TCL_PRIMITIVE_3D_TX1_MATRIX(x)                                   (0x00000580+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_TX1_MATRIX__SIZE                                        0x00000010
+#define  NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_A(x)                                 (0x00000600+((x)*16))
+#define  NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_A__SIZE                              0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_B(x)                                 (0x00000604+((x)*16))
+#define  NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_B__SIZE                              0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_C(x)                                 (0x00000608+((x)*16))
+#define  NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_C__SIZE                              0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_D(x)                                 (0x0000060c+((x)*16))
+#define  NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_D__SIZE                              0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_FOG_EQUATION_CONSTANT                           0x00000680
+#define  NV10_TCL_PRIMITIVE_3D_FOG_EQUATION_LINEAR                             0x00000684
+#define  NV10_TCL_PRIMITIVE_3D_FOG_EQUATION_QUADRATIC                          0x00000688
+#define  NV10_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS(x)                     (0x000006a0+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS__SIZE                  0x00000006
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R0x000006c4
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G0x000006c8
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B0x000006cc
+#define  NV10_TCL_PRIMITIVE_3D_VIEWPORT_SCALE_X                                        0x000006e8
+#define  NV10_TCL_PRIMITIVE_3D_VIEWPORT_SCALE_Y                                        0x000006ec
+#define  NV10_TCL_PRIMITIVE_3D_VIEWPORT_SCALE_Z                                        0x000006f0
+#define  NV10_TCL_PRIMITIVE_3D_VIEWPORT_SCALE_W                                        0x000006f4
+#define  NV10_TCL_PRIMITIVE_3D_POINT_PARAMETER(x)                              (0x000006f8+((x)*4))
+#define  NV10_TCL_PRIMITIVE_3D_POINT_PARAMETER__SIZE                           0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(x)           (0x00000800+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R__SIZE                0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G(x)           (0x00000804+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G__SIZE                0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B(x)           (0x00000808+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B__SIZE                0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(x)           (0x0000080c+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R__SIZE                0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G(x)           (0x00000810+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G__SIZE                0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B(x)           (0x00000814+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B__SIZE                0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(x)          (0x00000818+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R__SIZE       0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G(x)          (0x0000081c+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G__SIZE       0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B(x)          (0x00000820+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B__SIZE       0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_X(x)                          (0x00000828+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_X__SIZE                       0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_Y(x)                          (0x0000082c+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_Y__SIZE                       0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_Z(x)                          (0x00000830+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_Z__SIZE                       0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_X(x)                            (0x00000834+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_X__SIZE                         0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_Y(x)                            (0x00000838+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_Y__SIZE                         0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_Z(x)                            (0x0000083c+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_Z__SIZE                         0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A(x)                          (0x00000840+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A__SIZE                       0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_B(x)                          (0x00000844+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_B__SIZE                       0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_C(x)                          (0x00000848+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_C__SIZE                       0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_X(x)                             (0x0000084c+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_X__SIZE                          0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_Y(x)                             (0x00000850+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_Y__SIZE                          0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_Z(x)                             (0x00000854+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_Z__SIZE                          0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_D(x)                          (0x00000858+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_D__SIZE                       0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_POSITION_X(x)                             (0x0000085c+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_POSITION_X__SIZE                          0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_POSITION_Y(x)                             (0x00000860+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_POSITION_Y__SIZE                          0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_POSITION_Z(x)                             (0x00000864+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_POSITION_Z__SIZE                          0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_ATTENUATION_CONSTANT(x)                   (0x00000868+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_ATTENUATION_CONSTANT__SIZE                        0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_ATTENUATION_LINEAR(x)                     (0x0000086c+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_ATTENUATION_LINEAR__SIZE                  0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_ATTENUATION_QUADRATIC(x)                  (0x00000870+((x)*128))
+#define  NV10_TCL_PRIMITIVE_3D_LIGHT_ATTENUATION_QUADRATIC__SIZE               0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_POS_3F_X                                 0x00000c00
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_POS_3F_Y                                 0x00000c04
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_POS_3F_Z                                 0x00000c08
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_POS_4F_X                                 0x00000c18
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_POS_4F_Y                                 0x00000c1c
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_POS_4F_Z                                 0x00000c20
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_POS_4F_W                                 0x00000c24
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_X                                 0x00000c30
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_Y                                 0x00000c34
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_Z                                 0x00000c38
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY                                        0x00000c40
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_X_SHIFT                       0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_X_MASK                                0x0000ffff
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_SHIFT                       16
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_MASK                                0xffff0000
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z                                 0x00000c44
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z_Z_SHIFT                                0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z_Z_MASK                         0x0000ffff
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4F_R                                 0x00000c50
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4F_G                                 0x00000c54
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4F_B                                 0x00000c58
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4F_A                                 0x00000c5c
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_COL_3F_R                                 0x00000c60
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_COL_3F_G                                 0x00000c64
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_COL_3F_B                                 0x00000c68
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I                                   0x00000c6c
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_R_SHIFT                          0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_R_MASK                           0x000000ff
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_SHIFT                          8
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_MASK                           0x0000ff00
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_SHIFT                          16
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_MASK                           0x00ff0000
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_SHIFT                          24
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_MASK                           0xff000000
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_R                                        0x00000c80
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_G                                        0x00000c84
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_B                                        0x00000c88
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I                                  0x00000c8c
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_R_SHIFT                         0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_R_MASK                          0x000000ff
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_G_SHIFT                         8
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_G_MASK                          0x0000ff00
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_B_SHIFT                         16
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_B_MASK                          0x00ff0000
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_2F_S                                 0x00000c90
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_2F_T                                 0x00000c94
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_2I                                   0x00000c98
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_S_SHIFT                          0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_S_MASK                           0x0000ffff
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_T_SHIFT                          16
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_T_MASK                           0xffff0000
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_S                                 0x00000ca0
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_T                                 0x00000ca4
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_R                                 0x00000ca8
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_Q                                 0x00000cac
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST                                        0x00000cb0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_S_SHIFT                       0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_S_MASK                                0x0000ffff
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_T_SHIFT                       16
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_T_MASK                                0xffff0000
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ                                        0x00000cb4
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_R_SHIFT                       0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_R_MASK                                0x0000ffff
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_Q_SHIFT                       16
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_Q_MASK                                0xffff0000
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_2F_S                                 0x00000cb8
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_2F_T                                 0x00000cbc
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_2I                                   0x00000cc0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_S_SHIFT                          0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_S_MASK                           0x0000ffff
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_T_SHIFT                          16
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_T_MASK                           0xffff0000
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_S                                 0x00000cc8
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_T                                 0x00000ccc
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_R                                 0x00000cd0
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_Q                                 0x00000cd4
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST                                        0x00000cd8
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_S_SHIFT                       0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_S_MASK                                0x0000ffff
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_T_SHIFT                       16
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_T_MASK                                0xffff0000
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ                                        0x00000cdc
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_R_SHIFT                       0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_R_MASK                                0x0000ffff
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_Q_SHIFT                       16
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_Q_MASK                                0xffff0000
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_FOG_1F                                   0x00000ce0
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_WGH_1F                                   0x00000ce4
+#define  NV10_TCL_PRIMITIVE_3D_EDGEFLAG_ENABLE                                 0x00000cec
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_VALIDATE                           0x00000cf0
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_POS                         0x00000d00
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_POS                         0x00000d04
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_POS_TYPE_SHIFT             0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_POS_TYPE_MASK              0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_POS_FIELDS_SHIFT           4
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_POS_FIELDS_MASK            0x000000f0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_POS_STRIDE_SHIFT           8
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_POS_STRIDE_MASK            0x0000ff00
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_COL                         0x00000d08
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL                         0x00000d0c
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL_TYPE_SHIFT             0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL_TYPE_MASK              0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL_FIELDS_SHIFT           4
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL_FIELDS_MASK            0x000000f0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL_STRIDE_SHIFT           8
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL_STRIDE_MASK            0x0000ff00
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_COL2                                0x00000d10
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL2                                0x00000d14
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL2_TYPE_SHIFT            0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL2_TYPE_MASK             0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL2_FIELDS_SHIFT          4
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL2_FIELDS_MASK           0x000000f0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL2_STRIDE_SHIFT          8
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL2_STRIDE_MASK           0x0000ff00
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_TX0                         0x00000d18
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX0                         0x00000d1c
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX0_TYPE_SHIFT             0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX0_TYPE_MASK              0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX0_FIELDS_SHIFT           4
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX0_FIELDS_MASK            0x000000f0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX0_STRIDE_SHIFT           8
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX0_STRIDE_MASK            0x0000ff00
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_TX1                         0x00000d20
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX1                         0x00000d24
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX1_TYPE_SHIFT             0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX1_TYPE_MASK              0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX1_FIELDS_SHIFT           4
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX1_FIELDS_MASK            0x000000f0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX1_STRIDE_SHIFT           8
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX1_STRIDE_MASK            0x0000ff00
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_NOR                         0x00000d28
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_NOR                         0x00000d2c
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_NOR_TYPE_SHIFT             0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_NOR_TYPE_MASK              0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_NOR_FIELDS_SHIFT           4
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_NOR_FIELDS_MASK            0x000000f0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_NOR_STRIDE_SHIFT           8
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_NOR_STRIDE_MASK            0x0000ff00
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_WGH                         0x00000d30
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_WGH                         0x00000d34
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_WGH_TYPE_SHIFT             0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_WGH_TYPE_MASK              0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_WGH_FIELDS_SHIFT           4
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_WGH_FIELDS_MASK            0x000000f0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_WGH_STRIDE_SHIFT           8
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_WGH_STRIDE_MASK            0x0000ff00
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_FOG                         0x00000d38
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FOG                         0x00000d3c
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FOG_TYPE_SHIFT             0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FOG_TYPE_MASK              0x0000000f
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FOG_FIELDS_SHIFT           4
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FOG_FIELDS_MASK            0x000000f0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FOG_STRIDE_SHIFT           8
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FOG_STRIDE_MASK            0x0000ff00
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END                                        0x00000dfc
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_STOP                           0x00000000
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_POINTS                         0x00000001
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_LINES                          0x00000002
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_LINE_LOOP                      0x00000003
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_LINE_STRIP                     0x00000004
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_TRIANGLES                      0x00000005
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_TRIANGLE_STRIP                 0x00000006
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_TRIANGLE_FAN                   0x00000007
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_QUADS                          0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_QUAD_STRIP                     0x00000009
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_POLYGON                                0x0000000a
+#define  NV10_TCL_PRIMITIVE_3D_DRAW_INDEX                                      0x00000e00
+#define   NV10_TCL_PRIMITIVE_3D_DRAW_INDEX_I0_SHIFT                            0
+#define   NV10_TCL_PRIMITIVE_3D_DRAW_INDEX_I0_MASK                             0x0000ffff
+#define   NV10_TCL_PRIMITIVE_3D_DRAW_INDEX_I1_SHIFT                            24
+#define   NV10_TCL_PRIMITIVE_3D_DRAW_INDEX_I1_MASK                             0xff000000
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_BEGIN_END                         0x000013fc
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_BEGIN_END_STOP                    0x00000000
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_BEGIN_END_POINTS                  0x00000001
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_BEGIN_END_LINES                   0x00000002
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_BEGIN_END_LINE_LOOP               0x00000003
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_BEGIN_END_LINE_STRIP              0x00000004
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_BEGIN_END_TRIANGLES               0x00000005
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_BEGIN_END_TRIANGLE_STRIP          0x00000006
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_BEGIN_END_TRIANGLE_FAN            0x00000007
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_BEGIN_END_QUADS                   0x00000008
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_BEGIN_END_QUAD_STRIP              0x00000009
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_BEGIN_END_POLYGON                 0x0000000a
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_DRAW_ARRAYS                       0x00001400
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_DRAW_ARRAYS_FIRST_SHIFT          0
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_DRAW_ARRAYS_FIRST_MASK           0x0000ffff
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_DRAW_ARRAYS_LAST_SHIFT           24
+#define   NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_DRAW_ARRAYS_LAST_MASK            0xff000000
+#define  NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_DATA                               0x00001800
+
+
+#define NV04_CONTEXT_COLOR_KEY                                                 0x00000057
+
+#define  NV04_CONTEXT_COLOR_KEY_NOP                                            0x00000100
+#define  NV04_CONTEXT_COLOR_KEY_NOTIFY                                         0x00000104
+#define  NV04_CONTEXT_COLOR_KEY_DMA_NOTIFY                                     0x00000180
+#define  NV04_CONTEXT_COLOR_KEY_COLOR_FORMAT                                   0x00000300
+#define  NV04_CONTEXT_COLOR_KEY_COLOR                                          0x00000304
+
+
+#define NV03_CONTEXT_SURFACES_2D                                               0x00000058
+
+#define  NV03_CONTEXT_SURFACES_2D_SYNCHRONIZE                                  0x00000100
+#define  NV03_CONTEXT_SURFACES_2D_DMA_NOTIFY                                   0x00000180
+#define  NV03_CONTEXT_SURFACES_2D_DMA_SOURCE                                   0x00000184
+#define  NV03_CONTEXT_SURFACES_2D_DMA_DESTIN                                   0x00000188
+#define  NV03_CONTEXT_SURFACES_2D_COLOR_FORMAT                                 0x00000300
+#define  NV03_CONTEXT_SURFACES_2D_PITCH                                                0x00000304
+#define   NV03_CONTEXT_SURFACES_2D_PITCH_SOURCE_SHIFT                          0
+#define   NV03_CONTEXT_SURFACES_2D_PITCH_SOURCE_MASK                           0x0000ffff
+#define   NV03_CONTEXT_SURFACES_2D_PITCH_DESTIN_SHIFT                          16
+#define   NV03_CONTEXT_SURFACES_2D_PITCH_DESTIN_MASK                           0xffff0000
+#define  NV03_CONTEXT_SURFACES_2D_OFFSET_SOURCE                                        0x00000308
+#define  NV03_CONTEXT_SURFACES_2D_OFFSET_DESTIN                                        0x0000030c
+
+
+#define NV03_CONTEXT_SURFACES_3D                                               0x0000005a
+
+#define  NV03_CONTEXT_SURFACES_3D_SYNCHRONIZE                                  0x00000100
+#define  NV03_CONTEXT_SURFACES_3D_DMA_NOTIFY                                   0x00000180
+#define  NV03_CONTEXT_SURFACES_3D_DMA_SURfACE                                  0x00000184
+#define  NV03_CONTEXT_SURFACES_3D_PITCH                                                0x00000300
+#define  NV03_CONTEXT_SURFACES_3D_OFFSET_COLOR                                 0x00000304
+#define  NV03_CONTEXT_SURFACES_3D_OFFSET_ZETA                                  0x00000308
+
+
+#define NV04_RENDER_SOLID_LINE                                                 0x0000005c
+
+#define  NV04_RENDER_SOLID_LINE_SURFACE                                                0x00000198
+
+
+#define NV_RENDER_SOLID_TRIANGLE                                               0x0000005d
+
+
+
+#define NV_RENDER_SOLID_RECTANGLE                                              0x0000005e
+
+#define  NV_RENDER_SOLID_RECTANGLE_SURFACE                                     0x00000198
+
+
+#define NV_IMAGE_BLIT                                                          0x0000005f
+
+#define  NV_IMAGE_BLIT_NOP                                                     0x00000100
+#define  NV_IMAGE_BLIT_NOTIFY                                                  0x00000104
+#define  NV_IMAGE_BLIT_DMA_NOTIFY                                              0x00000180
+#define  NV_IMAGE_BLIT_COLOR_KEY                                               0x00000184
+#define  NV_IMAGE_BLIT_CLIP_RECTANGLE                                          0x00000188
+#define  NV_IMAGE_BLIT_PATTERN                                                 0x0000018c
+#define  NV_IMAGE_BLIT_ROP                                                     0x00000190
+#define  NV_IMAGE_BLIT_SURFACE                                                 0x0000019c
+#define  NV_IMAGE_BLIT_OPERATION                                               0x000002fc
+#define  NV_IMAGE_BLIT_OPERATION_SRCCOPY_AND                                   0x00000000
+#define  NV_IMAGE_BLIT_OPERATION_ROP_AND                                       0x00000001
+#define  NV_IMAGE_BLIT_OPERATION_BLEND_AND                                     0x00000002
+#define  NV_IMAGE_BLIT_OPERATION_SRCCOPY_PREMULT                               0x00000003
+#define  NV_IMAGE_BLIT_OPERATION_BLEND_PREMULT                                 0x00000004
+#define  NV_IMAGE_BLIT_POINT_IN                                                        0x00000300
+#define   NV_IMAGE_BLIT_POINT_IN_X_SHIFT                                       0
+#define   NV_IMAGE_BLIT_POINT_IN_X_MASK                                                0x0000ffff
+#define   NV_IMAGE_BLIT_POINT_IN_Y_SHIFT                                       16
+#define   NV_IMAGE_BLIT_POINT_IN_Y_MASK                                                0xffff0000
+#define  NV_IMAGE_BLIT_POINT_OUT                                               0x00000304
+#define   NV_IMAGE_BLIT_POINT_OUT_X_SHIFT                                      0
+#define   NV_IMAGE_BLIT_POINT_OUT_X_MASK                                       0x0000ffff
+#define   NV_IMAGE_BLIT_POINT_OUT_Y_SHIFT                                      16
+#define   NV_IMAGE_BLIT_POINT_OUT_Y_MASK                                       0xffff0000
+#define  NV_IMAGE_BLIT_SIZE                                                    0x00000308
+#define   NV_IMAGE_BLIT_SIZE_W_SHIFT                                           0
+#define   NV_IMAGE_BLIT_SIZE_W_MASK                                            0x0000ffff
+#define   NV_IMAGE_BLIT_SIZE_H_SHIFT                                           16
+#define   NV_IMAGE_BLIT_SIZE_H_MASK                                            0xffff0000
+
+
+#define NV04_INDEXED_IMAGE_FROM_CPU                                            0x00000060
+
+#define  NV04_INDEXED_IMAGE_FROM_CPU_NOP                                       0x00000100
+#define  NV04_INDEXED_IMAGE_FROM_CPU_NOTIFY                                    0x00000104
+#define  NV04_INDEXED_IMAGE_FROM_CPU_PATCH                                     0x0000010c
+#define  NV04_INDEXED_IMAGE_FROM_CPU_DMA_NOTIFY                                        0x00000180
+#define  NV04_INDEXED_IMAGE_FROM_CPU_DMA_LUT                                   0x00000184
+#define  NV04_INDEXED_IMAGE_FROM_CPU_COLOR_FORMAT                              0x000003e8
+#define  NV04_INDEXED_IMAGE_FROM_CPU_INDEX_FORMAT                              0x000003ec
+#define  NV04_INDEXED_IMAGE_FROM_CPU_LUT_OFFSET                                        0x000003f0
+#define  NV04_INDEXED_IMAGE_FROM_CPU_POINT                                     0x000003f4
+#define  NV04_INDEXED_IMAGE_FROM_CPU_SIZE_OUT                                  0x000003f8
+#define  NV04_INDEXED_IMAGE_FROM_CPU_SIZE_IN                                   0x000003fc
+#define  NV04_INDEXED_IMAGE_FROM_CPU_COLOR                                     0x00000400
+
+
+#define NV_IMAGE_FROM_CPU                                                      0x00000061
+
+
+
+#define NV10_CONTEXT_SURFACES_2D                                               0x00000062
+
+
+
+#define NV05_SCALED_IMAGE_FROM_MEMORY                                          0x00000063
+
+#define  NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION                                0x000002fc
+#define  NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_DITHER                 0x00000000
+#define  NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE               0x00000001
+#define  NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_SUBTR_TRUNCATE         0x00000002
+
+
+#define NV01_IMAGE_SRCCOPY_AND                                                 0x00000064
+
+#define  NV01_IMAGE_SRCCOPY_AND_NOTIFY                                         0x00000104
+#define  NV01_IMAGE_SRCCOPY_AND_DMA_NOTIFY                                     0x00000180
+#define  NV01_IMAGE_SRCCOPY_AND_IMAGE_OUTPUT                                   0x00000200
+#define  NV01_IMAGE_SRCCOPY_AND_IMAGE_INPUT                                    0x00000204
+
+
+#define NV05_INDEXED_IMAGE_FROM_CPU                                            0x00000064
+
+#define  NV05_INDEXED_IMAGE_FROM_CPU_NOP                                       0x00000100
+#define  NV05_INDEXED_IMAGE_FROM_CPU_NOTIFY                                    0x00000104
+#define  NV05_INDEXED_IMAGE_FROM_CPU_DMA_NOTIFY                                        0x00000180
+#define  NV05_INDEXED_IMAGE_FROM_CPU_DMA_LUT                                   0x00000184
+#define  NV05_INDEXED_IMAGE_FROM_CPU_COLOR_KEY                                 0x00000188
+#define  NV05_INDEXED_IMAGE_FROM_CPU_CLIP_RECTANGLE                            0x0000018c
+#define  NV05_INDEXED_IMAGE_FROM_CPU_PATTERN                                   0x00000190
+#define  NV05_INDEXED_IMAGE_FROM_CPU_ROP                                       0x00000194
+#define  NV05_INDEXED_IMAGE_FROM_CPU_BETA1                                     0x00000198
+#define  NV05_INDEXED_IMAGE_FROM_CPU_BETA4                                     0x0000019c
+#define  NV05_INDEXED_IMAGE_FROM_CPU_SURFACE                                   0x000001a0
+#define  NV05_INDEXED_IMAGE_FROM_CPU_COLOR_CONVERSION                          0x000003e0
+#define  NV05_INDEXED_IMAGE_FROM_CPU_OPERATION                                 0x000003e4
+#define  NV05_INDEXED_IMAGE_FROM_CPU_COLOR_FORMAT                              0x000003e8
+#define  NV05_INDEXED_IMAGE_FROM_CPU_INDEX_FORMAT                              0x000003ec
+#define  NV05_INDEXED_IMAGE_FROM_CPU_LUT_OFFSET                                        0x000003f0
+#define  NV05_INDEXED_IMAGE_FROM_CPU_POINT                                     0x000003f4
+#define  NV05_INDEXED_IMAGE_FROM_CPU_SIZE_OUT                                  0x000003f8
+#define  NV05_INDEXED_IMAGE_FROM_CPU_SIZE_IN                                   0x000003fc
+#define  NV05_INDEXED_IMAGE_FROM_CPU_INDICES                                   0x00000400
+
+
+#define NV05_IMAGE_FROM_CPU                                                    0x00000065
+
+#define  NV05_IMAGE_FROM_CPU_NOP                                               0x00000100
+#define  NV05_IMAGE_FROM_CPU_NOTIFY                                            0x00000104
+#define  NV05_IMAGE_FROM_CPU_DMA_NOTIFY                                                0x00000180
+#define  NV05_IMAGE_FROM_CPU_COLOR_KEY                                         0x00000184
+#define  NV05_IMAGE_FROM_CPU_CLIP_RECTANGLE                                    0x00000188
+#define  NV05_IMAGE_FROM_CPU_PATTERN                                           0x0000018c
+#define  NV05_IMAGE_FROM_CPU_ROP                                               0x00000190
+#define  NV05_IMAGE_FROM_CPU_BETA1                                             0x00000194
+#define  NV05_IMAGE_FROM_CPU_BETA4                                             0x00000198
+#define  NV05_IMAGE_FROM_CPU_SURFACE                                           0x0000019c
+#define  NV05_IMAGE_FROM_CPU_COLOR_CONVERSION                                  0x000002f8
+#define  NV05_IMAGE_FROM_CPU_OPERATION                                         0x000002fc
+#define  NV05_IMAGE_FROM_CPU_COLOR_FORMAT                                      0x00000300
+#define  NV05_IMAGE_FROM_CPU_POINT                                             0x00000304
+#define  NV05_IMAGE_FROM_CPU_SIZE_OUT                                          0x00000308
+#define  NV05_IMAGE_FROM_CPU_SIZE_IN                                           0x0000030c
+#define  NV05_IMAGE_FROM_CPU_COLOR                                             0x00000400
+
+
+#define NV05_STRETCHED_IMAGE_FROM_CPU                                          0x00000066
+
+#define  NV05_STRETCHED_IMAGE_FROM_CPU_NOP                                     0x00000100
+#define  NV05_STRETCHED_IMAGE_FROM_CPU_NOTIFY                                  0x00000104
+#define  NV05_STRETCHED_IMAGE_FROM_CPU_DMA_NOTIFY                              0x00000180
+#define  NV05_STRETCHED_IMAGE_FROM_CPU_COLOR_KEY                               0x00000184
+#define  NV05_STRETCHED_IMAGE_FROM_CPU_PATTERN                                 0x00000188
+#define  NV05_STRETCHED_IMAGE_FROM_CPU_ROP                                     0x0000018c
+#define  NV05_STRETCHED_IMAGE_FROM_CPU_BETA1                                   0x00000190
+#define  NV05_STRETCHED_IMAGE_FROM_CPU_BETA4                                   0x00000194
+#define  NV05_STRETCHED_IMAGE_FROM_CPU_SURFACE                                 0x00000198
+#define  NV05_STRETCHED_IMAGE_FROM_CPU_COLOR_CONVERSION                                0x000002f8
+#define  NV05_STRETCHED_IMAGE_FROM_CPU_OPERATION                               0x000002fc
+#define  NV05_STRETCHED_IMAGE_FROM_CPU_COLOR_FORMAT                            0x00000300
+#define  NV05_STRETCHED_IMAGE_FROM_CPU_SIZE_IN                                 0x00000304
+#define  NV05_STRETCHED_IMAGE_FROM_CPU_DELTA_DX_DU                             0x00000308
+#define  NV05_STRETCHED_IMAGE_FROM_CPU_DELTA_DY_DV                             0x0000030c
+#define  NV05_STRETCHED_IMAGE_FROM_CPU_CLIP_0                                  0x00000310
+#define  NV05_STRETCHED_IMAGE_FROM_CPU_CLIP_1                                  0x00000314
+#define  NV05_STRETCHED_IMAGE_FROM_CPU_POINT12D4                               0x00000318
+#define  NV05_STRETCHED_IMAGE_FROM_CPU_COLOR                                   0x00000400
+
+
+#define NV04_IMAGE_BLEND_PREMULT                                               0x00000067
+
+#define  NV04_IMAGE_BLEND_PREMULT_NOP                                          0x00000100
+#define  NV04_IMAGE_BLEND_PREMULT_NOTIFY                                       0x00000104
+#define  NV04_IMAGE_BLEND_PREMULT_DMA_NOTIFY                                   0x00000180
+#define  NV04_IMAGE_BLEND_PREMULT_IMAGE_OUTPUT                                 0x00000200
+#define  NV04_IMAGE_BLEND_PREMULT_BETA_INPUT                                   0x00000204
+#define  NV04_IMAGE_BLEND_PREMULT_IMAGE_INPUT                                  0x00000208
+
+
+#define NV03_CHANNEL_PIO                                                       0x0000006a
+
+
+
+#define NV03_CHANNEL_DMA                                                       0x0000006b
+
+
+
+#define NV04_BETA_SOLID                                                                0x00000072
+
+#define  NV04_BETA_SOLID_NOP                                                   0x00000100
+#define  NV04_BETA_SOLID_NOTIFY                                                        0x00000104
+#define  NV04_BETA_SOLID_DMA_NOTIFY                                            0x00000180
+#define  NV04_BETA_SOLID_BETA_OUTPUT                                           0x00000200
+#define  NV04_BETA_SOLID_BETA_FACTOR                                           0x00000300
+
+
+#define NV_STRETCHED_IMAGE_FROM_CPU                                            0x00000076
+
+#define  NV_STRETCHED_IMAGE_FROM_CPU_NOP                                       0x00000100
+#define  NV_STRETCHED_IMAGE_FROM_CPU_NOTIFY                                    0x00000104
+#define  NV_STRETCHED_IMAGE_FROM_CPU_PATCH                                     0x0000010c
+#define  NV_STRETCHED_IMAGE_FROM_CPU_DMA_NOTIFY                                        0x00000180
+#define  NV_STRETCHED_IMAGE_FROM_CPU_COLOR_FORMAT                              0x00000300
+#define  NV_STRETCHED_IMAGE_FROM_CPU_SIZE_IN                                   0x00000304
+#define  NV_STRETCHED_IMAGE_FROM_CPU_DELTA_DU_DX                               0x00000308
+#define  NV_STRETCHED_IMAGE_FROM_CPU_DELTA_DV_DY                               0x0000030c
+#define  NV_STRETCHED_IMAGE_FROM_CPU_CLIP_0                                    0x00000310
+#define  NV_STRETCHED_IMAGE_FROM_CPU_CLIP_1                                    0x00000314
+#define  NV_STRETCHED_IMAGE_FROM_CPU_POINT12D4                                 0x00000318
+#define  NV_STRETCHED_IMAGE_FROM_CPU_COLOR                                     0x00000400
+
+
+#define NV04_SCALED_IMAGE_FROM_MEMORY                                          0x00000077
+
+#define  NV04_SCALED_IMAGE_FROM_MEMORY_BETA4                                   0x00000194
+#define  NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE                                 0x00000198
+
+
+#define NV10_TEXTURE_FROM_CPU                                                  0x0000007b
+
+#define  NV10_TEXTURE_FROM_CPU_NOP                                             0x00000100
+#define  NV10_TEXTURE_FROM_CPU_NOTIFY                                          0x00000104
+#define  NV10_TEXTURE_FROM_CPU_WAIT_FOR_IDLE                                   0x00000108
+#define  NV10_TEXTURE_FROM_CPU_PM_TRIGGER                                      0x00000140
+#define  NV10_TEXTURE_FROM_CPU_DMA_NOTIFY                                      0x00000180
+#define  NV10_TEXTURE_FROM_CPU_SURFACE                                         0x00000184
+#define  NV10_TEXTURE_FROM_CPU_COLOR_FORMAT                                    0x00000300
+#define  NV10_TEXTURE_FROM_CPU_POINT                                           0x00000304
+#define   NV10_TEXTURE_FROM_CPU_POINT_X_SHIFT                                  0
+#define   NV10_TEXTURE_FROM_CPU_POINT_X_MASK                                   0x0000ffff
+#define   NV10_TEXTURE_FROM_CPU_POINT_Y_SHIFT                                  16
+#define   NV10_TEXTURE_FROM_CPU_POINT_Y_MASK                                   0xffff0000
+#define  NV10_TEXTURE_FROM_CPU_SIZE                                            0x00000308
+#define   NV10_TEXTURE_FROM_CPU_SIZE_W_SHIFT                                   0
+#define   NV10_TEXTURE_FROM_CPU_SIZE_W_MASK                                    0x0000ffff
+#define   NV10_TEXTURE_FROM_CPU_SIZE_H_SHIFT                                   16
+#define   NV10_TEXTURE_FROM_CPU_SIZE_H_MASK                                    0xffff0000
+#define  NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL                                 0x0000030c
+#define   NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_X_SHIFT                                0
+#define   NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_X_MASK                         0x0000ffff
+#define   NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_W_SHIFT                                16
+#define   NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_W_MASK                         0xffff0000
+#define  NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL                                   0x00000310
+#define   NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_Y_SHIFT                          0
+#define   NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_Y_MASK                           0x0000ffff
+#define   NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_H_SHIFT                          16
+#define   NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_H_MASK                           0xffff0000
+#define  NV10_TEXTURE_FROM_CPU_COLOR(x)                                                (0x00000400+((x)*4))
+#define  NV10_TEXTURE_FROM_CPU_COLOR__SIZE                                     0x00000100
+
+
+#define NV10_VIDEO_DISPLAY                                                     0x0000007c
+
+
+
+#define NV10_DVD_SUBPICTURE                                                    0x00000088
+
+
+
+#define NV10_SCALED_IMAGE_FROM_MEMORY                                          0x00000089
+
+#define  NV10_SCALED_IMAGE_FROM_MEMORY_WAIT_FOR_IDLE                           0x00000108
+
+
+#define NV10_IMAGE_FROM_CPU                                                    0x0000008a
+
+#define  NV10_IMAGE_FROM_CPU_BETA4                                             0x00000198
+#define  NV10_IMAGE_FROM_CPU_SURFACE                                           0x0000019c
+#define  NV10_IMAGE_FROM_CPU_COLOR_CONVERSION                                  0x000002f8
+
+
+#define NV10_CONTEXT_SURFACES_3D                                               0x00000093
+
+
+
+#define NV10_DX5_TEXTURE_TRIANGLE                                              0x00000094
+
+
+
+#define NV10_DX6_MULTI_TEXTURE_TRIANGLE                                                0x00000095
+
+
+
+#define NV11_TCL_PRIMITIVE_3D                                                  0x00000096
+
+#define  NV11_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_ENABLE                           0x00000d40
+#define  NV11_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP                               0x00000d44
+#define  NV11_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_CLEAR                         0x00001500
+#define  NV11_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_AND                           0x00001501
+#define  NV11_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_AND_REVERSE                   0x00001502
+#define  NV11_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_COPY                          0x00001503
+#define  NV11_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_AND_INVERTED                  0x00001504
+#define  NV11_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_NOOP                          0x00001505
+#define  NV11_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_XOR                           0x00001506
+#define  NV11_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_OR                            0x00001507
+#define  NV11_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_NOR                           0x00001508
+#define  NV11_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_EQUIV                         0x00001509
+#define  NV11_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_INVERT                                0x0000150a
+#define  NV11_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_OR_REVERSE                    0x0000150b
+#define  NV11_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_COPY_INVERTED                 0x0000150c
+#define  NV11_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_OR_INVERTED                   0x0000150d
+#define  NV11_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_NAND                          0x0000150e
+#define  NV11_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_SET                           0x0000150f
+
+
+#define NV20_TCL_PRIMITIVE_3D                                                  0x00000097
+
+#define  NV20_TCL_PRIMITIVE_3D_NOP                                             0x00000100
+#define  NV20_TCL_PRIMITIVE_3D_NOTIFY                                          0x00000104
+#define  NV20_TCL_PRIMITIVE_3D_DMA_NOTIFY                                      0x00000180
+#define  NV20_TCL_PRIMITIVE_3D_DMA_IN_MEMORY0                                  0x00000184
+#define  NV20_TCL_PRIMITIVE_3D_DMA_IN_MEMORY1                                  0x00000188
+#define  NV20_TCL_PRIMITIVE_3D_DMA_IN_MEMORY2                                  0x00000194
+#define  NV20_TCL_PRIMITIVE_3D_DMA_IN_MEMORY3                                  0x00000198
+#define  NV20_TCL_PRIMITIVE_3D_DMA_IN_MEMORY6                                  0x000001a4
+#define  NV20_TCL_PRIMITIVE_3D_DMA_IN_MEMORY7                                  0x000001a8
+#define  NV20_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ                                  0x00000200
+#define  NV20_TCL_PRIMITIVE_3D_VIEWPORT_VERT                                   0x00000204
+#define  NV20_TCL_PRIMITIVE_3D_BUFFER_FORMAT                                   0x00000208
+#define  NV20_TCL_PRIMITIVE_3D_BUFFER_PITCH                                    0x0000020c
+#define  NV20_TCL_PRIMITIVE_3D_COLOR_OFFSET                                    0x00000210
+#define  NV20_TCL_PRIMITIVE_3D_ZETA_OFFSET                                     0x00000214
+#define  NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA(x)                                  (0x00000260+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA__SIZE                               0x00000008
+#define  NV20_TCL_PRIMITIVE_3D_RC_FINAL0                                       0x00000288
+#define  NV20_TCL_PRIMITIVE_3D_RC_FINAL1                                       0x0000028c
+#define  NV20_TCL_PRIMITIVE_3D_LIGHT_CONTROL                                   0x00000294
+#define  NV20_TCL_PRIMITIVE_3D_FOG_MODE                                                0x0000029c
+#define  NV20_TCL_PRIMITIVE_3D_FOG_COORD_DIST                                  0x000002a0
+#define  NV20_TCL_PRIMITIVE_3D_FOG_ENABLE                                      0x000002a4
+#define  NV20_TCL_PRIMITIVE_3D_FOG_COLOR                                       0x000002a8
+#define  NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_MODE                              0x000002b4
+#define  NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(x)                          (0x000002c0+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ__SIZE                       0x00000008
+#define  NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT(x)                           (0x000002e0+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT__SIZE                                0x00000008
+#define  NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_ENABLE                               0x00000300
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_ENABLE                               0x00000304
+#define  NV20_TCL_PRIMITIVE_3D_CULL_FACE_ENABLE                                        0x00000308
+#define  NV20_TCL_PRIMITIVE_3D_DEPTH_TEST_ENABLE                               0x0000030c
+#define  NV20_TCL_PRIMITIVE_3D_DITHER_ENABLE                                   0x00000310
+#define  NV20_TCL_PRIMITIVE_3D_LIGHTING_ENABLE                                 0x00000314
+#define  NV20_TCL_PRIMITIVE_3D_POINT_PARAMETERS_ENABLE                         0x00000318
+#define  NV20_TCL_PRIMITIVE_3D_LINE_SMOOTH_ENABLE                              0x00000320
+#define  NV20_TCL_PRIMITIVE_3D_POLYGON_SMOOTH_ENABLE                           0x00000324
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_ENABLE                                  0x0000032c
+#define  NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_POINT_ENABLE                     0x00000330
+#define  NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_LINE_ENABLE                      0x00000334
+#define  NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FILL_ENABLE                      0x00000338
+#define  NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC                                 0x0000033c
+#define  NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_NEVER                           0x00000200
+#define  NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_LESS                            0x00000201
+#define  NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_EQUAL                           0x00000202
+#define  NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_LEQUAL                          0x00000203
+#define  NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_GREATER                         0x00000204
+#define  NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_GREATER                         0x00000204
+#define  NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_NOTEQUAL                                0x00000205
+#define  NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_GEQUAL                          0x00000206
+#define  NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_ALWAYS                          0x00000207
+#define  NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_REF                                  0x00000340
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC                                  0x00000344
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ZERO                             0x00000000
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ONE                              0x00000001
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_SRC_COLOR                                0x00000300
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ONE_MINUS_SRC_COLOR              0x00000301
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_SRC_ALPHA                                0x00000302
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ONE_MINUS_SRC_ALPHA              0x00000303
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_DST_ALPHA                                0x00000304
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ONE_MINUS_DST_ALPHA              0x00000305
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_DST_COLOR                                0x00000306
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ONE_MINUS_DST_COLOR              0x00000307
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_SRC_ALPHA_SATURATE               0x00000308
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_CONSTANT_COLOR                   0x00008001
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_COLOR         0x00008002
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_CONSTANT_ALPHA                   0x00008003
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_ALPHA         0x00008004
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_DST                                  0x00000348
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ZERO                             0x00000000
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ONE                              0x00000001
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_SRC_COLOR                                0x00000300
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ONE_MINUS_SRC_COLOR              0x00000301
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_SRC_ALPHA                                0x00000302
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ONE_MINUS_SRC_ALPHA              0x00000303
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_DST_ALPHA                                0x00000304
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ONE_MINUS_DST_ALPHA              0x00000305
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_DST_COLOR                                0x00000306
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ONE_MINUS_DST_COLOR              0x00000307
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_SRC_ALPHA_SATURATE               0x00000308
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_CONSTANT_COLOR                   0x00008001
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_COLOR         0x00008002
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_CONSTANT_ALPHA                   0x00008003
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_ALPHA         0x00008004
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_COLOR                                     0x0000034c
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_EQUATION                                  0x00000350
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_EQUATION_FUNC_ADD                         0x00008006
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_EQUATION_MIN                              0x00008007
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_EQUATION_MAX                              0x00008008
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_EQUATION_FUNC_SUBTRACT                    0x0000800a
+#define  NV20_TCL_PRIMITIVE_3D_BLEND_EQUATION_FUNC_REVERSE_SUBTRACT            0x0000800b
+#define  NV20_TCL_PRIMITIVE_3D_DEPTH_FUNC                                      0x00000354
+#define  NV20_TCL_PRIMITIVE_3D_DEPTH_FUNC_NEVER                                        0x00000200
+#define  NV20_TCL_PRIMITIVE_3D_DEPTH_FUNC_LESS                                 0x00000201
+#define  NV20_TCL_PRIMITIVE_3D_DEPTH_FUNC_EQUAL                                        0x00000202
+#define  NV20_TCL_PRIMITIVE_3D_DEPTH_FUNC_LEQUAL                               0x00000203
+#define  NV20_TCL_PRIMITIVE_3D_DEPTH_FUNC_GREATER                              0x00000204
+#define  NV20_TCL_PRIMITIVE_3D_DEPTH_FUNC_GREATER                              0x00000204
+#define  NV20_TCL_PRIMITIVE_3D_DEPTH_FUNC_NOTEQUAL                             0x00000205
+#define  NV20_TCL_PRIMITIVE_3D_DEPTH_FUNC_GEQUAL                               0x00000206
+#define  NV20_TCL_PRIMITIVE_3D_DEPTH_FUNC_ALWAYS                               0x00000207
+#define  NV20_TCL_PRIMITIVE_3D_COLOR_MASK                                      0x00000358
+#define  NV20_TCL_PRIMITIVE_3D_DEPTH_WRITE_ENABLE                              0x0000035c
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_MASK                                    0x00000360
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC                               0x00000364
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC_NEVER                         0x00000200
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC_LESS                          0x00000201
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC_EQUAL                         0x00000202
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC_LEQUAL                                0x00000203
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC_GREATER                       0x00000204
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC_GREATER                       0x00000204
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC_NOTEQUAL                      0x00000205
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC_GEQUAL                                0x00000206
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC_ALWAYS                                0x00000207
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_FUNC_REF                                        0x00000368
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_FUNC_MASK                               0x0000036c
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL                                 0x00000370
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL_ZERO                            0x00000000
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL_INVERT                          0x0000150a
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL_KEEP                            0x00001e00
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL_REPLACE                         0x00001e01
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL_INCR                            0x00001e02
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL_DECR                            0x00001e03
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL_INCR_WRAP                       0x00008507
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL_DECR_WRAP                       0x00008508
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL                                        0x00000374
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL_ZERO                           0x00000000
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL_INVERT                         0x0000150a
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL_KEEP                           0x00001e00
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL_REPLACE                                0x00001e01
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL_INCR                           0x00001e02
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL_DECR                           0x00001e03
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL_INCR_WRAP                      0x00008507
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL_DECR_WRAP                      0x00008508
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS                                        0x00000378
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS_ZERO                           0x00000000
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS_INVERT                         0x0000150a
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS_KEEP                           0x00001e00
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS_REPLACE                                0x00001e01
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS_INCR                           0x00001e02
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS_DECR                           0x00001e03
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS_INCR_WRAP                      0x00008507
+#define  NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS_DECR_WRAP                      0x00008508
+#define  NV20_TCL_PRIMITIVE_3D_SHADE_MODEL                                     0x0000037c
+#define  NV20_TCL_PRIMITIVE_3D_SHADE_MODEL_FLAT                                        0x00001d00
+#define  NV20_TCL_PRIMITIVE_3D_SHADE_MODEL_SMOOTH                              0x00001d01
+#define  NV20_TCL_PRIMITIVE_3D_LINE_WIDTH                                      0x00000380
+#define  NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FACTOR                           0x00000384
+#define  NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_UNITS                            0x00000388
+#define  NV20_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT                              0x0000038c
+#define  NV20_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT_POINT                                0x00001b00
+#define  NV20_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT_LINE                         0x00001b01
+#define  NV20_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT_FILL                         0x00001b02
+#define  NV20_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK                               0x00000390
+#define  NV20_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK_POINT                         0x00001b00
+#define  NV20_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK_LINE                          0x00001b01
+#define  NV20_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK_FILL                          0x00001b02
+#define  NV20_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR                                        0x00000394
+#define  NV20_TCL_PRIMITIVE_3D_DEPTH_RANGE_FAR                                 0x00000398
+#define  NV20_TCL_PRIMITIVE_3D_CULL_FACE                                       0x0000039c
+#define  NV20_TCL_PRIMITIVE_3D_CULL_FACE_FRONT                                 0x00000404
+#define  NV20_TCL_PRIMITIVE_3D_CULL_FACE_BACK                                  0x00000405
+#define  NV20_TCL_PRIMITIVE_3D_CULL_FACE_FRONT_AND_BACK                                0x00000408
+#define  NV20_TCL_PRIMITIVE_3D_FRONT_FACE                                      0x000003a0
+#define  NV20_TCL_PRIMITIVE_3D_FRONT_FACE_CW                                   0x00000900
+#define  NV20_TCL_PRIMITIVE_3D_FRONT_FACE_CCW                                  0x00000901
+#define  NV20_TCL_PRIMITIVE_3D_NORMALIZE_ENABLE                                        0x000003a4
+#define  NV20_TCL_PRIMITIVE_3D_SEPARATE_SPECULAR_ENABLE                                0x000003b8
+#define  NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS                                  0x000003bc
+#define  NV20_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE(x)                            (0x000003c0+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE__SIZE                         0x00000010
+#define  NV20_TCL_PRIMITIVE_3D_TX_MATRIX_ENABLE(x)                             (0x00000420+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_TX_MATRIX_ENABLE__SIZE                          0x00000004
+#define  NV20_TCL_PRIMITIVE_3D_POINT_SIZE                                      0x0000043c
+#define  NV20_TCL_PRIMITIVE_3D_MODELVIEW_MATRIX(x)                             (0x00000480+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_MODELVIEW_MATRIX__SIZE                          0x00000010
+#define  NV20_TCL_PRIMITIVE_3D_PROJECTION_MATRIX(x)                            (0x00000680+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_PROJECTION_MATRIX__SIZE                         0x00000010
+#define  NV20_TCL_PRIMITIVE_3D_TX0_MATRIX(x)                                   (0x000006c0+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_TX0_MATRIX__SIZE                                        0x00000010
+#define  NV20_TCL_PRIMITIVE_3D_TX1_MATRIX(x)                                   (0x00000700+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_TX1_MATRIX__SIZE                                        0x00000010
+#define  NV20_TCL_PRIMITIVE_3D_TX2_MATRIX(x)                                   (0x00000740+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_TX2_MATRIX__SIZE                                        0x00000010
+#define  NV20_TCL_PRIMITIVE_3D_TX3_MATRIX(x)                                   (0x00000780+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_TX3_MATRIX__SIZE                                        0x00000010
+#define  NV20_TCL_PRIMITIVE_3D_FOG_EQUATION_CONSTANT                           0x000009c0
+#define  NV20_TCL_PRIMITIVE_3D_FOG_EQUATION_LINEAR                             0x000009c4
+#define  NV20_TCL_PRIMITIVE_3D_FOG_EQUATION_QUADRATIC                          0x000009c8
+#define  NV20_TCL_PRIMITIVE_3D_VIEWPORT_SCALE0_X                               0x00000a20
+#define  NV20_TCL_PRIMITIVE_3D_VIEWPORT_SCALE0_Y                               0x00000a24
+#define  NV20_TCL_PRIMITIVE_3D_VIEWPORT_SCALE0_Z                               0x00000a28
+#define  NV20_TCL_PRIMITIVE_3D_VIEWPORT_SCALE0_W                               0x00000a2c
+#define  NV20_TCL_PRIMITIVE_3D_POINT_PARAMETER(x)                              (0x00000a30+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_POINT_PARAMETER__SIZE                           0x00000007
+#define  NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0(x)                           (0x00000a60+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0__SIZE                                0x00000008
+#define  NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1(x)                           (0x00000a80+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1__SIZE                                0x00000008
+#define  NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA(x)                                 (0x00000aa0+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA__SIZE                              0x00000008
+#define  NV20_TCL_PRIMITIVE_3D_RC_IN_RGB(x)                                    (0x00000ac0+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_RC_IN_RGB__SIZE                                 0x00000008
+#define  NV20_TCL_PRIMITIVE_3D_VIEWPORT_SCALE1_X                               0x00000af0
+#define  NV20_TCL_PRIMITIVE_3D_VIEWPORT_SCALE1_Y                               0x00000af4
+#define  NV20_TCL_PRIMITIVE_3D_VIEWPORT_SCALE1_Z                               0x00000af8
+#define  NV20_TCL_PRIMITIVE_3D_VIEWPORT_SCALE1_W                               0x00000afc
+#define  NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_INST(x)                               (0x00000b00+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_INST__SIZE                            0x00000004
+#define  NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST(x)                              (0x00000b80+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST__SIZE                           0x00000004
+#define  NV20_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_ENABLE                          0x0000147c
+#define  NV20_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_PATTERN(x)                      (0x00001480+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_PATTERN__SIZE                   0x00000020
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_POS_3F_X                                 0x00001500
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_POS_3F_Y                                 0x00001504
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_POS_3F_Z                                 0x00001508
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4F_X                                 0x00001518
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4F_Y                                 0x0000151c
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4F_Z                                 0x00001520
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_POS_3I_XY                                        0x00001528
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_POS_3I_XY_X_SHIFT                       0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_POS_3I_XY_X_MASK                                0x0000ffff
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_POS_3I_XY_Y_SHIFT                       16
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_POS_3I_XY_Y_MASK                                0xffff0000
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_POS_3I_Z                                 0x0000152c
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_POS_3I_Z_Z_SHIFT                                0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_POS_3I_Z_Z_MASK                         0x0000ffff
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_X                                 0x00001530
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_Y                                 0x00001534
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_Z                                 0x00001538
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY                                        0x00001540
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_X_SHIFT                       0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_X_MASK                                0x0000ffff
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_SHIFT                       16
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_MASK                                0xffff0000
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z                                 0x00001544
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z_Z_SHIFT                                0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z_Z_MASK                         0x0000ffff
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4F_X                                 0x00001550
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4F_Y                                 0x00001554
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4F_Z                                 0x00001558
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4F_W                                 0x0000155c
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_COL_3F_X                                 0x00001560
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_COL_3F_Y                                 0x00001564
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_COL_3F_Z                                 0x00001568
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I                                   0x0000156c
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_R_SHIFT                          0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_R_MASK                           0x000000ff
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_SHIFT                          8
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_MASK                           0x0000ff00
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_SHIFT                          16
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_MASK                           0x00ff0000
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_SHIFT                          24
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_MASK                           0xff000000
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_X                                        0x00001580
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_Y                                        0x00001584
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_Z                                        0x00001588
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_4I                                  0x0000158c
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_4I_R_SHIFT                         0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_4I_R_MASK                          0x000000ff
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_4I_G_SHIFT                         8
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_4I_G_MASK                          0x0000ff00
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_4I_B_SHIFT                         16
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_4I_B_MASK                          0x00ff0000
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_4I_A_SHIFT                         24
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_4I_A_MASK                          0xff000000
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_2F_S                                 0x00001590
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_2F_T                                 0x00001594
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_2I                                   0x00001598
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_S_SHIFT                          0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_S_MASK                           0x0000ffff
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_T_SHIFT                          16
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_T_MASK                           0xffff0000
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_S                                 0x000015a0
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_T                                 0x000015a4
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_R                                 0x000015a8
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_Q                                 0x000015ac
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST                                        0x000015b0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_S_SHIFT                       0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_S_MASK                                0x0000ffff
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_T_SHIFT                       16
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_T_MASK                                0xffff0000
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ                                        0x000015b4
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_R_SHIFT                       0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_R_MASK                                0x0000ffff
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_Q_SHIFT                       16
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_Q_MASK                                0xffff0000
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_2F_S                                 0x000015b8
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_2F_T                                 0x000015bc
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_2I                                   0x000015c0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_S_SHIFT                          0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_S_MASK                           0x0000ffff
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_T_SHIFT                          16
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_T_MASK                           0xffff0000
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_S                                 0x000015c8
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_T                                 0x000015cc
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_R                                 0x000015d0
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_Q                                 0x000015d4
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST                                        0x000015d8
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_S_SHIFT                       0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_S_MASK                                0x0000ffff
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_T_SHIFT                       16
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_T_MASK                                0xffff0000
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ                                        0x000015dc
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_R_SHIFT                       0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_R_MASK                                0x0000ffff
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_Q_SHIFT                       16
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_Q_MASK                                0xffff0000
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_2F_S                                 0x000015e0
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_2F_T                                 0x000015e4
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_2I                                   0x000015e8
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_2I_S_SHIFT                          0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_2I_S_MASK                           0x0000ffff
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_2I_T_SHIFT                          16
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_2I_T_MASK                           0xffff0000
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4F_S                                 0x000015f0
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4F_T                                 0x000015f4
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4F_R                                 0x000015f8
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4F_Q                                 0x000015fc
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST                                        0x00001600
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_S_SHIFT                       0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_S_MASK                                0x0000ffff
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_T_SHIFT                       16
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_T_MASK                                0xffff0000
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ                                        0x00001604
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_R_SHIFT                       0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_R_MASK                                0x0000ffff
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_Q_SHIFT                       16
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_Q_MASK                                0xffff0000
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_2F_S                                 0x00001608
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_2F_T                                 0x0000160c
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_2I                                   0x00001610
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_2I_S_SHIFT                          0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_2I_S_MASK                           0x0000ffff
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_2I_T_SHIFT                          16
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_2I_T_MASK                           0xffff0000
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4F_S                                 0x00001620
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4F_T                                 0x00001624
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4F_R                                 0x00001628
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4F_Q                                 0x0000162c
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST                                        0x00001630
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_S_SHIFT                       0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_S_MASK                                0x0000ffff
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_T_SHIFT                       16
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_T_MASK                                0xffff0000
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ                                        0x00001634
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_R_SHIFT                       0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_R_MASK                                0x0000ffff
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_Q_SHIFT                       16
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_Q_MASK                                0xffff0000
+#define  NV20_TCL_PRIMITIVE_3D_EDGEFLAG_ENABLE                                 0x000016bc
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR_OFFSET(x)                           (0x00001720+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR_OFFSET__SIZE                                0x00000010
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT(x)                          (0x00001760+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT__SIZE                       0x00000010
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TYPE_SHIFT                 0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TYPE_MASK                  0x0000000f
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FIELDS_SHIFT               4
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FIELDS_MASK                        0x000000f0
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_STRIDE_SHIFT               8
+#define   NV20_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_STRIDE_MASK                        0x0000ff00
+#define  NV20_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_ENABLE                           0x000017bc
+#define  NV20_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP                               0x000017c0
+#define  NV20_TCL_PRIMITIVE_3D_LIGHT_MODEL_TWO_SIDE_ENABLE                     0x000017c4
+#define  NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE                             0x000017f8
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END                                        0x000017fc
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_BUFFER_DRAW_ARRAYS                       0x00001810
+#define  NV20_TCL_PRIMITIVE_3D_VERTEX_ARRAY_DATA                               0x00001818
+#define  NV20_TCL_PRIMITIVE_3D_TX_OFFSET(x)                                    (0x00001b00+((x)*64))
+#define  NV20_TCL_PRIMITIVE_3D_TX_OFFSET__SIZE                                 0x00000004
+#define  NV20_TCL_PRIMITIVE_3D_TX_FORMAT(x)                                    (0x00001b04+((x)*64))
+#define  NV20_TCL_PRIMITIVE_3D_TX_FORMAT__SIZE                                 0x00000004
+#define  NV20_TCL_PRIMITIVE_3D_TX_WRAP(x)                                      (0x00001b08+((x)*64))
+#define  NV20_TCL_PRIMITIVE_3D_TX_WRAP__SIZE                                   0x00000004
+#define  NV20_TCL_PRIMITIVE_3D_TX_ENABLE(x)                                    (0x00001b0c+((x)*64))
+#define  NV20_TCL_PRIMITIVE_3D_TX_ENABLE__SIZE                                 0x00000004
+#define  NV20_TCL_PRIMITIVE_3D_TX_FILTER(x)                                    (0x00001b14+((x)*64))
+#define  NV20_TCL_PRIMITIVE_3D_TX_FILTER__SIZE                                 0x00000004
+#define  NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR(x)                              (0x00001b24+((x)*64))
+#define  NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR__SIZE                           0x00000004
+#define  NV20_TCL_PRIMITIVE_3D_SCISSOR_HORIZ                                   0x00001c30
+#define  NV20_TCL_PRIMITIVE_3D_SCISSOR_VERT                                    0x00001c50
+#define  NV20_TCL_PRIMITIVE_3D_CLEAR_VALUE                                     0x00001d90
+#define  NV20_TCL_PRIMITIVE_3D_CLEAR_BUFFERS                                   0x00001d94
+#define  NV20_TCL_PRIMITIVE_3D_RC_COLOR0                                       0x00001e20
+#define  NV20_TCL_PRIMITIVE_3D_RC_COLOR1                                       0x00001e24
+#define  NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB(x)                                   (0x00001e40+((x)*4))
+#define  NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB__SIZE                                        0x00000008
+#define  NV20_TCL_PRIMITIVE_3D_RC_ENABLE                                       0x00001e60
+#define  NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP                                    0x00001e70
+#define  NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_ID                              0x00001ea4
+
+
+#define NV17_TCL_PRIMITIVE_3D                                                  0x00000099
+
+#define  NV17_TCL_PRIMITIVE_3D_DMA_IN_MEMORY4                                  0x000001ac
+#define  NV17_TCL_PRIMITIVE_3D_DMA_IN_MEMORY5                                  0x000001b0
+#define  NV17_TCL_PRIMITIVE_3D_COLOR_MASK_ENABLE                               0x000002bc
+#define  NV17_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_PITCH                          0x00000d5c
+#define  NV17_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_OFFSET                         0x00000d60
+#define  NV17_TCL_PRIMITIVE_3D_LMA_DEPTH_FILL_VALUE                            0x00000d68
+#define  NV17_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_CLEAR                          0x00000d6c
+#define  NV17_TCL_PRIMITIVE_3D_LMA_DEPTH_ENABLE                                        0x00001658
+
+
+#define NV20_SWIZZLED_SURFACE                                                  0x0000009e
+
+
+
+#define NV12_IMAGE_BLIT                                                                0x0000009f
+
+#define  NV12_IMAGE_BLIT_BETA1                                                 0x00000194
+#define  NV12_IMAGE_BLIT_BETA4                                                 0x00000198
+
+
+#define NV30_CONTEXT_SURFACES_2D                                               0x00000362
+
+
+
+#define NV30_STRETCHED_IMAGE_FROM_CPU                                          0x00000366
+
+
+
+#define NV30_TEXTURE_FROM_CPU                                                  0x0000037b
+
+
+
+#define NV30_SCALED_IMAGE_FROM_MEMORY                                          0x00000389
+
+
+
+#define NV30_IMAGE_FROM_CPU                                                    0x0000038a
+
+
+
+#define NV30_TCL_PRIMITIVE_3D                                                  0x00000397
+
+
+
+#define NV30_SWIZZLED_SURFACE                                                  0x0000039e
+
+
+
+#define NV36_TCL_PRIMITIVE_3D                                                  0x00000497
+
+
+
+#define NV25_TCL_PRIMITIVE_3D                                                  0x00000597
+
+#define  NV25_TCL_PRIMITIVE_3D_DMA_IN_MEMORY4                                  0x0000019c
+#define  NV25_TCL_PRIMITIVE_3D_DMA_IN_MEMORY5                                  0x000001a0
+#define  NV25_TCL_PRIMITIVE_3D_DMA_IN_MEMORY8                                  0x000001ac
+#define  NV25_TCL_PRIMITIVE_3D_DMA_IN_MEMORY9                                  0x000001b0
+
+
+#define NV34_TCL_PRIMITIVE_3D                                                  0x00000697
+
+#define  NV34_TCL_PRIMITIVE_3D_NOP                                             0x00000100
+#define  NV34_TCL_PRIMITIVE_3D_NOTIFY                                          0x00000104
+#define  NV34_TCL_PRIMITIVE_3D_DMA_NOTIFY                                      0x00000180
+#define  NV34_TCL_PRIMITIVE_3D_DMA_IN_MEMORY0                                  0x00000184
+#define  NV34_TCL_PRIMITIVE_3D_DMA_IN_MEMORY1                                  0x00000188
+#define  NV34_TCL_PRIMITIVE_3D_DMA_IN_MEMORY2                                  0x0000018c
+#define  NV34_TCL_PRIMITIVE_3D_DMA_IN_MEMORY3                                  0x00000194
+#define  NV34_TCL_PRIMITIVE_3D_DMA_IN_MEMORY4                                  0x00000198
+#define  NV34_TCL_PRIMITIVE_3D_DMA_IN_MEMORY5                                  0x000001a4
+#define  NV34_TCL_PRIMITIVE_3D_DMA_IN_MEMORY6                                  0x000001a8
+#define  NV34_TCL_PRIMITIVE_3D_DMA_IN_MEMORY7                                  0x000001ac
+#define  NV34_TCL_PRIMITIVE_3D_DMA_IN_MEMORY8                                  0x000001b0
+#define  NV34_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ                                  0x00000200
+#define  NV34_TCL_PRIMITIVE_3D_VIEWPORT_VERT                                   0x00000204
+#define  NV34_TCL_PRIMITIVE_3D_FORMAT                                          0x00000208
+#define  NV34_TCL_PRIMITIVE_3D_PITCH                                           0x0000020c
+#define   NV34_TCL_PRIMITIVE_3D_PITCH_COLOR_SHIFT                              0
+#define   NV34_TCL_PRIMITIVE_3D_PITCH_COLOR_MASK                               0x0000ffff
+#define   NV34_TCL_PRIMITIVE_3D_PITCH_ZETA_SHIFT                               16
+#define   NV34_TCL_PRIMITIVE_3D_PITCH_ZETA_MASK                                        0xffff0000
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_OFFSET                                    0x00000210
+#define  NV34_TCL_PRIMITIVE_3D_ZETA_OFFSET                                     0x00000214
+#define  NV34_TCL_PRIMITIVE_3D_COLOR1_OFFSET                                   0x00000218
+#define  NV34_TCL_PRIMITIVE_3D_COLOR1_PITCH                                    0x0000021c
+#define  NV34_TCL_PRIMITIVE_3D_LMA_DEPTH_PITCH                                 0x0000022c
+#define  NV34_TCL_PRIMITIVE_3D_LMA_DEPTH_OFFSET                                        0x00000230
+#define  NV34_TCL_PRIMITIVE_3D_TX_MATRIX_ENABLE(x)                             (0x00000240+((x)*4))
+#define  NV34_TCL_PRIMITIVE_3D_TX_MATRIX_ENABLE__SIZE                          0x00000004
+#define  NV34_TCL_PRIMITIVE_3D_UNK0250(x)                                      (0x00000250+((x)*4))
+#define  NV34_TCL_PRIMITIVE_3D_UNK0250__SIZE                                   0x00000004
+#define  NV34_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(x)                          (0x000002c0+((x)*8))
+#define  NV34_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ__SIZE                       0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT(x)                           (0x000002c4+((x)*8))
+#define  NV34_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT__SIZE                                0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_ALPHA_FUNC_ENABLE                               0x00000304
+#define  NV34_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC                                 0x00000308
+#define  NV34_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_NEVER                           0x00000200
+#define  NV34_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_LESS                            0x00000201
+#define  NV34_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_EQUAL                           0x00000202
+#define  NV34_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_LEQUAL                          0x00000203
+#define  NV34_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_GREATER                         0x00000204
+#define  NV34_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_GREATER                         0x00000204
+#define  NV34_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_NOTEQUAL                                0x00000205
+#define  NV34_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_GEQUAL                          0x00000206
+#define  NV34_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_ALWAYS                          0x00000207
+#define  NV34_TCL_PRIMITIVE_3D_ALPHA_FUNC_REF                                  0x0000030c
+#define  NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_ENABLE                               0x00000310
+#define  NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC                                  0x00000314
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_SHIFT                       0
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_MASK                                0x0000ffff
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_ZERO                                0x00000000
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_ONE                         0x00000001
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_SRC_COLOR                   0x00000300
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_COLOR         0x00000301
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_SRC_ALPHA                   0x00000302
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_ALPHA         0x00000303
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_DST_ALPHA                   0x00000304
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_ALPHA         0x00000305
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_DST_COLOR                   0x00000306
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_COLOR         0x00000307
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_SRC_ALPHA_SATURATE          0x00000308
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_CONSTANT_COLOR              0x00008001
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_COLOR    0x00008002
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_CONSTANT_ALPHA              0x00008003
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_ALPHA    0x00008004
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_SHIFT                     16
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_MASK                      0xffff0000
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_ZERO                      0x00000000
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_ONE                       0x00000001
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_SRC_COLOR                 0x00000300
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_COLOR       0x00000301
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA                 0x00000302
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_ALPHA       0x00000303
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_DST_ALPHA                 0x00000304
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_ALPHA       0x00000305
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_DST_COLOR                 0x00000306
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_COLOR       0x00000307
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA_SATURATE                0x00000308
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_CONSTANT_COLOR            0x00008001
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_COLOR  0x00008002
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_CONSTANT_ALPHA            0x00008003
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_ALPHA  0x00008004
+#define  NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST                                  0x00000318
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_SHIFT                       0
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_MASK                                0x0000ffff
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_ZERO                                0x00000000
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_ONE                         0x00000001
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_SRC_COLOR                   0x00000300
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_COLOR         0x00000301
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_SRC_ALPHA                   0x00000302
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_ALPHA         0x00000303
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_DST_ALPHA                   0x00000304
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_ALPHA         0x00000305
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_DST_COLOR                   0x00000306
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_COLOR         0x00000307
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_SRC_ALPHA_SATURATE          0x00000308
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_CONSTANT_COLOR              0x00008001
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_COLOR    0x00008002
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_CONSTANT_ALPHA              0x00008003
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_ALPHA    0x00008004
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_SHIFT                     16
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_MASK                      0xffff0000
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_ZERO                      0x00000000
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_ONE                       0x00000001
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_SRC_COLOR                 0x00000300
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_COLOR       0x00000301
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_SRC_ALPHA                 0x00000302
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_ALPHA       0x00000303
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_DST_ALPHA                 0x00000304
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_ALPHA       0x00000305
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_DST_COLOR                 0x00000306
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_COLOR       0x00000307
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_SRC_ALPHA_SATURATE                0x00000308
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_CONSTANT_COLOR            0x00008001
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_COLOR  0x00008002
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_CONSTANT_ALPHA            0x00008003
+#define   NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_ALPHA  0x00008004
+#define  NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_COLOR                                        0x0000031c
+#define  NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_EQUATION                             0x00000320
+#define  NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_EQUATION_FUNC_ADD                    0x00008006
+#define  NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_EQUATION_MIN                         0x00008007
+#define  NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_EQUATION_MAX                         0x00008008
+#define  NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_EQUATION_FUNC_SUBTRACT               0x0000800a
+#define  NV34_TCL_PRIMITIVE_3D_BLEND_FUNC_EQUATION_FUNC_REVERSE_SUBTRACT       0x0000800b
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_MASK                                      0x00000324
+#define   NV34_TCL_PRIMITIVE_3D_COLOR_MASK_B_SHIFT                             0
+#define   NV34_TCL_PRIMITIVE_3D_COLOR_MASK_B_MASK                              0x000000ff
+#define   NV34_TCL_PRIMITIVE_3D_COLOR_MASK_G_SHIFT                             8
+#define   NV34_TCL_PRIMITIVE_3D_COLOR_MASK_G_MASK                              0x0000ff00
+#define   NV34_TCL_PRIMITIVE_3D_COLOR_MASK_R_SHIFT                             16
+#define   NV34_TCL_PRIMITIVE_3D_COLOR_MASK_R_MASK                              0x00ff0000
+#define   NV34_TCL_PRIMITIVE_3D_COLOR_MASK_A_SHIFT                             24
+#define   NV34_TCL_PRIMITIVE_3D_COLOR_MASK_A_MASK                              0xff000000
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_ENABLE                             0x00000328
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_MASK                               0x0000032c
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC                          0x00000330
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC_NEVER                    0x00000200
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC_LESS                     0x00000201
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC_EQUAL                    0x00000202
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC_LEQUAL                   0x00000203
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC_GREATER                  0x00000204
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC_GREATER                  0x00000204
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC_NOTEQUAL                 0x00000205
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC_GEQUAL                   0x00000206
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC_ALWAYS                   0x00000207
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_REF                           0x00000334
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_MASK                          0x00000338
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL                            0x0000033c
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL_ZERO                       0x00000000
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL_INVERT                     0x0000150a
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL_KEEP                       0x00001e00
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL_REPLACE                    0x00001e01
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL_INCR                       0x00001e02
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL_DECR                       0x00001e03
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL_INCR_WRAP                  0x00008507
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL_DECR_WRAP                  0x00008508
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL                           0x00000340
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL_ZERO                      0x00000000
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL_INVERT                    0x0000150a
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL_KEEP                      0x00001e00
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL_REPLACE                   0x00001e01
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL_INCR                      0x00001e02
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL_DECR                      0x00001e03
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL_INCR_WRAP                 0x00008507
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL_DECR_WRAP                 0x00008508
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS                           0x00000344
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS_ZERO                      0x00000000
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS_INVERT                    0x0000150a
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS_KEEP                      0x00001e00
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS_REPLACE                   0x00001e01
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS_INCR                      0x00001e02
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS_DECR                      0x00001e03
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS_INCR_WRAP                 0x00008507
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS_DECR_WRAP                 0x00008508
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_ENABLE                            0x00000348
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_MASK                              0x0000034c
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC                         0x00000350
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC_NEVER                   0x00000200
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC_LESS                    0x00000201
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC_EQUAL                   0x00000202
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC_LEQUAL                  0x00000203
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC_GREATER                 0x00000204
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC_GREATER                 0x00000204
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC_NOTEQUAL                        0x00000205
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC_GEQUAL                  0x00000206
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC_ALWAYS                  0x00000207
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_REF                          0x00000354
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_MASK                         0x00000358
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL                           0x0000035c
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL_ZERO                      0x00000000
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL_INVERT                    0x0000150a
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL_KEEP                      0x00001e00
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL_REPLACE                   0x00001e01
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL_INCR                      0x00001e02
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL_DECR                      0x00001e03
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL_INCR_WRAP                 0x00008507
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL_DECR_WRAP                 0x00008508
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL                          0x00000360
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL_ZERO                     0x00000000
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL_INVERT                   0x0000150a
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL_KEEP                     0x00001e00
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL_REPLACE                  0x00001e01
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL_INCR                     0x00001e02
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL_DECR                     0x00001e03
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL_INCR_WRAP                        0x00008507
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL_DECR_WRAP                        0x00008508
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS                          0x00000364
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS_ZERO                     0x00000000
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS_INVERT                   0x0000150a
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS_KEEP                     0x00001e00
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS_REPLACE                  0x00001e01
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS_INCR                     0x00001e02
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS_DECR                     0x00001e03
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS_INCR_WRAP                        0x00008507
+#define  NV34_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS_DECR_WRAP                        0x00008508
+#define  NV34_TCL_PRIMITIVE_3D_SHADE_MODEL                                     0x00000368
+#define  NV34_TCL_PRIMITIVE_3D_SHADE_MODEL_FLAT                                        0x00001d00
+#define  NV34_TCL_PRIMITIVE_3D_SHADE_MODEL_SMOOTH                              0x00001d01
+#define  NV34_TCL_PRIMITIVE_3D_FOG_ENABLE                                      0x0000036c
+#define  NV34_TCL_PRIMITIVE_3D_FOG_COLOR                                       0x00000370
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_ENABLE                           0x00000374
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP                               0x00000378
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_CLEAR                         0x00001500
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_AND                           0x00001501
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_AND_REVERSE                   0x00001502
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_COPY                          0x00001503
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_AND_INVERTED                  0x00001504
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_NOOP                          0x00001505
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_XOR                           0x00001506
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_OR                            0x00001507
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_NOR                           0x00001508
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_EQUIV                         0x00001509
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_INVERT                                0x0000150a
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_OR_REVERSE                    0x0000150b
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_COPY_INVERTED                 0x0000150c
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_OR_INVERTED                   0x0000150d
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_NAND                          0x0000150e
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP_SET                           0x0000150f
+#define  NV34_TCL_PRIMITIVE_3D_NORMALIZE_ENABLE                                        0x0000037c
+#define  NV34_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR                                        0x00000394
+#define  NV34_TCL_PRIMITIVE_3D_DEPTH_RANGE_FAR                                 0x00000398
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_MATERIAL_FRONT_R                          0x000003a0
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_MATERIAL_FRONT_G                          0x000003a4
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_MATERIAL_FRONT_B                          0x000003a8
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_MATERIAL_FRONT_A                          0x000003b4
+#define  NV34_TCL_PRIMITIVE_3D_LINE_WIDTH                                      0x000003b8
+#define  NV34_TCL_PRIMITIVE_3D_LINE_SMOOTH_ENABLE                              0x000003bc
+#define  NV34_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE(x)                            (0x00000400+((x)*4))
+#define  NV34_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE__SIZE                         0x00000020
+#define  NV34_TCL_PRIMITIVE_3D_MODELVIEW_MATRIX(x)                             (0x00000480+((x)*4))
+#define  NV34_TCL_PRIMITIVE_3D_MODELVIEW_MATRIX__SIZE                          0x00000010
+#define  NV34_TCL_PRIMITIVE_3D_PROJECTION_MATRIX(x)                            (0x00000680+((x)*4))
+#define  NV34_TCL_PRIMITIVE_3D_PROJECTION_MATRIX__SIZE                         0x00000010
+#define  NV34_TCL_PRIMITIVE_3D_TX0_MATRIX(x)                                   (0x000006c0+((x)*4))
+#define  NV34_TCL_PRIMITIVE_3D_TX0_MATRIX__SIZE                                        0x00000010
+#define  NV34_TCL_PRIMITIVE_3D_TX1_MATRIX(x)                                   (0x00000700+((x)*4))
+#define  NV34_TCL_PRIMITIVE_3D_TX1_MATRIX__SIZE                                        0x00000010
+#define  NV34_TCL_PRIMITIVE_3D_TX2_MATRIX(x)                                   (0x00000740+((x)*4))
+#define  NV34_TCL_PRIMITIVE_3D_TX2_MATRIX__SIZE                                        0x00000010
+#define  NV34_TCL_PRIMITIVE_3D_TX3_MATRIX(x)                                   (0x00000780+((x)*4))
+#define  NV34_TCL_PRIMITIVE_3D_TX3_MATRIX__SIZE                                        0x00000010
+#define  NV34_TCL_PRIMITIVE_3D_SCISSOR_HORIZ                                   0x000008c0
+#define   NV34_TCL_PRIMITIVE_3D_SCISSOR_HORIZ_X_SHIFT                          0
+#define   NV34_TCL_PRIMITIVE_3D_SCISSOR_HORIZ_X_MASK                           0x0000ffff
+#define   NV34_TCL_PRIMITIVE_3D_SCISSOR_HORIZ_W_SHIFT                          16
+#define   NV34_TCL_PRIMITIVE_3D_SCISSOR_HORIZ_W_MASK                           0xffff0000
+#define  NV34_TCL_PRIMITIVE_3D_SCISSOR_VERT                                    0x000008c4
+#define   NV34_TCL_PRIMITIVE_3D_SCISSOR_VERT_Y_SHIFT                           0
+#define   NV34_TCL_PRIMITIVE_3D_SCISSOR_VERT_Y_MASK                            0x0000ffff
+#define   NV34_TCL_PRIMITIVE_3D_SCISSOR_VERT_H_SHIFT                           16
+#define   NV34_TCL_PRIMITIVE_3D_SCISSOR_VERT_H_MASK                            0xffff0000
+#define  NV34_TCL_PRIMITIVE_3D_FOG_COORD_DIST                                  0x000008c8
+#define  NV34_TCL_PRIMITIVE_3D_FOG_MODE                                                0x000008cc
+#define  NV34_TCL_PRIMITIVE_3D_FOG_EQUATION_CONSTANT                           0x000008d0
+#define  NV34_TCL_PRIMITIVE_3D_FOG_EQUATION_LINEAR                             0x000008d4
+#define  NV34_TCL_PRIMITIVE_3D_FOG_EQUATION_QUADRATIC                          0x000008d8
+#define  NV34_TCL_PRIMITIVE_3D_RC_COLOR0                                       0x000008ec
+#define  NV34_TCL_PRIMITIVE_3D_RC_COLOR1                                       0x000008f0
+#define  NV34_TCL_PRIMITIVE_3D_RC_FINAL0                                       0x000008f4
+#define  NV34_TCL_PRIMITIVE_3D_RC_FINAL1                                       0x000008f8
+#define  NV34_TCL_PRIMITIVE_3D_RC_ENABLE                                       0x000008fc
+#define  NV34_TCL_PRIMITIVE_3D_RC_IN_ALPHA(x)                                  (0x00000900+((x)*32))
+#define  NV34_TCL_PRIMITIVE_3D_RC_IN_ALPHA__SIZE                               0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_RC_IN_RGB(x)                                    (0x00000904+((x)*32))
+#define  NV34_TCL_PRIMITIVE_3D_RC_IN_RGB__SIZE                                 0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0(x)                           (0x00000908+((x)*32))
+#define  NV34_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0__SIZE                                0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1(x)                           (0x0000090c+((x)*32))
+#define  NV34_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1__SIZE                                0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_RC_OUT_ALPHA(x)                                 (0x00000910+((x)*32))
+#define  NV34_TCL_PRIMITIVE_3D_RC_OUT_ALPHA__SIZE                              0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_RC_OUT_RGB(x)                                   (0x00000914+((x)*32))
+#define  NV34_TCL_PRIMITIVE_3D_RC_OUT_RGB__SIZE                                        0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R0x00000a10
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G0x00000a14
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B0x00000a18
+#define  NV34_TCL_PRIMITIVE_3D_VIEWPORT_SCALE0_X                               0x00000a20
+#define  NV34_TCL_PRIMITIVE_3D_VIEWPORT_SCALE0_Y                               0x00000a24
+#define  NV34_TCL_PRIMITIVE_3D_VIEWPORT_SCALE0_Z                               0x00000a28
+#define  NV34_TCL_PRIMITIVE_3D_VIEWPORT_SCALE0_W                               0x00000a2c
+#define  NV34_TCL_PRIMITIVE_3D_VIEWPORT_SCALE1_X                               0x00000a30
+#define  NV34_TCL_PRIMITIVE_3D_VIEWPORT_SCALE1_Y                               0x00000a34
+#define  NV34_TCL_PRIMITIVE_3D_VIEWPORT_SCALE1_Z                               0x00000a38
+#define  NV34_TCL_PRIMITIVE_3D_VIEWPORT_SCALE1_W                               0x00000a3c
+#define  NV34_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FILL_ENABLE                      0x00000a60
+#define  NV34_TCL_PRIMITIVE_3D_POLYGON_OFFSET_LINE_ENABLE                      0x00000a64
+#define  NV34_TCL_PRIMITIVE_3D_POLYGON_OFFSET_POINT_ENABLE                     0x00000a68
+#define  NV34_TCL_PRIMITIVE_3D_DEPTH_FUNC                                      0x00000a6c
+#define  NV34_TCL_PRIMITIVE_3D_DEPTH_FUNC_NEVER                                        0x00000200
+#define  NV34_TCL_PRIMITIVE_3D_DEPTH_FUNC_LESS                                 0x00000201
+#define  NV34_TCL_PRIMITIVE_3D_DEPTH_FUNC_EQUAL                                        0x00000202
+#define  NV34_TCL_PRIMITIVE_3D_DEPTH_FUNC_LEQUAL                               0x00000203
+#define  NV34_TCL_PRIMITIVE_3D_DEPTH_FUNC_GREATER                              0x00000204
+#define  NV34_TCL_PRIMITIVE_3D_DEPTH_FUNC_GREATER                              0x00000204
+#define  NV34_TCL_PRIMITIVE_3D_DEPTH_FUNC_NOTEQUAL                             0x00000205
+#define  NV34_TCL_PRIMITIVE_3D_DEPTH_FUNC_GEQUAL                               0x00000206
+#define  NV34_TCL_PRIMITIVE_3D_DEPTH_FUNC_ALWAYS                               0x00000207
+#define  NV34_TCL_PRIMITIVE_3D_DEPTH_WRITE_ENABLE                              0x00000a70
+#define  NV34_TCL_PRIMITIVE_3D_DEPTH_TEST_ENABLE                               0x00000a74
+#define  NV34_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FACTOR                           0x00000a78
+#define  NV34_TCL_PRIMITIVE_3D_POLYGON_OFFSET_UNITS                            0x00000a7c
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY                                        0x00000a90
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_X_SHIFT                       0
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_X_MASK                                0x0000ffff
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_SHIFT                       16
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_MASK                                0xffff0000
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z                                 0x00000a94
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z_Z_SHIFT                                0
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z_Z_MASK                         0x0000ffff
+#define  NV34_TCL_PRIMITIVE_3D_VP_UPLOAD_INST(x)                               (0x00000b80+((x)*4))
+#define  NV34_TCL_PRIMITIVE_3D_VP_UPLOAD_INST__SIZE                            0x00000004
+#define  NV34_TCL_PRIMITIVE_3D_CLIP_PLANE_A(x)                                 (0x00000e00+((x)*16))
+#define  NV34_TCL_PRIMITIVE_3D_CLIP_PLANE_A__SIZE                              0x00000020
+#define  NV34_TCL_PRIMITIVE_3D_CLIP_PLANE_B(x)                                 (0x00000e04+((x)*16))
+#define  NV34_TCL_PRIMITIVE_3D_CLIP_PLANE_B__SIZE                              0x00000020
+#define  NV34_TCL_PRIMITIVE_3D_CLIP_PLANE_C(x)                                 (0x00000e08+((x)*16))
+#define  NV34_TCL_PRIMITIVE_3D_CLIP_PLANE_C__SIZE                              0x00000020
+#define  NV34_TCL_PRIMITIVE_3D_CLIP_PLANE_D(x)                                 (0x00000e0c+((x)*16))
+#define  NV34_TCL_PRIMITIVE_3D_CLIP_PLANE_D__SIZE                              0x00000020
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(x)           (0x00001000+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R__SIZE                0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G(x)           (0x00001004+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G__SIZE                0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B(x)           (0x00001008+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B__SIZE                0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(x)           (0x0000100c+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R__SIZE                0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G(x)           (0x00001010+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G__SIZE                0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B(x)           (0x00001014+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B__SIZE                0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(x)          (0x00001018+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R__SIZE       0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G(x)          (0x0000101c+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G__SIZE       0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B(x)          (0x00001020+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B__SIZE       0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_X(x)                          (0x00001028+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_X__SIZE                       0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_Y(x)                          (0x0000102c+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_Y__SIZE                       0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_Z(x)                          (0x00001030+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_Z__SIZE                       0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_X(x)                            (0x00001034+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_X__SIZE                         0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_Y(x)                            (0x00001038+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_Y__SIZE                         0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_Z(x)                            (0x0000103c+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_Z__SIZE                         0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A(x)                          (0x00001200+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A__SIZE                       0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_B(x)                          (0x00001204+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_B__SIZE                       0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_C(x)                          (0x00001208+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_C__SIZE                       0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_X(x)                             (0x0000120c+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_X__SIZE                          0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_Y(x)                             (0x00001210+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_Y__SIZE                          0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_Z(x)                             (0x00001214+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_Z__SIZE                          0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_D(x)                          (0x00001218+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_D__SIZE                       0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_POSITION_X(x)                             (0x0000121c+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_POSITION_X__SIZE                          0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_POSITION_Y(x)                             (0x00001220+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_POSITION_Y__SIZE                          0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_POSITION_Z(x)                             (0x00001224+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_POSITION_Z__SIZE                          0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_ATTENUATION_CONSTANT(x)                   (0x00001228+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_ATTENUATION_CONSTANT__SIZE                        0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_ATTENUATION_LINEAR(x)                     (0x0000122c+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_ATTENUATION_LINEAR__SIZE                  0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_ATTENUATION_QUADRATIC(x)                  (0x00001230+((x)*64))
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_ATTENUATION_QUADRATIC__SIZE               0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS(x)                     (0x00001400+((x)*4))
+#define  NV34_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS__SIZE                  0x00000006
+#define  NV34_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_ENABLE                          0x0000147c
+#define  NV34_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_PATTERN(x)                      (0x00001480+((x)*4))
+#define  NV34_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_PATTERN__SIZE                   0x00000020
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_ATTR_3F_X(x)                             (0x00001500+((x)*16))
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_ATTR_3F_X__SIZE                          0x00000010
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_ATTR_3F_Y(x)                             (0x00001504+((x)*16))
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_ATTR_3F_Y__SIZE                          0x00000010
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_ATTR_3F_Z(x)                             (0x00001508+((x)*16))
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_ATTR_3F_Z__SIZE                          0x00000010
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT(x)                          (0x00001740+((x)*4))
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT__SIZE                       0x0000000c
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TYPE_SHIFT                 0
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TYPE_MASK                  0x0000000f
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FIELDS_SHIFT               4
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FIELDS_MASK                        0x000000f0
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_STRIDE_SHIFT               8
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_STRIDE_MASK                        0x0000ff00
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R0x000017a0
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G0x000017a4
+#define  NV34_TCL_PRIMITIVE_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B0x000017a8
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_MATERIAL_BACK_R                           0x000017b0
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_MATERIAL_BACK_G                           0x000017b4
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_MATERIAL_BACK_B                           0x000017b8
+#define  NV34_TCL_PRIMITIVE_3D_COLOR_MATERIAL_BACK_A                           0x000017c0
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END                                        0x00001808
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_STOP                           0x00000000
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_POINTS                         0x00000001
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_LINES                          0x00000002
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_LINE_LOOP                      0x00000003
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_LINE_STRIP                     0x00000004
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_TRIANGLES                      0x00000005
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_TRIANGLE_STRIP                 0x00000006
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_TRIANGLE_FAN                   0x00000007
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_QUADS                          0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_QUAD_STRIP                     0x00000009
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_BEGIN_END_POLYGON                                0x0000000a
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_DATA                                     0x00001818
+#define  NV34_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT                              0x00001828
+#define  NV34_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT_POINT                                0x00001b00
+#define  NV34_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT_LINE                         0x00001b01
+#define  NV34_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT_FILL                         0x00001b02
+#define  NV34_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK                               0x0000182c
+#define  NV34_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK_POINT                         0x00001b00
+#define  NV34_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK_LINE                          0x00001b01
+#define  NV34_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK_FILL                          0x00001b02
+#define  NV34_TCL_PRIMITIVE_3D_CULL_FACE                                       0x00001830
+#define  NV34_TCL_PRIMITIVE_3D_CULL_FACE_FRONT                                 0x00000404
+#define  NV34_TCL_PRIMITIVE_3D_CULL_FACE_BACK                                  0x00000405
+#define  NV34_TCL_PRIMITIVE_3D_CULL_FACE_FRONT_AND_BACK                                0x00000408
+#define  NV34_TCL_PRIMITIVE_3D_FRONT_FACE                                      0x00001834
+#define  NV34_TCL_PRIMITIVE_3D_FRONT_FACE_CW                                   0x00000900
+#define  NV34_TCL_PRIMITIVE_3D_FRONT_FACE_CCW                                  0x00000901
+#define  NV34_TCL_PRIMITIVE_3D_POLYGON_SMOOTH_ENABLE                           0x00001838
+#define  NV34_TCL_PRIMITIVE_3D_CULL_FACE_ENABLE                                        0x0000183c
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_ATTR_2F_X(x)                             (0x00001880+((x)*8))
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_ATTR_2F_X__SIZE                          0x00000010
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_ATTR_2F_Y(x)                             (0x00001884+((x)*8))
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_ATTR_2F_Y__SIZE                          0x00000010
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_TX_2I_ST(x)                              (0x00001920+((x)*4))
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_TX_2I_ST__SIZE                           0x00000004
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_TX_2I_ST_S_SHIFT                                0
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_TX_2I_ST_S_MASK                         0x0000ffff
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_TX_2I_ST_T_SHIFT                                16
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_TX_2I_ST_T_MASK                         0xffff0000
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_COL_4I(x)                                        (0x0000194c+((x)*4))
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_COL_4I__SIZE                             0x00000002
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_COL_4I_R_SHIFT                          0
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_COL_4I_R_MASK                           0x000000ff
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_SHIFT                          8
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_MASK                           0x0000ff00
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_SHIFT                          16
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_MASK                           0x00ff0000
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_SHIFT                          24
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_MASK                           0xff000000
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY                                        0x00001980
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY_X_SHIFT                       0
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY_X_MASK                                0x0000ffff
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY_Y_SHIFT                       16
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY_Y_MASK                                0xffff0000
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW                                        0x00001984
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW_Z_SHIFT                       0
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW_Z_MASK                                0x0000ffff
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW_W_SHIFT                       16
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW_W_MASK                                0xffff0000
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_TX_4I_ST(x)                              (0x000019c0+((x)*8))
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_TX_4I_ST__SIZE                           0x00000004
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_TX_4I_ST_S_SHIFT                                0
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_TX_4I_ST_S_MASK                         0x0000ffff
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_TX_4I_ST_T_SHIFT                                16
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_TX_4I_ST_T_MASK                         0xffff0000
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_TX_4I_RQ(x)                              (0x000019c4+((x)*8))
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_TX_4I_RQ__SIZE                           0x00000004
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_TX_4I_RQ_R_SHIFT                                0
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_TX_4I_RQ_R_MASK                         0x0000ffff
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_TX_4I_RQ_Q_SHIFT                                16
+#define   NV34_TCL_PRIMITIVE_3D_VERTEX_TX_4I_RQ_Q_MASK                         0xffff0000
+#define  NV34_TCL_PRIMITIVE_3D_TX_OFFSET(x)                                    (0x00001a00+((x)*32))
+#define  NV34_TCL_PRIMITIVE_3D_TX_OFFSET__SIZE                                 0x00000004
+#define  NV34_TCL_PRIMITIVE_3D_TX_FORMAT(x)                                    (0x00001a04+((x)*32))
+#define  NV34_TCL_PRIMITIVE_3D_TX_FORMAT__SIZE                                 0x00000004
+#define   NV34_TCL_PRIMITIVE_3D_TX_FORMAT_CUBE_MAP                             (1 <<  2)
+#define   NV34_TCL_PRIMITIVE_3D_TX_FORMAT_COMPONENTS_SHIFT                     4
+#define   NV34_TCL_PRIMITIVE_3D_TX_FORMAT_COMPONENTS_MASK                      0x000000f0
+#define   NV34_TCL_PRIMITIVE_3D_TX_FORMAT_MIPMAP_LEVELS_SHIFT                  16
+#define   NV34_TCL_PRIMITIVE_3D_TX_FORMAT_MIPMAP_LEVELS_MASK                   0x000f0000
+#define   NV34_TCL_PRIMITIVE_3D_TX_FORMAT_BASE_SIZE_U_SHIFT                    20
+#define   NV34_TCL_PRIMITIVE_3D_TX_FORMAT_BASE_SIZE_U_MASK                     0x00f00000
+#define   NV34_TCL_PRIMITIVE_3D_TX_FORMAT_BASE_SIZE_V_SHIFT                    24
+#define   NV34_TCL_PRIMITIVE_3D_TX_FORMAT_BASE_SIZE_V_MASK                     0x0f000000
+#define   NV34_TCL_PRIMITIVE_3D_TX_FORMAT_BASE_SIZE_W_SHIFT                    28
+#define   NV34_TCL_PRIMITIVE_3D_TX_FORMAT_BASE_SIZE_W_MASK                     0xf0000000
+#define  NV34_TCL_PRIMITIVE_3D_TX_WRAP(x)                                      (0x00001a08+((x)*32))
+#define  NV34_TCL_PRIMITIVE_3D_TX_WRAP__SIZE                                   0x00000004
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_S_SHIFT                                        0
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_S_MASK                                 0x000000ff
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_S_REPEAT                               0x00000001
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_S_MIRRORED_REPEAT                      0x00000002
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_S_CLAMP_TO_EDGE                                0x00000003
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_S_CLAMP_TO_BORDER                      0x00000004
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_S_CLAMP                                        0x00000005
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_T_SHIFT                                        8
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_T_MASK                                 0x0000ff00
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_T_REPEAT                               0x00000001
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_T_MIRRORED_REPEAT                      0x00000002
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_T_CLAMP_TO_EDGE                                0x00000003
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_T_CLAMP_TO_BORDER                      0x00000004
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_T_CLAMP                                        0x00000005
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_R_SHIFT                                        16
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_R_MASK                                 0x00ff0000
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_R_REPEAT                               0x00000001
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_R_MIRRORED_REPEAT                      0x00000002
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_R_CLAMP_TO_EDGE                                0x00000003
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_R_CLAMP_TO_BORDER                      0x00000004
+#define   NV34_TCL_PRIMITIVE_3D_TX_WRAP_R_CLAMP                                        0x00000005
+#define  NV34_TCL_PRIMITIVE_3D_TX_ENABLE(x)                                    (0x00001a0c+((x)*32))
+#define  NV34_TCL_PRIMITIVE_3D_TX_ENABLE__SIZE                                 0x00000004
+#define   NV34_TCL_PRIMITIVE_3D_TX_ENABLE_ENABLE                               (1 << 30)
+#define  NV34_TCL_PRIMITIVE_3D_TX_SWIZZLE(x)                                   (0x00001a10+((x)*32))
+#define  NV34_TCL_PRIMITIVE_3D_TX_SWIZZLE__SIZE                                        0x00000004
+#define  NV34_TCL_PRIMITIVE_3D_TX_FILTER(x)                                    (0x00001a14+((x)*32))
+#define  NV34_TCL_PRIMITIVE_3D_TX_FILTER__SIZE                                 0x00000004
+#define   NV34_TCL_PRIMITIVE_3D_TX_FILTER_MINIFY_SHIFT                         16
+#define   NV34_TCL_PRIMITIVE_3D_TX_FILTER_MINIFY_MASK                          0x000f0000
+#define   NV34_TCL_PRIMITIVE_3D_TX_FILTER_MINIFY_NEAREST                       0x00000001
+#define   NV34_TCL_PRIMITIVE_3D_TX_FILTER_MINIFY_LINEAR                                0x00000002
+#define   NV34_TCL_PRIMITIVE_3D_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST                0x00000003
+#define   NV34_TCL_PRIMITIVE_3D_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST         0x00000004
+#define   NV34_TCL_PRIMITIVE_3D_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR         0x00000005
+#define   NV34_TCL_PRIMITIVE_3D_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR          0x00000006
+#define   NV34_TCL_PRIMITIVE_3D_TX_FILTER_MAGNIFY_SHIFT                                24
+#define   NV34_TCL_PRIMITIVE_3D_TX_FILTER_MAGNIFY_MASK                         0x0f000000
+#define   NV34_TCL_PRIMITIVE_3D_TX_FILTER_MAGNIFY_NEAREST                      0x00000001
+#define   NV34_TCL_PRIMITIVE_3D_TX_FILTER_MAGNIFY_LINEAR                       0x00000002
+#define   NV34_TCL_PRIMITIVE_3D_TX_FILTER_MAGNIFY_NEAREST_MIPMAP_NEAREST       0x00000003
+#define   NV34_TCL_PRIMITIVE_3D_TX_FILTER_MAGNIFY_LINEAR_MIPMAP_NEAREST                0x00000004
+#define   NV34_TCL_PRIMITIVE_3D_TX_FILTER_MAGNIFY_NEAREST_MIPMAP_LINEAR                0x00000005
+#define   NV34_TCL_PRIMITIVE_3D_TX_FILTER_MAGNIFY_LINEAR_MIPMAP_LINEAR         0x00000006
+#define  NV34_TCL_PRIMITIVE_3D_TX_NPOT_SIZE(x)                                 (0x00001a18+((x)*32))
+#define  NV34_TCL_PRIMITIVE_3D_TX_NPOT_SIZE__SIZE                              0x00000004
+#define   NV34_TCL_PRIMITIVE_3D_TX_NPOT_SIZE_H_SHIFT                           0
+#define   NV34_TCL_PRIMITIVE_3D_TX_NPOT_SIZE_H_MASK                            0x0000ffff
+#define   NV34_TCL_PRIMITIVE_3D_TX_NPOT_SIZE_W_SHIFT                           16
+#define   NV34_TCL_PRIMITIVE_3D_TX_NPOT_SIZE_W_MASK                            0xffff0000
+#define  NV34_TCL_PRIMITIVE_3D_TX_BORDER_COLOR(x)                              (0x00001a1c+((x)*32))
+#define  NV34_TCL_PRIMITIVE_3D_TX_BORDER_COLOR__SIZE                           0x00000004
+#define   NV34_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_B_SHIFT                                0
+#define   NV34_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_B_MASK                         0x000000ff
+#define   NV34_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_G_SHIFT                                8
+#define   NV34_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_G_MASK                         0x0000ff00
+#define   NV34_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_R_SHIFT                                16
+#define   NV34_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_R_MASK                         0x00ff0000
+#define   NV34_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_A_SHIFT                                24
+#define   NV34_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_A_MASK                         0xff000000
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_ATTR_4F_X(x)                             (0x00001c00+((x)*16))
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_ATTR_4F_X__SIZE                          0x00000010
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_ATTR_4F_Y(x)                             (0x00001c04+((x)*16))
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_ATTR_4F_Y__SIZE                          0x00000010
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_ATTR_4F_Z(x)                             (0x00001c08+((x)*16))
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_ATTR_4F_Z__SIZE                          0x00000010
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_ATTR_4F_W(x)                             (0x00001c0c+((x)*16))
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_ATTR_4F_W__SIZE                          0x00000010
+#define  NV34_TCL_PRIMITIVE_3D_CLEAR_DEPTH_VALUE                               0x00001d8c
+#define  NV34_TCL_PRIMITIVE_3D_LINE_STIPPLE_ENABLE                             0x00001db4
+#define  NV34_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN                            0x00001db8
+#define   NV34_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN_FACTOR_SHIFT              0
+#define   NV34_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN_FACTOR_MASK               0x0000ffff
+#define   NV34_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN_PATTERN_SHIFT             16
+#define   NV34_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN_PATTERN_MASK              0xffff0000
+#define  NV34_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS(x)                      (0x00001e20+((x)*4))
+#define  NV34_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS__SIZE                   0x00000006
+#define  NV34_TCL_PRIMITIVE_3D_VERTEX_FOG_1F                                   0x00001e54
+#define  NV34_TCL_PRIMITIVE_3D_POINT_PARAMETERS(x)                             (0x00001ec0+((x)*4))
+#define  NV34_TCL_PRIMITIVE_3D_POINT_PARAMETERS__SIZE                          0x00000008
+#define  NV34_TCL_PRIMITIVE_3D_POINT_SIZE                                      0x00001ee0
+#define  NV34_TCL_PRIMITIVE_3D_POINT_PARAMETERS_ENABLE                         0x00001ee4
+#define  NV34_TCL_PRIMITIVE_3D_POINT_SPRITE                                    0x00001ee8
+#define  NV34_TCL_PRIMITIVE_3D_UNK1f80(x)                                      (0x00001f80+((x)*4))
+#define  NV34_TCL_PRIMITIVE_3D_UNK1f80__SIZE                                   0x00000010
+
+
+#define NV40_CONTEXT_SURFACES_2D                                               0x00003062
+
+
+
+#define NV40_STRETCHED_IMAGE_FROM_CPU                                          0x00003066
+
+
+
+#define NV40_TEXTURE_FROM_CPU                                                  0x0000307b
+
+
+
+#define NV40_SCALED_IMAGE_FROM_MEMORY                                          0x00003089
+
+
+
+#define NV40_IMAGE_FROM_CPU                                                    0x0000308a
+
+
+
+#define NV40_SWIZZLED_SURFACE                                                  0x0000309e
+
+
+
+#define NV40TCL                                                                        0x00004097
+
+#define  NV40TCL_REF_CNT                                                       0x00000050
+#define  NV40TCL_NOP                                                           0x00000100
+#define  NV40TCL_NOTIFY                                                                0x00000104
+#define  NV40TCL_DMA_NOTIFY                                                    0x00000180
+#define  NV40TCL_DMA_TEXTURE0                                                  0x00000184
+#define  NV40TCL_DMA_TEXTURE1                                                  0x00000188
+#define  NV40TCL_DMA_COLOR1                                                    0x0000018c
+#define  NV40TCL_DMA_COLOR0                                                    0x00000194
+#define  NV40TCL_DMA_ZETA                                                      0x00000198
+#define  NV40TCL_DMA_VTXBUF0                                                   0x0000019c
+#define  NV40TCL_DMA_VTXBUF1                                                   0x000001a0
+#define  NV40TCL_DMA_FENCE                                                     0x000001a4
+#define  NV40TCL_DMA_QUERY                                                     0x000001a8
+#define  NV40TCL_DMA_UNK01AC                                                   0x000001ac
+#define  NV40TCL_DMA_UNK01B0                                                   0x000001b0
+#define  NV40TCL_DMA_COLOR2                                                    0x000001b4
+#define  NV40TCL_DMA_COLOR3                                                    0x000001b8
+#define  NV40TCL_RT_HORIZ                                                      0x00000200
+#define   NV40TCL_RT_HORIZ_W_SHIFT                                             16
+#define   NV40TCL_RT_HORIZ_W_MASK                                              0xffff0000
+#define   NV40TCL_RT_HORIZ_X_SHIFT                                             0
+#define   NV40TCL_RT_HORIZ_X_MASK                                              0x0000ffff
+#define  NV40TCL_RT_VERT                                                       0x00000204
+#define   NV40TCL_RT_VERT_H_SHIFT                                              16
+#define   NV40TCL_RT_VERT_H_MASK                                               0xffff0000
+#define   NV40TCL_RT_VERT_Y_SHIFT                                              0
+#define   NV40TCL_RT_VERT_Y_MASK                                               0x0000ffff
+#define  NV40TCL_RT_FORMAT                                                     0x00000208
+#define   NV40TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT                                  24
+#define   NV40TCL_RT_FORMAT_LOG2_HEIGHT_MASK                                   0xff000000
+#define   NV40TCL_RT_FORMAT_LOG2_WIDTH_SHIFT                                   16
+#define   NV40TCL_RT_FORMAT_LOG2_WIDTH_MASK                                    0x00ff0000
+#define   NV40TCL_RT_FORMAT_TYPE_SHIFT                                         8
+#define   NV40TCL_RT_FORMAT_TYPE_MASK                                          0x00000f00
+#define   NV40TCL_RT_FORMAT_TYPE_LINEAR                                                0x00000001
+#define   NV40TCL_RT_FORMAT_TYPE_SWIZZLED                                      0x00000002
+#define   NV40TCL_RT_FORMAT_DEPTH_SHIFT                                                5
+#define   NV40TCL_RT_FORMAT_DEPTH_MASK                                         0x000000e0
+#define   NV40TCL_RT_FORMAT_DEPTH_Z16                                          0x00000001
+#define   NV40TCL_RT_FORMAT_DEPTH_Z24S8                                                0x00000002
+#define   NV40TCL_RT_FORMAT_COLOR_SHIFT                                                0
+#define   NV40TCL_RT_FORMAT_COLOR_MASK                                         0x0000001f
+#define   NV40TCL_RT_FORMAT_COLOR_R5G6B5                                       0x00000003
+#define   NV40TCL_RT_FORMAT_COLOR_X8R8G8B8                                     0x00000005
+#define   NV40TCL_RT_FORMAT_COLOR_A8R8G8B8                                     0x00000008
+#define   NV40TCL_RT_FORMAT_COLOR_B8                                           0x00000009
+#define  NV40TCL_COLOR0_PITCH                                                  0x0000020c
+#define  NV40TCL_COLOR0_OFFSET                                                 0x00000210
+#define  NV40TCL_ZETA_OFFSET                                                   0x00000214
+#define  NV40TCL_COLOR1_OFFSET                                                 0x00000218
+#define  NV40TCL_COLOR1_PITCH                                                  0x0000021c
+#define  NV40TCL_RT_ENABLE                                                     0x00000220
+#define   NV40TCL_RT_ENABLE_MRT                                                        (1 <<  4)
+#define   NV40TCL_RT_ENABLE_COLOR3                                             (1 <<  3)
+#define   NV40TCL_RT_ENABLE_COLOR2                                             (1 <<  2)
+#define   NV40TCL_RT_ENABLE_COLOR1                                             (1 <<  1)
+#define   NV40TCL_RT_ENABLE_COLOR0                                             (1 <<  0)
+#define  NV40TCL_ZETA_PITCH                                                    0x0000022c
+#define  NV40TCL_COLOR2_PITCH                                                  0x00000280
+#define  NV40TCL_COLOR3_PITCH                                                  0x00000284
+#define  NV40TCL_COLOR2_OFFSET                                                 0x00000288
+#define  NV40TCL_COLOR3_OFFSET                                                 0x0000028c
+#define  NV40TCL_VIEWPORT_CLIP_HORIZ(x)                                                (0x000002c0+((x)*8))
+#define  NV40TCL_VIEWPORT_CLIP_HORIZ__SIZE                                     0x00000008
+#define  NV40TCL_VIEWPORT_CLIP_VERT(x)                                         (0x000002c4+((x)*8))
+#define  NV40TCL_VIEWPORT_CLIP_VERT__SIZE                                      0x00000008
+#define  NV40TCL_DITHER_ENABLE                                                 0x00000300
+#define  NV40TCL_ALPHA_TEST_ENABLE                                             0x00000304
+#define  NV40TCL_ALPHA_TEST_FUNC                                               0x00000308
+#define  NV40TCL_ALPHA_TEST_FUNC_NEVER                                         0x00000200
+#define  NV40TCL_ALPHA_TEST_FUNC_LESS                                          0x00000201
+#define  NV40TCL_ALPHA_TEST_FUNC_EQUAL                                         0x00000202
+#define  NV40TCL_ALPHA_TEST_FUNC_LEQUAL                                                0x00000203
+#define  NV40TCL_ALPHA_TEST_FUNC_GREATER                                       0x00000204
+#define  NV40TCL_ALPHA_TEST_FUNC_GREATER                                       0x00000204
+#define  NV40TCL_ALPHA_TEST_FUNC_NOTEQUAL                                      0x00000205
+#define  NV40TCL_ALPHA_TEST_FUNC_GEQUAL                                                0x00000206
+#define  NV40TCL_ALPHA_TEST_FUNC_ALWAYS                                                0x00000207
+#define  NV40TCL_ALPHA_TEST_REF                                                        0x0000030c
+#define  NV40TCL_BLEND_ENABLE                                                  0x00000310
+#define  NV40TCL_BLEND_FUNC_SRC                                                        0x00000314
+#define   NV40TCL_BLEND_FUNC_SRC_RGB_SHIFT                                     0
+#define   NV40TCL_BLEND_FUNC_SRC_RGB_MASK                                      0x0000ffff
+#define   NV40TCL_BLEND_FUNC_SRC_RGB_ZERO                                      0x00000000
+#define   NV40TCL_BLEND_FUNC_SRC_RGB_ONE                                       0x00000001
+#define   NV40TCL_BLEND_FUNC_SRC_RGB_SRC_COLOR                                 0x00000300
+#define   NV40TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_COLOR                       0x00000301
+#define   NV40TCL_BLEND_FUNC_SRC_RGB_SRC_ALPHA                                 0x00000302
+#define   NV40TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_ALPHA                       0x00000303
+#define   NV40TCL_BLEND_FUNC_SRC_RGB_DST_ALPHA                                 0x00000304
+#define   NV40TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_ALPHA                       0x00000305
+#define   NV40TCL_BLEND_FUNC_SRC_RGB_DST_COLOR                                 0x00000306
+#define   NV40TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_COLOR                       0x00000307
+#define   NV40TCL_BLEND_FUNC_SRC_RGB_SRC_ALPHA_SATURATE                                0x00000308
+#define   NV40TCL_BLEND_FUNC_SRC_RGB_CONSTANT_COLOR                            0x00008001
+#define   NV40TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_COLOR                  0x00008002
+#define   NV40TCL_BLEND_FUNC_SRC_RGB_CONSTANT_ALPHA                            0x00008003
+#define   NV40TCL_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_ALPHA                  0x00008004
+#define   NV40TCL_BLEND_FUNC_SRC_ALPHA_SHIFT                                   16
+#define   NV40TCL_BLEND_FUNC_SRC_ALPHA_MASK                                    0xffff0000
+#define   NV40TCL_BLEND_FUNC_SRC_ALPHA_ZERO                                    0x00000000
+#define   NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE                                     0x00000001
+#define   NV40TCL_BLEND_FUNC_SRC_ALPHA_SRC_COLOR                               0x00000300
+#define   NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_COLOR                     0x00000301
+#define   NV40TCL_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA                               0x00000302
+#define   NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_ALPHA                     0x00000303
+#define   NV40TCL_BLEND_FUNC_SRC_ALPHA_DST_ALPHA                               0x00000304
+#define   NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_ALPHA                     0x00000305
+#define   NV40TCL_BLEND_FUNC_SRC_ALPHA_DST_COLOR                               0x00000306
+#define   NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_COLOR                     0x00000307
+#define   NV40TCL_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA_SATURATE                      0x00000308
+#define   NV40TCL_BLEND_FUNC_SRC_ALPHA_CONSTANT_COLOR                          0x00008001
+#define   NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_COLOR                        0x00008002
+#define   NV40TCL_BLEND_FUNC_SRC_ALPHA_CONSTANT_ALPHA                          0x00008003
+#define   NV40TCL_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_ALPHA                        0x00008004
+#define  NV40TCL_BLEND_FUNC_DST                                                        0x00000318
+#define   NV40TCL_BLEND_FUNC_DST_RGB_SHIFT                                     0
+#define   NV40TCL_BLEND_FUNC_DST_RGB_MASK                                      0x0000ffff
+#define   NV40TCL_BLEND_FUNC_DST_RGB_ZERO                                      0x00000000
+#define   NV40TCL_BLEND_FUNC_DST_RGB_ONE                                       0x00000001
+#define   NV40TCL_BLEND_FUNC_DST_RGB_SRC_COLOR                                 0x00000300
+#define   NV40TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_COLOR                       0x00000301
+#define   NV40TCL_BLEND_FUNC_DST_RGB_SRC_ALPHA                                 0x00000302
+#define   NV40TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_ALPHA                       0x00000303
+#define   NV40TCL_BLEND_FUNC_DST_RGB_DST_ALPHA                                 0x00000304
+#define   NV40TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_ALPHA                       0x00000305
+#define   NV40TCL_BLEND_FUNC_DST_RGB_DST_COLOR                                 0x00000306
+#define   NV40TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_COLOR                       0x00000307
+#define   NV40TCL_BLEND_FUNC_DST_RGB_SRC_ALPHA_SATURATE                                0x00000308
+#define   NV40TCL_BLEND_FUNC_DST_RGB_CONSTANT_COLOR                            0x00008001
+#define   NV40TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_COLOR                  0x00008002
+#define   NV40TCL_BLEND_FUNC_DST_RGB_CONSTANT_ALPHA                            0x00008003
+#define   NV40TCL_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_ALPHA                  0x00008004
+#define   NV40TCL_BLEND_FUNC_DST_ALPHA_SHIFT                                   16
+#define   NV40TCL_BLEND_FUNC_DST_ALPHA_MASK                                    0xffff0000
+#define   NV40TCL_BLEND_FUNC_DST_ALPHA_ZERO                                    0x00000000
+#define   NV40TCL_BLEND_FUNC_DST_ALPHA_ONE                                     0x00000001
+#define   NV40TCL_BLEND_FUNC_DST_ALPHA_SRC_COLOR                               0x00000300
+#define   NV40TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_COLOR                     0x00000301
+#define   NV40TCL_BLEND_FUNC_DST_ALPHA_SRC_ALPHA                               0x00000302
+#define   NV40TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_ALPHA                     0x00000303
+#define   NV40TCL_BLEND_FUNC_DST_ALPHA_DST_ALPHA                               0x00000304
+#define   NV40TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_ALPHA                     0x00000305
+#define   NV40TCL_BLEND_FUNC_DST_ALPHA_DST_COLOR                               0x00000306
+#define   NV40TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_COLOR                     0x00000307
+#define   NV40TCL_BLEND_FUNC_DST_ALPHA_SRC_ALPHA_SATURATE                      0x00000308
+#define   NV40TCL_BLEND_FUNC_DST_ALPHA_CONSTANT_COLOR                          0x00008001
+#define   NV40TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_COLOR                        0x00008002
+#define   NV40TCL_BLEND_FUNC_DST_ALPHA_CONSTANT_ALPHA                          0x00008003
+#define   NV40TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_ALPHA                        0x00008004
+#define  NV40TCL_BLEND_COLOR                                                   0x0000031c
+#define  NV40TCL_BLEND_EQUATION                                                        0x00000320
+#define   NV40TCL_BLEND_EQUATION_RGB_SHIFT                                     0
+#define   NV40TCL_BLEND_EQUATION_RGB_MASK                                      0x0000ffff
+#define   NV40TCL_BLEND_EQUATION_RGB_FUNC_ADD                                  0x00008006
+#define   NV40TCL_BLEND_EQUATION_RGB_MIN                                       0x00008007
+#define   NV40TCL_BLEND_EQUATION_RGB_MAX                                       0x00008008
+#define   NV40TCL_BLEND_EQUATION_RGB_FUNC_SUBTRACT                             0x0000800a
+#define   NV40TCL_BLEND_EQUATION_RGB_FUNC_REVERSE_SUBTRACT                     0x0000800b
+#define   NV40TCL_BLEND_EQUATION_ALPHA_SHIFT                                   16
+#define   NV40TCL_BLEND_EQUATION_ALPHA_MASK                                    0xffff0000
+#define   NV40TCL_BLEND_EQUATION_ALPHA_FUNC_ADD                                        0x00008006
+#define   NV40TCL_BLEND_EQUATION_ALPHA_MIN                                     0x00008007
+#define   NV40TCL_BLEND_EQUATION_ALPHA_MAX                                     0x00008008
+#define   NV40TCL_BLEND_EQUATION_ALPHA_FUNC_SUBTRACT                           0x0000800a
+#define   NV40TCL_BLEND_EQUATION_ALPHA_FUNC_REVERSE_SUBTRACT                   0x0000800b
+#define  NV40TCL_COLOR_MASK                                                    0x00000324
+#define   NV40TCL_COLOR_MASK_BUFFER0_B_SHIFT                                   0
+#define   NV40TCL_COLOR_MASK_BUFFER0_B_MASK                                    0x000000ff
+#define   NV40TCL_COLOR_MASK_BUFFER0_G_SHIFT                                   8
+#define   NV40TCL_COLOR_MASK_BUFFER0_G_MASK                                    0x0000ff00
+#define   NV40TCL_COLOR_MASK_BUFFER0_R_SHIFT                                   16
+#define   NV40TCL_COLOR_MASK_BUFFER0_R_MASK                                    0x00ff0000
+#define   NV40TCL_COLOR_MASK_BUFFER0_A_SHIFT                                   24
+#define   NV40TCL_COLOR_MASK_BUFFER0_A_MASK                                    0xff000000
+#define  NV40TCL_STENCIL_BACK_ENABLE                                           0x00000328
+#define  NV40TCL_STENCIL_BACK_MASK                                             0x0000032c
+#define  NV40TCL_STENCIL_BACK_FUNC_FUNC                                                0x00000330
+#define  NV40TCL_STENCIL_BACK_FUNC_FUNC_NEVER                                  0x00000200
+#define  NV40TCL_STENCIL_BACK_FUNC_FUNC_LESS                                   0x00000201
+#define  NV40TCL_STENCIL_BACK_FUNC_FUNC_EQUAL                                  0x00000202
+#define  NV40TCL_STENCIL_BACK_FUNC_FUNC_LEQUAL                                 0x00000203
+#define  NV40TCL_STENCIL_BACK_FUNC_FUNC_GREATER                                        0x00000204
+#define  NV40TCL_STENCIL_BACK_FUNC_FUNC_GREATER                                        0x00000204
+#define  NV40TCL_STENCIL_BACK_FUNC_FUNC_NOTEQUAL                               0x00000205
+#define  NV40TCL_STENCIL_BACK_FUNC_FUNC_GEQUAL                                 0x00000206
+#define  NV40TCL_STENCIL_BACK_FUNC_FUNC_ALWAYS                                 0x00000207
+#define  NV40TCL_STENCIL_BACK_FUNC_REF                                         0x00000334
+#define  NV40TCL_STENCIL_BACK_FUNC_MASK                                                0x00000338
+#define  NV40TCL_STENCIL_BACK_OP_FAIL                                          0x0000033c
+#define  NV40TCL_STENCIL_BACK_OP_FAIL_ZERO                                     0x00000000
+#define  NV40TCL_STENCIL_BACK_OP_FAIL_INVERT                                   0x0000150a
+#define  NV40TCL_STENCIL_BACK_OP_FAIL_KEEP                                     0x00001e00
+#define  NV40TCL_STENCIL_BACK_OP_FAIL_REPLACE                                  0x00001e01
+#define  NV40TCL_STENCIL_BACK_OP_FAIL_INCR                                     0x00001e02
+#define  NV40TCL_STENCIL_BACK_OP_FAIL_DECR                                     0x00001e03
+#define  NV40TCL_STENCIL_BACK_OP_FAIL_INCR_WRAP                                        0x00008507
+#define  NV40TCL_STENCIL_BACK_OP_FAIL_DECR_WRAP                                        0x00008508
+#define  NV40TCL_STENCIL_BACK_OP_ZFAIL                                         0x00000340
+#define  NV40TCL_STENCIL_BACK_OP_ZFAIL_ZERO                                    0x00000000
+#define  NV40TCL_STENCIL_BACK_OP_ZFAIL_INVERT                                  0x0000150a
+#define  NV40TCL_STENCIL_BACK_OP_ZFAIL_KEEP                                    0x00001e00
+#define  NV40TCL_STENCIL_BACK_OP_ZFAIL_REPLACE                                 0x00001e01
+#define  NV40TCL_STENCIL_BACK_OP_ZFAIL_INCR                                    0x00001e02
+#define  NV40TCL_STENCIL_BACK_OP_ZFAIL_DECR                                    0x00001e03
+#define  NV40TCL_STENCIL_BACK_OP_ZFAIL_INCR_WRAP                               0x00008507
+#define  NV40TCL_STENCIL_BACK_OP_ZFAIL_DECR_WRAP                               0x00008508
+#define  NV40TCL_STENCIL_BACK_OP_ZPASS                                         0x00000344
+#define  NV40TCL_STENCIL_BACK_OP_ZPASS_ZERO                                    0x00000000
+#define  NV40TCL_STENCIL_BACK_OP_ZPASS_INVERT                                  0x0000150a
+#define  NV40TCL_STENCIL_BACK_OP_ZPASS_KEEP                                    0x00001e00
+#define  NV40TCL_STENCIL_BACK_OP_ZPASS_REPLACE                                 0x00001e01
+#define  NV40TCL_STENCIL_BACK_OP_ZPASS_INCR                                    0x00001e02
+#define  NV40TCL_STENCIL_BACK_OP_ZPASS_DECR                                    0x00001e03
+#define  NV40TCL_STENCIL_BACK_OP_ZPASS_INCR_WRAP                               0x00008507
+#define  NV40TCL_STENCIL_BACK_OP_ZPASS_DECR_WRAP                               0x00008508
+#define  NV40TCL_STENCIL_FRONT_ENABLE                                          0x00000348
+#define  NV40TCL_STENCIL_FRONT_MASK                                            0x0000034c
+#define  NV40TCL_STENCIL_FRONT_FUNC_FUNC                                       0x00000350
+#define  NV40TCL_STENCIL_FRONT_FUNC_FUNC_NEVER                                 0x00000200
+#define  NV40TCL_STENCIL_FRONT_FUNC_FUNC_LESS                                  0x00000201
+#define  NV40TCL_STENCIL_FRONT_FUNC_FUNC_EQUAL                                 0x00000202
+#define  NV40TCL_STENCIL_FRONT_FUNC_FUNC_LEQUAL                                        0x00000203
+#define  NV40TCL_STENCIL_FRONT_FUNC_FUNC_GREATER                               0x00000204
+#define  NV40TCL_STENCIL_FRONT_FUNC_FUNC_GREATER                               0x00000204
+#define  NV40TCL_STENCIL_FRONT_FUNC_FUNC_NOTEQUAL                              0x00000205
+#define  NV40TCL_STENCIL_FRONT_FUNC_FUNC_GEQUAL                                        0x00000206
+#define  NV40TCL_STENCIL_FRONT_FUNC_FUNC_ALWAYS                                        0x00000207
+#define  NV40TCL_STENCIL_FRONT_FUNC_REF                                                0x00000354
+#define  NV40TCL_STENCIL_FRONT_FUNC_MASK                                       0x00000358
+#define  NV40TCL_STENCIL_FRONT_OP_FAIL                                         0x0000035c
+#define  NV40TCL_STENCIL_FRONT_OP_FAIL_ZERO                                    0x00000000
+#define  NV40TCL_STENCIL_FRONT_OP_FAIL_INVERT                                  0x0000150a
+#define  NV40TCL_STENCIL_FRONT_OP_FAIL_KEEP                                    0x00001e00
+#define  NV40TCL_STENCIL_FRONT_OP_FAIL_REPLACE                                 0x00001e01
+#define  NV40TCL_STENCIL_FRONT_OP_FAIL_INCR                                    0x00001e02
+#define  NV40TCL_STENCIL_FRONT_OP_FAIL_DECR                                    0x00001e03
+#define  NV40TCL_STENCIL_FRONT_OP_FAIL_INCR_WRAP                               0x00008507
+#define  NV40TCL_STENCIL_FRONT_OP_FAIL_DECR_WRAP                               0x00008508
+#define  NV40TCL_STENCIL_FRONT_OP_ZFAIL                                                0x00000360
+#define  NV40TCL_STENCIL_FRONT_OP_ZFAIL_ZERO                                   0x00000000
+#define  NV40TCL_STENCIL_FRONT_OP_ZFAIL_INVERT                                 0x0000150a
+#define  NV40TCL_STENCIL_FRONT_OP_ZFAIL_KEEP                                   0x00001e00
+#define  NV40TCL_STENCIL_FRONT_OP_ZFAIL_REPLACE                                        0x00001e01
+#define  NV40TCL_STENCIL_FRONT_OP_ZFAIL_INCR                                   0x00001e02
+#define  NV40TCL_STENCIL_FRONT_OP_ZFAIL_DECR                                   0x00001e03
+#define  NV40TCL_STENCIL_FRONT_OP_ZFAIL_INCR_WRAP                              0x00008507
+#define  NV40TCL_STENCIL_FRONT_OP_ZFAIL_DECR_WRAP                              0x00008508
+#define  NV40TCL_STENCIL_FRONT_OP_ZPASS                                                0x00000364
+#define  NV40TCL_STENCIL_FRONT_OP_ZPASS_ZERO                                   0x00000000
+#define  NV40TCL_STENCIL_FRONT_OP_ZPASS_INVERT                                 0x0000150a
+#define  NV40TCL_STENCIL_FRONT_OP_ZPASS_KEEP                                   0x00001e00
+#define  NV40TCL_STENCIL_FRONT_OP_ZPASS_REPLACE                                        0x00001e01
+#define  NV40TCL_STENCIL_FRONT_OP_ZPASS_INCR                                   0x00001e02
+#define  NV40TCL_STENCIL_FRONT_OP_ZPASS_DECR                                   0x00001e03
+#define  NV40TCL_STENCIL_FRONT_OP_ZPASS_INCR_WRAP                              0x00008507
+#define  NV40TCL_STENCIL_FRONT_OP_ZPASS_DECR_WRAP                              0x00008508
+#define  NV40TCL_SHADE_MODEL                                                   0x00000368
+#define  NV40TCL_SHADE_MODEL_FLAT                                              0x00001d00
+#define  NV40TCL_SHADE_MODEL_SMOOTH                                            0x00001d01
+#define  NV40TCL_MRT_COLOR_MASK                                                        0x00000370
+#define   NV40TCL_MRT_COLOR_MASK_BUFFER1_A                                     (1 <<  4)
+#define   NV40TCL_MRT_COLOR_MASK_BUFFER1_R                                     (1 <<  5)
+#define   NV40TCL_MRT_COLOR_MASK_BUFFER1_G                                     (1 <<  6)
+#define   NV40TCL_MRT_COLOR_MASK_BUFFER1_B                                     (1 <<  7)
+#define   NV40TCL_MRT_COLOR_MASK_BUFFER2_A                                     (1 <<  8)
+#define   NV40TCL_MRT_COLOR_MASK_BUFFER2_R                                     (1 <<  9)
+#define   NV40TCL_MRT_COLOR_MASK_BUFFER2_G                                     (1 << 10)
+#define   NV40TCL_MRT_COLOR_MASK_BUFFER2_B                                     (1 << 11)
+#define   NV40TCL_MRT_COLOR_MASK_BUFFER3_A                                     (1 << 12)
+#define   NV40TCL_MRT_COLOR_MASK_BUFFER3_R                                     (1 << 13)
+#define   NV40TCL_MRT_COLOR_MASK_BUFFER3_G                                     (1 << 14)
+#define   NV40TCL_MRT_COLOR_MASK_BUFFER3_B                                     (1 << 15)
+#define  NV40TCL_COLOR_LOGIC_OP_ENABLE                                         0x00000374
+#define  NV40TCL_COLOR_LOGIC_OP                                                        0x00000378
+#define  NV40TCL_COLOR_LOGIC_OP_CLEAR                                          0x00001500
+#define  NV40TCL_COLOR_LOGIC_OP_AND                                            0x00001501
+#define  NV40TCL_COLOR_LOGIC_OP_AND_REVERSE                                    0x00001502
+#define  NV40TCL_COLOR_LOGIC_OP_COPY                                           0x00001503
+#define  NV40TCL_COLOR_LOGIC_OP_AND_INVERTED                                   0x00001504
+#define  NV40TCL_COLOR_LOGIC_OP_NOOP                                           0x00001505
+#define  NV40TCL_COLOR_LOGIC_OP_XOR                                            0x00001506
+#define  NV40TCL_COLOR_LOGIC_OP_OR                                             0x00001507
+#define  NV40TCL_COLOR_LOGIC_OP_NOR                                            0x00001508
+#define  NV40TCL_COLOR_LOGIC_OP_EQUIV                                          0x00001509
+#define  NV40TCL_COLOR_LOGIC_OP_INVERT                                         0x0000150a
+#define  NV40TCL_COLOR_LOGIC_OP_OR_REVERSE                                     0x0000150b
+#define  NV40TCL_COLOR_LOGIC_OP_COPY_INVERTED                                  0x0000150c
+#define  NV40TCL_COLOR_LOGIC_OP_OR_INVERTED                                    0x0000150d
+#define  NV40TCL_COLOR_LOGIC_OP_NAND                                           0x0000150e
+#define  NV40TCL_COLOR_LOGIC_OP_SET                                            0x0000150f
+#define  NV40TCL_DEPTH_RANGE_NEAR                                              0x00000394
+#define  NV40TCL_DEPTH_RANGE_FAR                                               0x00000398
+#define  NV40TCL_LINE_WIDTH                                                    0x000003b8
+#define  NV40TCL_LINE_SMOOTH_ENABLE                                            0x000003bc
+#define  NV40TCL_UNK03C0(x)                                                    (0x000003c0+((x)*4))
+#define  NV40TCL_UNK03C0__SIZE                                                 0x00000010
+#define  NV40TCL_UNK0400(x)                                                    (0x00000400+((x)*4))
+#define  NV40TCL_UNK0400__SIZE                                                 0x00000010
+#define  NV40TCL_UNK0440(x)                                                    (0x00000440+((x)*4))
+#define  NV40TCL_UNK0440__SIZE                                                 0x00000020
+#define  NV40TCL_SCISSOR_HORIZ                                                 0x000008c0
+#define   NV40TCL_SCISSOR_HORIZ_X_SHIFT                                                0
+#define   NV40TCL_SCISSOR_HORIZ_X_MASK                                         0x0000ffff
+#define   NV40TCL_SCISSOR_HORIZ_W_SHIFT                                                16
+#define   NV40TCL_SCISSOR_HORIZ_W_MASK                                         0xffff0000
+#define  NV40TCL_SCISSOR_VERT                                                  0x000008c4
+#define   NV40TCL_SCISSOR_VERT_Y_SHIFT                                         0
+#define   NV40TCL_SCISSOR_VERT_Y_MASK                                          0x0000ffff
+#define   NV40TCL_SCISSOR_VERT_H_SHIFT                                         16
+#define   NV40TCL_SCISSOR_VERT_H_MASK                                          0xffff0000
+#define  NV40TCL_FOG_MODE                                                      0x000008cc
+#define  NV40TCL_FOG_EQUATION_CONSTANT                                         0x000008d0
+#define  NV40TCL_FOG_EQUATION_LINEAR                                           0x000008d4
+#define  NV40TCL_FOG_EQUATION_QUADRATIC                                                0x000008d8
+#define  NV40TCL_FP_ADDRESS                                                    0x000008e4
+#define   NV40TCL_FP_ADDRESS_OFFSET_SHIFT                                      8
+#define   NV40TCL_FP_ADDRESS_OFFSET_MASK                                       0xffffff00
+#define   NV40TCL_FP_ADDRESS_DMA1                                              (1 <<  1)
+#define   NV40TCL_FP_ADDRESS_DMA0                                              (1 <<  0)
+#define  NV40TCL_VIEWPORT_HORIZ                                                        0x00000a00
+#define   NV40TCL_VIEWPORT_HORIZ_W_SHIFT                                       16
+#define   NV40TCL_VIEWPORT_HORIZ_W_MASK                                                0xffff0000
+#define   NV40TCL_VIEWPORT_HORIZ_X_SHIFT                                       0
+#define   NV40TCL_VIEWPORT_HORIZ_X_MASK                                                0x0000ffff
+#define  NV40TCL_VIEWPORT_VERT                                                 0x00000a04
+#define   NV40TCL_VIEWPORT_VERT_H_SHIFT                                                16
+#define   NV40TCL_VIEWPORT_VERT_H_MASK                                         0xffff0000
+#define   NV40TCL_VIEWPORT_VERT_Y_SHIFT                                                0
+#define   NV40TCL_VIEWPORT_VERT_Y_MASK                                         0x0000ffff
+#define  NV40TCL_VIEWPORT_TRANSLATE_X                                          0x00000a20
+#define  NV40TCL_VIEWPORT_TRANSLATE_Y                                          0x00000a24
+#define  NV40TCL_VIEWPORT_TRANSLATE_Z                                          0x00000a28
+#define  NV40TCL_VIEWPORT_TRANSLATE_W                                          0x00000a2c
+#define  NV40TCL_VIEWPORT_SCALE_X                                              0x00000a30
+#define  NV40TCL_VIEWPORT_SCALE_Y                                              0x00000a34
+#define  NV40TCL_VIEWPORT_SCALE_Z                                              0x00000a38
+#define  NV40TCL_VIEWPORT_SCALE_W                                              0x00000a3c
+#define  NV40TCL_POLYGON_OFFSET_FILL_ENABLE                                    0x00000a60
+#define  NV40TCL_POLYGON_OFFSET_LINE_ENABLE                                    0x00000a64
+#define  NV40TCL_POLYGON_OFFSET_POINT_ENABLE                                   0x00000a68
+#define  NV40TCL_DEPTH_FUNC                                                    0x00000a6c
+#define  NV40TCL_DEPTH_FUNC_NEVER                                              0x00000200
+#define  NV40TCL_DEPTH_FUNC_LESS                                               0x00000201
+#define  NV40TCL_DEPTH_FUNC_EQUAL                                              0x00000202
+#define  NV40TCL_DEPTH_FUNC_LEQUAL                                             0x00000203
+#define  NV40TCL_DEPTH_FUNC_GREATER                                            0x00000204
+#define  NV40TCL_DEPTH_FUNC_GREATER                                            0x00000204
+#define  NV40TCL_DEPTH_FUNC_NOTEQUAL                                           0x00000205
+#define  NV40TCL_DEPTH_FUNC_GEQUAL                                             0x00000206
+#define  NV40TCL_DEPTH_FUNC_ALWAYS                                             0x00000207
+#define  NV40TCL_DEPTH_WRITE_ENABLE                                            0x00000a70
+#define  NV40TCL_DEPTH_TEST_ENABLE                                             0x00000a74
+#define  NV40TCL_POLYGON_OFFSET_FACTOR                                         0x00000a78
+#define  NV40TCL_POLYGON_OFFSET_UNITS                                          0x00000a7c
+#define  NV40TCL_UNK0B40(x)                                                    (0x00000b40+((x)*4))
+#define  NV40TCL_UNK0B40__SIZE                                                 0x00000008
+#define  NV40TCL_VP_UPLOAD_INST(x)                                             (0x00000b80+((x)*4))
+#define  NV40TCL_VP_UPLOAD_INST__SIZE                                          0x00000004
+#define  NV40TCL_CLIP_PLANE_ENABLE                                             0x00001478
+#define   NV40TCL_CLIP_PLANE_ENABLE_PLANE0                                     (1 <<  2)
+#define   NV40TCL_CLIP_PLANE_ENABLE_PLANE1                                     (1 <<  6)
+#define   NV40TCL_CLIP_PLANE_ENABLE_PLANE2                                     (1 << 10)
+#define   NV40TCL_CLIP_PLANE_ENABLE_PLANE3                                     (1 << 14)
+#define   NV40TCL_CLIP_PLANE_ENABLE_PLANE4                                     (1 << 18)
+#define   NV40TCL_CLIP_PLANE_ENABLE_PLANE5                                     (1 << 22)
+#define  NV40TCL_POLYGON_STIPPLE_ENABLE                                                0x0000147c
+#define  NV40TCL_POLYGON_STIPPLE_PATTERN(x)                                    (0x00001480+((x)*4))
+#define  NV40TCL_POLYGON_STIPPLE_PATTERN__SIZE                                 0x00000020
+#define  NV40TCL_VTX_ATTR_3F_X(x)                                              (0x00001500+((x)*16))
+#define  NV40TCL_VTX_ATTR_3F_X__SIZE                                           0x00000010
+#define  NV40TCL_VTX_ATTR_3F_Y(x)                                              (0x00001504+((x)*16))
+#define  NV40TCL_VTX_ATTR_3F_Y__SIZE                                           0x00000010
+#define  NV40TCL_VTX_ATTR_3F_Z(x)                                              (0x00001508+((x)*16))
+#define  NV40TCL_VTX_ATTR_3F_Z__SIZE                                           0x00000010
+#define  NV40TCL_VTXBUF_ADDRESS(x)                                             (0x00001680+((x)*4))
+#define  NV40TCL_VTXBUF_ADDRESS__SIZE                                          0x00000010
+#define   NV40TCL_VTXBUF_ADDRESS_DMA1                                          (1 << 31)
+#define   NV40TCL_VTXBUF_ADDRESS_OFFSET_SHIFT                                  0
+#define   NV40TCL_VTXBUF_ADDRESS_OFFSET_MASK                                   0x0fffffff
+#define  NV40TCL_VTX_CACHE_INVALIDATE                                          0x00001714
+#define  NV40TCL_VTXFMT(x)                                                     (0x00001740+((x)*4))
+#define  NV40TCL_VTXFMT__SIZE                                                  0x00000010
+#define   NV40TCL_VTXFMT_TYPE_SHIFT                                            0
+#define   NV40TCL_VTXFMT_TYPE_MASK                                             0x0000000f
+#define   NV40TCL_VTXFMT_TYPE_FLOAT                                            0x00000002
+#define   NV40TCL_VTXFMT_TYPE_UBYTE                                            0x00000004
+#define   NV40TCL_VTXFMT_SIZE_SHIFT                                            4
+#define   NV40TCL_VTXFMT_SIZE_MASK                                             0x000000f0
+#define   NV40TCL_VTXFMT_STRIDE_SHIFT                                          8
+#define   NV40TCL_VTXFMT_STRIDE_MASK                                           0x0000ff00
+#define  NV40TCL_QUERY_RESET                                                   0x000017c8
+#define  NV40TCL_QUERY_UNK17CC                                                 0x000017cc
+#define  NV40TCL_QUERY_GET                                                     0x00001800
+#define   NV40TCL_QUERY_GET_UNK24_SHIFT                                                24
+#define   NV40TCL_QUERY_GET_UNK24_MASK                                         0xff000000
+#define   NV40TCL_QUERY_GET_OFFSET_SHIFT                                       0
+#define   NV40TCL_QUERY_GET_OFFSET_MASK                                                0x00ffffff
+#define  NV40TCL_BEGIN_END                                                     0x00001808
+#define  NV40TCL_BEGIN_END_STOP                                                        0x00000000
+#define  NV40TCL_BEGIN_END_POINTS                                              0x00000001
+#define  NV40TCL_BEGIN_END_LINES                                               0x00000002
+#define  NV40TCL_BEGIN_END_LINE_LOOP                                           0x00000003
+#define  NV40TCL_BEGIN_END_LINE_STRIP                                          0x00000004
+#define  NV40TCL_BEGIN_END_TRIANGLES                                           0x00000005
+#define  NV40TCL_BEGIN_END_TRIANGLE_STRIP                                      0x00000006
+#define  NV40TCL_BEGIN_END_TRIANGLE_FAN                                                0x00000007
+#define  NV40TCL_BEGIN_END_QUADS                                               0x00000008
+#define  NV40TCL_BEGIN_END_QUAD_STRIP                                          0x00000009
+#define  NV40TCL_BEGIN_END_POLYGON                                             0x0000000a
+#define  NV40TCL_VB_ELEMENT_U16                                                        0x0000180c
+#define   NV40TCL_VB_ELEMENT_U16_1_SHIFT                                       16
+#define   NV40TCL_VB_ELEMENT_U16_1_MASK                                                0xffff0000
+#define   NV40TCL_VB_ELEMENT_U16_0_SHIFT                                       0
+#define   NV40TCL_VB_ELEMENT_U16_0_MASK                                                0x0000ffff
+#define  NV40TCL_VB_ELEMENT_U32                                                        0x00001810
+#define  NV40TCL_VB_VERTEX_BATCH                                               0x00001814
+#define   NV40TCL_VB_VERTEX_BATCH_COUNT_SHIFT                                  24
+#define   NV40TCL_VB_VERTEX_BATCH_COUNT_MASK                                   0xff000000
+#define   NV40TCL_VB_VERTEX_BATCH_START_SHIFT                                  0
+#define   NV40TCL_VB_VERTEX_BATCH_START_MASK                                   0x00ffffff
+#define  NV40TCL_VERTEX_DATA                                                   0x00001818
+#define  NV40TCL_POLYGON_MODE_FRONT                                            0x00001828
+#define  NV40TCL_POLYGON_MODE_FRONT_POINT                                      0x00001b00
+#define  NV40TCL_POLYGON_MODE_FRONT_LINE                                       0x00001b01
+#define  NV40TCL_POLYGON_MODE_FRONT_FILL                                       0x00001b02
+#define  NV40TCL_POLYGON_MODE_BACK                                             0x0000182c
+#define  NV40TCL_POLYGON_MODE_BACK_POINT                                       0x00001b00
+#define  NV40TCL_POLYGON_MODE_BACK_LINE                                                0x00001b01
+#define  NV40TCL_POLYGON_MODE_BACK_FILL                                                0x00001b02
+#define  NV40TCL_CULL_FACE                                                     0x00001830
+#define  NV40TCL_CULL_FACE_FRONT                                               0x00000404
+#define  NV40TCL_CULL_FACE_BACK                                                        0x00000405
+#define  NV40TCL_CULL_FACE_FRONT_AND_BACK                                      0x00000408
+#define  NV40TCL_FRONT_FACE                                                    0x00001834
+#define  NV40TCL_FRONT_FACE_CW                                                 0x00000900
+#define  NV40TCL_FRONT_FACE_CCW                                                        0x00000901
+#define  NV40TCL_POLYGON_SMOOTH_ENABLE                                         0x00001838
+#define  NV40TCL_CULL_FACE_ENABLE                                              0x0000183c
+#define  NV40TCL_TEX_SIZE1(x)                                                  (0x00001840+((x)*4))
+#define  NV40TCL_TEX_SIZE1__SIZE                                               0x00000008
+#define   NV40TCL_TEX_SIZE1_DEPTH_SHIFT                                                20
+#define   NV40TCL_TEX_SIZE1_DEPTH_MASK                                         0xfff00000
+#define   NV40TCL_TEX_SIZE1_PITCH_SHIFT                                                0
+#define   NV40TCL_TEX_SIZE1_PITCH_MASK                                         0x0000ffff
+#define  NV40TCL_VTX_ATTR_2F_X(x)                                              (0x00001880+((x)*8))
+#define  NV40TCL_VTX_ATTR_2F_X__SIZE                                           0x00000010
+#define  NV40TCL_VTX_ATTR_2F_Y(x)                                              (0x00001884+((x)*8))
+#define  NV40TCL_VTX_ATTR_2F_Y__SIZE                                           0x00000010
+#define  NV40TCL_VTX_ATTR_2I(x)                                                        (0x00001900+((x)*4))
+#define  NV40TCL_VTX_ATTR_2I__SIZE                                             0x00000010
+#define   NV40TCL_VTX_ATTR_2I_Y_SHIFT                                          16
+#define   NV40TCL_VTX_ATTR_2I_Y_MASK                                           0xffff0000
+#define   NV40TCL_VTX_ATTR_2I_X_SHIFT                                          0
+#define   NV40TCL_VTX_ATTR_2I_X_MASK                                           0x0000ffff
+#define  NV40TCL_VTX_ATTR_4I_0(x)                                              (0x00001900+((x)*8))
+#define  NV40TCL_VTX_ATTR_4I_0__SIZE                                           0x00000010
+#define   NV40TCL_VTX_ATTR_4I_0_Y_SHIFT                                                16
+#define   NV40TCL_VTX_ATTR_4I_0_Y_MASK                                         0xffff0000
+#define   NV40TCL_VTX_ATTR_4I_0_X_SHIFT                                                0
+#define   NV40TCL_VTX_ATTR_4I_0_X_MASK                                         0x0000ffff
+#define  NV40TCL_VTX_ATTR_4I_1(x)                                              (0x00001904+((x)*8))
+#define  NV40TCL_VTX_ATTR_4I_1__SIZE                                           0x00000010
+#define   NV40TCL_VTX_ATTR_4I_1_W_SHIFT                                                16
+#define   NV40TCL_VTX_ATTR_4I_1_W_MASK                                         0xffff0000
+#define   NV40TCL_VTX_ATTR_4I_1_Z_SHIFT                                                0
+#define   NV40TCL_VTX_ATTR_4I_1_Z_MASK                                         0x0000ffff
+#define  NV40TCL_TEX_OFFSET(x)                                                 (0x00001a00+((x)*32))
+#define  NV40TCL_TEX_OFFSET__SIZE                                              0x00000010
+#define  NV40TCL_TEX_FORMAT(x)                                                 (0x00001a04+((x)*32))
+#define  NV40TCL_TEX_FORMAT__SIZE                                              0x00000010
+#define   NV40TCL_TEX_FORMAT_MIPMAP_COUNT_SHIFT                                        16
+#define   NV40TCL_TEX_FORMAT_MIPMAP_COUNT_MASK                                 0x000f0000
+#define   NV40TCL_TEX_FORMAT_RECT                                              (1 << 14)
+#define   NV40TCL_TEX_FORMAT_LINEAR                                            (1 << 13)
+#define   NV40TCL_TEX_FORMAT_FORMAT_SHIFT                                      8
+#define   NV40TCL_TEX_FORMAT_FORMAT_MASK                                       0x00001f00
+#define   NV40TCL_TEX_FORMAT_FORMAT_L8                                         0x00000001
+#define   NV40TCL_TEX_FORMAT_FORMAT_A1R5G5B5                                   0x00000002
+#define   NV40TCL_TEX_FORMAT_FORMAT_A4R4G4B4                                   0x00000003
+#define   NV40TCL_TEX_FORMAT_FORMAT_R5G6B5                                     0x00000004
+#define   NV40TCL_TEX_FORMAT_FORMAT_A8R8G8B8                                   0x00000005
+#define   NV40TCL_TEX_FORMAT_FORMAT_DXT1                                       0x00000006
+#define   NV40TCL_TEX_FORMAT_FORMAT_DXT3                                       0x00000007
+#define   NV40TCL_TEX_FORMAT_FORMAT_DXT5                                       0x00000008
+#define   NV40TCL_TEX_FORMAT_FORMAT_A8L8                                       0x00000018
+#define   NV40TCL_TEX_FORMAT_DIMS_SHIFT                                                4
+#define   NV40TCL_TEX_FORMAT_DIMS_MASK                                         0x000000f0
+#define   NV40TCL_TEX_FORMAT_NO_BORDER                                         (1 <<  3)
+#define   NV40TCL_TEX_FORMAT_CUBIC                                             (1 <<  2)
+#define   NV40TCL_TEX_FORMAT_DMA1                                              (1 <<  1)
+#define   NV40TCL_TEX_FORMAT_DMA0                                              (1 <<  0)
+#define  NV40TCL_TEX_WRAP(x)                                                   (0x00001a08+((x)*32))
+#define  NV40TCL_TEX_WRAP__SIZE                                                        0x00000010
+#define   NV40TCL_TEX_WRAP_S_SHIFT                                             0
+#define   NV40TCL_TEX_WRAP_S_MASK                                              0x000000ff
+#define   NV40TCL_TEX_WRAP_S_REPEAT                                            0x00000001
+#define   NV40TCL_TEX_WRAP_S_MIRRORED_REPEAT                                   0x00000002
+#define   NV40TCL_TEX_WRAP_S_CLAMP_TO_EDGE                                     0x00000003
+#define   NV40TCL_TEX_WRAP_S_CLAMP_TO_BORDER                                   0x00000004
+#define   NV40TCL_TEX_WRAP_S_CLAMP                                             0x00000005
+#define   NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE                              0x00000006
+#define   NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER                            0x00000007
+#define   NV40TCL_TEX_WRAP_S_MIRROR_CLAMP                                      0x00000008
+#define   NV40TCL_TEX_WRAP_T_SHIFT                                             8
+#define   NV40TCL_TEX_WRAP_T_MASK                                              0x0000ff00
+#define   NV40TCL_TEX_WRAP_T_REPEAT                                            0x00000001
+#define   NV40TCL_TEX_WRAP_T_MIRRORED_REPEAT                                   0x00000002
+#define   NV40TCL_TEX_WRAP_T_CLAMP_TO_EDGE                                     0x00000003
+#define   NV40TCL_TEX_WRAP_T_CLAMP_TO_BORDER                                   0x00000004
+#define   NV40TCL_TEX_WRAP_T_CLAMP                                             0x00000005
+#define   NV40TCL_TEX_WRAP_T_MIRROR_CLAMP_TO_EDGE                              0x00000006
+#define   NV40TCL_TEX_WRAP_T_MIRROR_CLAMP_TO_BORDER                            0x00000007
+#define   NV40TCL_TEX_WRAP_T_MIRROR_CLAMP                                      0x00000008
+#define   NV40TCL_TEX_WRAP_R_SHIFT                                             16
+#define   NV40TCL_TEX_WRAP_R_MASK                                              0x00ff0000
+#define   NV40TCL_TEX_WRAP_R_REPEAT                                            0x00000001
+#define   NV40TCL_TEX_WRAP_R_MIRRORED_REPEAT                                   0x00000002
+#define   NV40TCL_TEX_WRAP_R_CLAMP_TO_EDGE                                     0x00000003
+#define   NV40TCL_TEX_WRAP_R_CLAMP_TO_BORDER                                   0x00000004
+#define   NV40TCL_TEX_WRAP_R_CLAMP                                             0x00000005
+#define   NV40TCL_TEX_WRAP_R_MIRROR_CLAMP_TO_EDGE                              0x00000006
+#define   NV40TCL_TEX_WRAP_R_MIRROR_CLAMP_TO_BORDER                            0x00000007
+#define   NV40TCL_TEX_WRAP_R_MIRROR_CLAMP                                      0x00000008
+#define  NV40TCL_TEX_ENABLE(x)                                                 (0x00001a0c+((x)*32))
+#define  NV40TCL_TEX_ENABLE__SIZE                                              0x00000010
+#define   NV40TCL_TEX_ENABLE_ENABLE                                            (1 << 31)
+#define  NV40TCL_TEX_SWIZZLE(x)                                                        (0x00001a10+((x)*32))
+#define  NV40TCL_TEX_SWIZZLE__SIZE                                             0x00000010
+#define   NV40TCL_TEX_SWIZZLE_S0_X_SHIFT                                       14
+#define   NV40TCL_TEX_SWIZZLE_S0_X_MASK                                                0x0000c000
+#define   NV40TCL_TEX_SWIZZLE_S0_X_ZERO                                                0x00000000
+#define   NV40TCL_TEX_SWIZZLE_S0_X_ONE                                         0x00000001
+#define   NV40TCL_TEX_SWIZZLE_S0_X_S1                                          0x00000002
+#define   NV40TCL_TEX_SWIZZLE_S0_Y_SHIFT                                       12
+#define   NV40TCL_TEX_SWIZZLE_S0_Y_MASK                                                0x00003000
+#define   NV40TCL_TEX_SWIZZLE_S0_Y_ZERO                                                0x00000000
+#define   NV40TCL_TEX_SWIZZLE_S0_Y_ONE                                         0x00000001
+#define   NV40TCL_TEX_SWIZZLE_S0_Y_S1                                          0x00000002
+#define   NV40TCL_TEX_SWIZZLE_S0_Z_SHIFT                                       10
+#define   NV40TCL_TEX_SWIZZLE_S0_Z_MASK                                                0x00000c00
+#define   NV40TCL_TEX_SWIZZLE_S0_Z_ZERO                                                0x00000000
+#define   NV40TCL_TEX_SWIZZLE_S0_Z_ONE                                         0x00000001
+#define   NV40TCL_TEX_SWIZZLE_S0_Z_S1                                          0x00000002
+#define   NV40TCL_TEX_SWIZZLE_S0_W_SHIFT                                       8
+#define   NV40TCL_TEX_SWIZZLE_S0_W_MASK                                                0x00000300
+#define   NV40TCL_TEX_SWIZZLE_S0_W_ZERO                                                0x00000000
+#define   NV40TCL_TEX_SWIZZLE_S0_W_ONE                                         0x00000001
+#define   NV40TCL_TEX_SWIZZLE_S0_W_S1                                          0x00000002
+#define   NV40TCL_TEX_SWIZZLE_S1_X_SHIFT                                       6
+#define   NV40TCL_TEX_SWIZZLE_S1_X_MASK                                                0x000000c0
+#define   NV40TCL_TEX_SWIZZLE_S1_X_W                                           0x00000000
+#define   NV40TCL_TEX_SWIZZLE_S1_X_Z                                           0x00000001
+#define   NV40TCL_TEX_SWIZZLE_S1_X_Y                                           0x00000002
+#define   NV40TCL_TEX_SWIZZLE_S1_X_X                                           0x00000003
+#define   NV40TCL_TEX_SWIZZLE_S1_Y_SHIFT                                       4
+#define   NV40TCL_TEX_SWIZZLE_S1_Y_MASK                                                0x00000030
+#define   NV40TCL_TEX_SWIZZLE_S1_Y_W                                           0x00000000
+#define   NV40TCL_TEX_SWIZZLE_S1_Y_Z                                           0x00000001
+#define   NV40TCL_TEX_SWIZZLE_S1_Y_Y                                           0x00000002
+#define   NV40TCL_TEX_SWIZZLE_S1_Y_X                                           0x00000003
+#define   NV40TCL_TEX_SWIZZLE_S1_Z_SHIFT                                       2
+#define   NV40TCL_TEX_SWIZZLE_S1_Z_MASK                                                0x0000000c
+#define   NV40TCL_TEX_SWIZZLE_S1_Z_W                                           0x00000000
+#define   NV40TCL_TEX_SWIZZLE_S1_Z_Z                                           0x00000001
+#define   NV40TCL_TEX_SWIZZLE_S1_Z_Y                                           0x00000002
+#define   NV40TCL_TEX_SWIZZLE_S1_Z_X                                           0x00000003
+#define   NV40TCL_TEX_SWIZZLE_S1_W_SHIFT                                       0
+#define   NV40TCL_TEX_SWIZZLE_S1_W_MASK                                                0x00000003
+#define   NV40TCL_TEX_SWIZZLE_S1_W_W                                           0x00000000
+#define   NV40TCL_TEX_SWIZZLE_S1_W_Z                                           0x00000001
+#define   NV40TCL_TEX_SWIZZLE_S1_W_Y                                           0x00000002
+#define   NV40TCL_TEX_SWIZZLE_S1_W_X                                           0x00000003
+#define  NV40TCL_TEX_FILTER(x)                                                 (0x00001a14+((x)*32))
+#define  NV40TCL_TEX_FILTER__SIZE                                              0x00000010
+#define   NV40TCL_TEX_FILTER_MIN_SHIFT                                         16
+#define   NV40TCL_TEX_FILTER_MIN_MASK                                          0x000f0000
+#define   NV40TCL_TEX_FILTER_MIN_NEAREST                                       0x00000001
+#define   NV40TCL_TEX_FILTER_MIN_LINEAR                                                0x00000002
+#define   NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_NEAREST                                0x00000003
+#define   NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_NEAREST                         0x00000004
+#define   NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_LINEAR                         0x00000005
+#define   NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_LINEAR                          0x00000006
+#define   NV40TCL_TEX_FILTER_MAG_SHIFT                                         24
+#define   NV40TCL_TEX_FILTER_MAG_MASK                                          0x0f000000
+#define   NV40TCL_TEX_FILTER_MAG_NEAREST                                       0x00000001
+#define   NV40TCL_TEX_FILTER_MAG_LINEAR                                                0x00000002
+#define   NV40TCL_TEX_FILTER_MAG_NEAREST_MIPMAP_NEAREST                                0x00000003
+#define   NV40TCL_TEX_FILTER_MAG_LINEAR_MIPMAP_NEAREST                         0x00000004
+#define   NV40TCL_TEX_FILTER_MAG_NEAREST_MIPMAP_LINEAR                         0x00000005
+#define   NV40TCL_TEX_FILTER_MAG_LINEAR_MIPMAP_LINEAR                          0x00000006
+#define  NV40TCL_TEX_SIZE0(x)                                                  (0x00001a18+((x)*32))
+#define  NV40TCL_TEX_SIZE0__SIZE                                               0x00000010
+#define   NV40TCL_TEX_SIZE0_H_SHIFT                                            0
+#define   NV40TCL_TEX_SIZE0_H_MASK                                             0x0000ffff
+#define   NV40TCL_TEX_SIZE0_W_SHIFT                                            16
+#define   NV40TCL_TEX_SIZE0_W_MASK                                             0xffff0000
+#define  NV40TCL_TEX_BORDER_COLOR(x)                                           (0x00001a1c+((x)*32))
+#define  NV40TCL_TEX_BORDER_COLOR__SIZE                                                0x00000010
+#define   NV40TCL_TEX_BORDER_COLOR_B_SHIFT                                     0
+#define   NV40TCL_TEX_BORDER_COLOR_B_MASK                                      0x000000ff
+#define   NV40TCL_TEX_BORDER_COLOR_G_SHIFT                                     8
+#define   NV40TCL_TEX_BORDER_COLOR_G_MASK                                      0x0000ff00
+#define   NV40TCL_TEX_BORDER_COLOR_R_SHIFT                                     16
+#define   NV40TCL_TEX_BORDER_COLOR_R_MASK                                      0x00ff0000
+#define   NV40TCL_TEX_BORDER_COLOR_A_SHIFT                                     24
+#define   NV40TCL_TEX_BORDER_COLOR_A_MASK                                      0xff000000
+#define  NV40TCL_VTX_ATTR_4F_X(x)                                              (0x00001c00+((x)*16))
+#define  NV40TCL_VTX_ATTR_4F_X__SIZE                                           0x00000010
+#define  NV40TCL_VTX_ATTR_4F_Y(x)                                              (0x00001c04+((x)*16))
+#define  NV40TCL_VTX_ATTR_4F_Y__SIZE                                           0x00000010
+#define  NV40TCL_VTX_ATTR_4F_Z(x)                                              (0x00001c08+((x)*16))
+#define  NV40TCL_VTX_ATTR_4F_Z__SIZE                                           0x00000010
+#define  NV40TCL_VTX_ATTR_4F_W(x)                                              (0x00001c0c+((x)*16))
+#define  NV40TCL_VTX_ATTR_4F_W__SIZE                                           0x00000010
+#define  NV40TCL_FP_CONTROL                                                    0x00001d60
+#define   NV40TCL_FP_CONTROL_TEMP_COUNT_SHIFT                                  24
+#define   NV40TCL_FP_CONTROL_TEMP_COUNT_MASK                                   0xff000000
+#define   NV40TCL_FP_CONTROL_KIL                                               (1 <<  7)
+#define  NV40TCL_CLEAR_VALUE_DEPTH                                             0x00001d8c
+#define  NV40TCL_CLEAR_VALUE_COLOR                                             0x00001d90
+#define  NV40TCL_CLEAR_BUFFERS                                                 0x00001d94
+#define   NV40TCL_CLEAR_BUFFERS_COLOR_A                                                (1 <<  7)
+#define   NV40TCL_CLEAR_BUFFERS_COLOR_B                                                (1 <<  6)
+#define   NV40TCL_CLEAR_BUFFERS_COLOR_G                                                (1 <<  5)
+#define   NV40TCL_CLEAR_BUFFERS_COLOR_R                                                (1 <<  4)
+#define   NV40TCL_CLEAR_BUFFERS_STENCIL                                                (1 <<  1)
+#define   NV40TCL_CLEAR_BUFFERS_DEPTH                                          (1 <<  0)
+#define  NV40TCL_LINE_STIPPLE_ENABLE                                           0x00001db4
+#define  NV40TCL_LINE_STIPPLE_PATTERN                                          0x00001db8
+#define   NV40TCL_LINE_STIPPLE_PATTERN_FACTOR_SHIFT                            0
+#define   NV40TCL_LINE_STIPPLE_PATTERN_FACTOR_MASK                             0x0000ffff
+#define   NV40TCL_LINE_STIPPLE_PATTERN_PATTERN_SHIFT                           16
+#define   NV40TCL_LINE_STIPPLE_PATTERN_PATTERN_MASK                            0xffff0000
+#define  NV40TCL_VP_UPLOAD_FROM_ID                                             0x00001e9c
+#define  NV40TCL_VP_START_FROM_ID                                              0x00001ea0
+#define  NV40TCL_POINT_SIZE                                                    0x00001ee0
+#define  NV40TCL_POINT_SPRITE                                                  0x00001ee8
+#define  NV40TCL_VP_UPLOAD_CONST_ID                                            0x00001efc
+#define  NV40TCL_VP_UPLOAD_CONST_X(x)                                          (0x00001f00+((x)*16))
+#define  NV40TCL_VP_UPLOAD_CONST_X__SIZE                                       0x00000004
+#define  NV40TCL_VP_UPLOAD_CONST_Y(x)                                          (0x00001f04+((x)*16))
+#define  NV40TCL_VP_UPLOAD_CONST_Y__SIZE                                       0x00000004
+#define  NV40TCL_VP_UPLOAD_CONST_Z(x)                                          (0x00001f08+((x)*16))
+#define  NV40TCL_VP_UPLOAD_CONST_Z__SIZE                                       0x00000004
+#define  NV40TCL_VP_UPLOAD_CONST_W(x)                                          (0x00001f0c+((x)*16))
+#define  NV40TCL_VP_UPLOAD_CONST_W__SIZE                                       0x00000004
+#define  NV40TCL_TEX_CACHE_CTL                                                 0x00001fd8
+#define  NV40TCL_VP_ATTRIB_EN                                                  0x00001ff0
+#define  NV40TCL_VP_RESULT_EN                                                  0x00001ff4
+
+
+#define NV44_TCL_PRIMITIVE_3D                                                  0x00004497
+
+
+
+#define NV50_PRIMITIVE_2D                                                      0x0000502d
+
+#define  NV50_PRIMITIVE_2D_DMA_NOTIFY                                          0x00000180
+#define  NV50_PRIMITIVE_2D_DMA_IN_MEMORY0                                      0x00000184
+#define  NV50_PRIMITIVE_2D_DMA_IN_MEMORY1                                      0x00000188
+#define  NV50_PRIMITIVE_2D_DMA_IN_MEMORY2                                      0x0000018c
+
+
+#define NV50_MEMORY_TO_MEMORY_FORMAT                                           0x00005039
+
+
+
+#define NV50_TCL_PRIMITIVE_3D                                                  0x00005097
+
+#define  NV50_TCL_PRIMITIVE_3D_NOP                                             0x00000100
+#define  NV50_TCL_PRIMITIVE_3D_NOTIFY                                          0x00000104
+#define  NV50_TCL_PRIMITIVE_3D_DMA_NOTIFY                                      0x00000180
+#define  NV50_TCL_PRIMITIVE_3D_DMA_IN_MEMORY0(x)                               (0x00000184+((x)*4))
+#define  NV50_TCL_PRIMITIVE_3D_DMA_IN_MEMORY0__SIZE                            0x0000000b
+#define  NV50_TCL_PRIMITIVE_3D_DMA_IN_MEMORY1(x)                               (0x000001c0+((x)*4))
+#define  NV50_TCL_PRIMITIVE_3D_DMA_IN_MEMORY1__SIZE                            0x00000008
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_FOG_1F                                   0x00000314
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_POS_2F(x)                                        (0x00000318+((x)*4))
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_POS_2F__SIZE                             0x00000002
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_2F(x)                                        (0x000003c0+((x)*4))
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_2F__SIZE                             0x00000002
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_2F(x)                                        (0x000003c8+((x)*4))
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_2F__SIZE                             0x00000002
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_2F(x)                                        (0x000003d0+((x)*4))
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_2F__SIZE                             0x00000002
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_2F(x)                                        (0x000003d8+((x)*4))
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_2F__SIZE                             0x00000002
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_POS_3F(x)                                        (0x00000400+((x)*4))
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_POS_3F__SIZE                             0x00000003
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3F(x)                                        (0x00000420+((x)*4))
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3F__SIZE                             0x00000003
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_COL_3F(x)                                        (0x00000430+((x)*4))
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_COL_3F__SIZE                             0x00000003
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3F(x)                               (0x00000440+((x)*4))
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3F__SIZE                            0x00000003
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_ATTR_4F_X(x)                             (0x00000500+((x)*16))
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_ATTR_4F_X__SIZE                          0x00000010
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_ATTR_4F_Y(x)                             (0x00000504+((x)*16))
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_ATTR_4F_Y__SIZE                          0x00000010
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_ATTR_4F_Z(x)                             (0x00000508+((x)*16))
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_ATTR_4F_Z__SIZE                          0x00000010
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_ATTR_4F_W(x)                             (0x0000050c+((x)*16))
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_ATTR_4F_W__SIZE                          0x00000010
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_2I                                   0x000006a0
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_2I                                   0x000006a4
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_2I                                   0x000006a8
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_2I                                   0x000006ac
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY                                        0x00000700
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW                                        0x00000704
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST                                        0x00000740
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ                                        0x00000744
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST                                        0x00000748
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ                                        0x0000074c
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST                                        0x00000750
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ                                        0x00000754
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST                                        0x00000758
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ                                        0x0000075c
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY                                        0x00000790
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z                                 0x00000794
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4I                                   0x0000088c
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3I                                  0x00000890
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT(x)                          (0x00000900+((x)*16))
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT__SIZE                       0x00000010
+#define  NV50_TCL_PRIMITIVE_3D_VIEWPORT_UNK0(x)                                        (0x00000a00+((x)*4))
+#define  NV50_TCL_PRIMITIVE_3D_VIEWPORT_UNK0__SIZE                             0x00000003
+#define  NV50_TCL_PRIMITIVE_3D_VIEWPORT_UNK1(x)                                        (0x00000a0c+((x)*4))
+#define  NV50_TCL_PRIMITIVE_3D_VIEWPORT_UNK1__SIZE                             0x00000003
+#define  NV50_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ                                  0x00000c00
+#define   NV50_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ_X_SHIFT                         0
+#define   NV50_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ_X_MASK                          0x0000ffff
+#define   NV50_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ_W_SHIFT                         16
+#define   NV50_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ_W_MASK                          0xffff0000
+#define  NV50_TCL_PRIMITIVE_3D_VIEWPORT_VERT                                   0x00000c04
+#define   NV50_TCL_PRIMITIVE_3D_VIEWPORT_VERT_Y_SHIFT                          0
+#define   NV50_TCL_PRIMITIVE_3D_VIEWPORT_VERT_Y_MASK                           0x0000ffff
+#define   NV50_TCL_PRIMITIVE_3D_VIEWPORT_VERT_H_SHIFT                          16
+#define   NV50_TCL_PRIMITIVE_3D_VIEWPORT_VERT_H_MASK                           0xffff0000
+#define  NV50_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR                                        0x00000c08
+#define  NV50_TCL_PRIMITIVE_3D_DEPTH_RANGE_FAR                                 0x00000c0c
+#define  NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(x)                          (0x00000d00+((x)*8))
+#define  NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ__SIZE                       0x00000008
+#define  NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT(x)                           (0x00000d04+((x)*8))
+#define  NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT__SIZE                                0x00000008
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_BUFFER_FIRST                             0x00000d74
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_BUFFER_COUNT                             0x00000d78
+#define  NV50_TCL_PRIMITIVE_3D_CLEAR_COLOR(x)                                  (0x00000d80+((x)*4))
+#define  NV50_TCL_PRIMITIVE_3D_CLEAR_COLOR__SIZE                               0x00000004
+#define  NV50_TCL_PRIMITIVE_3D_CLEAR_DEPTH                                     0x00000d90
+#define  NV50_TCL_PRIMITIVE_3D_CLEAR_STENCIL                                   0x00000da0
+#define  NV50_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT                              0x00000dac
+#define  NV50_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT_POINT                                0x00001b00
+#define  NV50_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT_LINE                         0x00001b01
+#define  NV50_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT_FILL                         0x00001b02
+#define  NV50_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK                               0x00000db0
+#define  NV50_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK_POINT                         0x00001b00
+#define  NV50_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK_LINE                          0x00001b01
+#define  NV50_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK_FILL                          0x00001b02
+#define  NV50_TCL_PRIMITIVE_3D_POLYGON_SMOOTH_ENABLE                           0x00000db4
+#define  NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_POINT_ENABLE                     0x00000dc0
+#define  NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_LINE_ENABLE                      0x00000dc4
+#define  NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FILL_ENABLE                      0x00000dc8
+#define  NV50_TCL_PRIMITIVE_3D_SCISSOR_HORIZ                                   0x00000e04
+#define   NV50_TCL_PRIMITIVE_3D_SCISSOR_HORIZ_L_SHIFT                          0
+#define   NV50_TCL_PRIMITIVE_3D_SCISSOR_HORIZ_L_MASK                           0x0000ffff
+#define   NV50_TCL_PRIMITIVE_3D_SCISSOR_HORIZ_R_SHIFT                          16
+#define   NV50_TCL_PRIMITIVE_3D_SCISSOR_HORIZ_R_MASK                           0xffff0000
+#define  NV50_TCL_PRIMITIVE_3D_SCISSOR_VERT                                    0x00000e08
+#define   NV50_TCL_PRIMITIVE_3D_SCISSOR_VERT_T_SHIFT                           0
+#define   NV50_TCL_PRIMITIVE_3D_SCISSOR_VERT_T_MASK                            0x0000ffff
+#define   NV50_TCL_PRIMITIVE_3D_SCISSOR_VERT_B_SHIFT                           16
+#define   NV50_TCL_PRIMITIVE_3D_SCISSOR_VERT_B_MASK                            0xffff0000
+#define  NV50_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_ID                              0x00000f00
+#define  NV50_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST(x)                              (0x00000f04+((x)*4))
+#define  NV50_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST__SIZE                           0x00000010
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_REF                          0x00000f54
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_MASK                              0x00000f58
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_MASK                         0x00000f5c
+#define  NV50_TCL_PRIMITIVE_3D_DEPTH_TEST_ENABLE                               0x000012cc
+#define  NV50_TCL_PRIMITIVE_3D_SHADE_MODEL                                     0x000012d4
+#define  NV50_TCL_PRIMITIVE_3D_SHADE_MODEL_FLAT                                        0x00001d00
+#define  NV50_TCL_PRIMITIVE_3D_SHADE_MODEL_SMOOTH                              0x00001d01
+#define  NV50_TCL_PRIMITIVE_3D_DEPTH_WRITE_ENABLE                              0x000012e8
+#define  NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_ENABLE                               0x000012ec
+#define  NV50_TCL_PRIMITIVE_3D_DEPTH_FUNC                                      0x0000130c
+#define  NV50_TCL_PRIMITIVE_3D_DEPTH_FUNC_NEVER                                        0x00000200
+#define  NV50_TCL_PRIMITIVE_3D_DEPTH_FUNC_LESS                                 0x00000201
+#define  NV50_TCL_PRIMITIVE_3D_DEPTH_FUNC_EQUAL                                        0x00000202
+#define  NV50_TCL_PRIMITIVE_3D_DEPTH_FUNC_LEQUAL                               0x00000203
+#define  NV50_TCL_PRIMITIVE_3D_DEPTH_FUNC_GREATER                              0x00000204
+#define  NV50_TCL_PRIMITIVE_3D_DEPTH_FUNC_GREATER                              0x00000204
+#define  NV50_TCL_PRIMITIVE_3D_DEPTH_FUNC_NOTEQUAL                             0x00000205
+#define  NV50_TCL_PRIMITIVE_3D_DEPTH_FUNC_GEQUAL                               0x00000206
+#define  NV50_TCL_PRIMITIVE_3D_DEPTH_FUNC_ALWAYS                               0x00000207
+#define  NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_REF                                  0x00001310
+#define  NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC                                 0x00001314
+#define  NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_NEVER                           0x00000200
+#define  NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_LESS                            0x00000201
+#define  NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_EQUAL                           0x00000202
+#define  NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_LEQUAL                          0x00000203
+#define  NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_GREATER                         0x00000204
+#define  NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_GREATER                         0x00000204
+#define  NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_NOTEQUAL                                0x00000205
+#define  NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_GEQUAL                          0x00000206
+#define  NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC_ALWAYS                          0x00000207
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_COLOR(x)                                  (0x0000131c+((x)*4))
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_COLOR__SIZE                               0x00000004
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_EQUATION_RGB                              0x00001340
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_EQUATION_RGB_FUNC_ADD                     0x00008006
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_EQUATION_RGB_MIN                          0x00008007
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_EQUATION_RGB_MAX                          0x00008008
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_EQUATION_RGB_FUNC_SUBTRACT                        0x0000800a
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_EQUATION_RGB_FUNC_REVERSE_SUBTRACT                0x0000800b
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB                              0x00001344
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_ZERO                         0x00000000
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_ONE                          0x00000001
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_SRC_COLOR                    0x00000300
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_COLOR          0x00000301
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_SRC_ALPHA                    0x00000302
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_SRC_ALPHA          0x00000303
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_DST_ALPHA                    0x00000304
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_ALPHA          0x00000305
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_DST_COLOR                    0x00000306
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_DST_COLOR          0x00000307
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_SRC_ALPHA_SATURATE           0x00000308
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_CONSTANT_COLOR               0x00008001
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_COLOR     0x00008002
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_CONSTANT_ALPHA               0x00008003
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB_ONE_MINUS_CONSTANT_ALPHA     0x00008004
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB                              0x00001348
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_ZERO                         0x00000000
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_ONE                          0x00000001
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_SRC_COLOR                    0x00000300
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_COLOR          0x00000301
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_SRC_ALPHA                    0x00000302
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_SRC_ALPHA          0x00000303
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_DST_ALPHA                    0x00000304
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_ALPHA          0x00000305
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_DST_COLOR                    0x00000306
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_DST_COLOR          0x00000307
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_SRC_ALPHA_SATURATE           0x00000308
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_CONSTANT_COLOR               0x00008001
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_COLOR     0x00008002
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_CONSTANT_ALPHA               0x00008003
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB_ONE_MINUS_CONSTANT_ALPHA     0x00008004
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_EQUATION_ALPHA                            0x0000134c
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_EQUATION_ALPHA_FUNC_ADD                   0x00008006
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_EQUATION_ALPHA_MIN                                0x00008007
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_EQUATION_ALPHA_MAX                                0x00008008
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_EQUATION_ALPHA_FUNC_SUBTRACT              0x0000800a
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_EQUATION_ALPHA_FUNC_REVERSE_SUBTRACT      0x0000800b
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA                            0x00001350
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_ZERO                       0x00000000
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_ONE                                0x00000001
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_SRC_COLOR                  0x00000300
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_COLOR                0x00000301
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA                  0x00000302
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_SRC_ALPHA                0x00000303
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_DST_ALPHA                  0x00000304
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_ALPHA                0x00000305
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_DST_COLOR                  0x00000306
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_DST_COLOR                0x00000307
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_SRC_ALPHA_SATURATE         0x00000308
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_CONSTANT_COLOR             0x00008001
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_COLOR   0x00008002
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_CONSTANT_ALPHA             0x00008003
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA_ONE_MINUS_CONSTANT_ALPHA   0x00008004
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA                            0x00001358
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_ZERO                       0x00000000
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_ONE                                0x00000001
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_SRC_COLOR                  0x00000300
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_COLOR                0x00000301
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_SRC_ALPHA                  0x00000302
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_SRC_ALPHA                0x00000303
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_DST_ALPHA                  0x00000304
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_ALPHA                0x00000305
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_DST_COLOR                  0x00000306
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_DST_COLOR                0x00000307
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_SRC_ALPHA_SATURATE         0x00000308
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_CONSTANT_COLOR             0x00008001
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_COLOR   0x00008002
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_CONSTANT_ALPHA             0x00008003
+#define  NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_ALPHA   0x00008004
+#define  NV50_TCL_PRIMITIVE_3D_UNK1360(x)                                      (0x00001360+((x)*4))
+#define  NV50_TCL_PRIMITIVE_3D_UNK1360__SIZE                                   0x00000008
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_ENABLE                             0x00001380
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL                            0x00001384
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL_ZERO                       0x00000000
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL_INVERT                     0x0000150a
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL_KEEP                       0x00001e00
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL_REPLACE                    0x00001e01
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL_INCR                       0x00001e02
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL_DECR                       0x00001e03
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL_INCR_WRAP                  0x00008507
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL_DECR_WRAP                  0x00008508
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL                           0x00001388
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL_ZERO                      0x00000000
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL_INVERT                    0x0000150a
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL_KEEP                      0x00001e00
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL_REPLACE                   0x00001e01
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL_INCR                      0x00001e02
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL_DECR                      0x00001e03
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL_INCR_WRAP                 0x00008507
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL_DECR_WRAP                 0x00008508
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS                           0x0000138c
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS_ZERO                      0x00000000
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS_INVERT                    0x0000150a
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS_KEEP                      0x00001e00
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS_REPLACE                   0x00001e01
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS_INCR                      0x00001e02
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS_DECR                      0x00001e03
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS_INCR_WRAP                 0x00008507
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS_DECR_WRAP                 0x00008508
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC                          0x00001390
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC_NEVER                    0x00000200
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC_LESS                     0x00000201
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC_EQUAL                    0x00000202
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC_LEQUAL                   0x00000203
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC_GREATER                  0x00000204
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC_GREATER                  0x00000204
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC_NOTEQUAL                 0x00000205
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC_GEQUAL                   0x00000206
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC_ALWAYS                   0x00000207
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_REF                           0x00001394
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_MASK                               0x00001398
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_MASK                          0x0000139c
+#define  NV50_TCL_PRIMITIVE_3D_LINE_WIDTH                                      0x000013b0
+#define  NV50_TCL_PRIMITIVE_3D_VP_INST                                         0x0000140c
+#define  NV50_TCL_PRIMITIVE_3D_POINT_SIZE                                      0x00001518
+#define  NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FACTOR                           0x0000156c
+#define  NV50_TCL_PRIMITIVE_3D_LINE_SMOOTH_ENABLE                              0x00001570
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_ENABLE                            0x00001594
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL                           0x00001598
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL_ZERO                      0x00000000
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL_INVERT                    0x0000150a
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL_KEEP                      0x00001e00
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL_REPLACE                   0x00001e01
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL_INCR                      0x00001e02
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL_DECR                      0x00001e03
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL_INCR_WRAP                 0x00008507
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL_DECR_WRAP                 0x00008508
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL                          0x0000159c
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL_ZERO                     0x00000000
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL_INVERT                   0x0000150a
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL_KEEP                     0x00001e00
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL_REPLACE                  0x00001e01
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL_INCR                     0x00001e02
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL_DECR                     0x00001e03
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL_INCR_WRAP                        0x00008507
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL_DECR_WRAP                        0x00008508
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS                          0x000015a0
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS_ZERO                     0x00000000
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS_INVERT                   0x0000150a
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS_KEEP                     0x00001e00
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS_REPLACE                  0x00001e01
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS_INCR                     0x00001e02
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS_DECR                     0x00001e03
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS_INCR_WRAP                        0x00008507
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS_DECR_WRAP                        0x00008508
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC                         0x000015a4
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC_NEVER                   0x00000200
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC_LESS                    0x00000201
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC_EQUAL                   0x00000202
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC_LEQUAL                  0x00000203
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC_GREATER                 0x00000204
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC_GREATER                 0x00000204
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC_NOTEQUAL                        0x00000205
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC_GEQUAL                  0x00000206
+#define  NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC_ALWAYS                  0x00000207
+#define  NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_UNITS                            0x000015bc
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_BEGIN                                    0x000015dc
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_BEGIN_POINTS                             0x00000000
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_BEGIN_LINES                              0x00000001
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_BEGIN_LINE_LOOP                          0x00000002
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_BEGIN_LINE_STRIP                         0x00000003
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_BEGIN_TRIANGLES                          0x00000004
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_BEGIN_TRIANGLE_STRIP                     0x00000005
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_BEGIN_TRIANGLE_FAN                       0x00000006
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_BEGIN_QUADS                              0x00000007
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_BEGIN_QUAD_STRIP                         0x00000008
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_BEGIN_POLYGON                            0x00000009
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_END                                      0x000015e0
+#define  NV50_TCL_PRIMITIVE_3D_VERTEX_DATA                                     0x00001640
+#define  NV50_TCL_PRIMITIVE_3D_VP_INST_PARAMS(x)                               (0x00001650+((x)*4))
+#define  NV50_TCL_PRIMITIVE_3D_VP_INST_PARAMS__SIZE                            0x00000002
+#define  NV50_TCL_PRIMITIVE_3D_LINE_STIPPLE_ENABLE                             0x0000166c
+#define  NV50_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN                            0x00001680
+#define  NV50_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_ENABLE                          0x0000168c
+#define  NV50_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_PATTERN(x)                      (0x00001700+((x)*4))
+#define  NV50_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_PATTERN__SIZE                   0x00000020
+#define  NV50_TCL_PRIMITIVE_3D_CULL_FACE_ENABLE                                        0x00001918
+#define  NV50_TCL_PRIMITIVE_3D_FRONT_FACE                                      0x0000191c
+#define  NV50_TCL_PRIMITIVE_3D_FRONT_FACE_CW                                   0x00000900
+#define  NV50_TCL_PRIMITIVE_3D_FRONT_FACE_CCW                                  0x00000901
+#define  NV50_TCL_PRIMITIVE_3D_CULL_FACE                                       0x00001920
+#define  NV50_TCL_PRIMITIVE_3D_CULL_FACE_FRONT                                 0x00000404
+#define  NV50_TCL_PRIMITIVE_3D_CULL_FACE_BACK                                  0x00000405
+#define  NV50_TCL_PRIMITIVE_3D_CULL_FACE_FRONT_AND_BACK                                0x00000408
+#define  NV50_TCL_PRIMITIVE_3D_LOGIC_OP_ENABLE                                 0x000019c4
+#define  NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP                                     0x000019c8
+#define  NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP_CLEAR                               0x00001500
+#define  NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP_AND                                 0x00001501
+#define  NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP_AND_REVERSE                         0x00001502
+#define  NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP_COPY                                        0x00001503
+#define  NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP_AND_INVERTED                                0x00001504
+#define  NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP_NOOP                                        0x00001505
+#define  NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP_XOR                                 0x00001506
+#define  NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP_OR                                  0x00001507
+#define  NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP_NOR                                 0x00001508
+#define  NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP_EQUIV                               0x00001509
+#define  NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP_INVERT                              0x0000150a
+#define  NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP_OR_REVERSE                          0x0000150b
+#define  NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP_COPY_INVERTED                       0x0000150c
+#define  NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP_OR_INVERTED                         0x0000150d
+#define  NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP_NAND                                        0x0000150e
+#define  NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP_SET                                 0x0000150f
+#define  NV50_TCL_PRIMITIVE_3D_CLEAR_BUFFERS                                   0x000019d0
+#define  NV50_TCL_PRIMITIVE_3D_COLOR_MASK(x)                                   (0x00001a00+((x)*4))
+#define  NV50_TCL_PRIMITIVE_3D_COLOR_MASK__SIZE                                        0x00000008
+
+
+#define NV52_TCL_PRIMITIVE_3D                                                  0x00008297
+
+
+
+#endif /* NOUVEAU_REG_H */

diff --git a/src/mesa/pipe/nouveau/nouveau_grobj.h b/src/mesa/pipe/nouveau/nouveau_grobj.h
new file mode 100644 (file)
index 0000000..a36db7f
--- /dev/null
+++ b/src/mesa/pipe/nouveau/nouveau_grobj.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2007 Nouveau Project
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef __NOUVEAU_GROBJ_H__
+#define __NOUVEAU_GROBJ_H__
+
+#include "nouveau_channel.h"
+
+struct nouveau_grobj {
+       struct nouveau_channel *channel;
+       int grclass;
+       uint32_t handle;
+
+       enum {
+               NOUVEAU_GROBJ_UNBOUND = 0,
+               NOUVEAU_GROBJ_BOUND = 1,
+               NOUVEAU_GROBJ_EXPLICIT_BIND = 2,
+       } bound;
+       int subc;
+};
+
+#endif

diff --git a/src/mesa/pipe/nouveau/nouveau_notifier.h b/src/mesa/pipe/nouveau/nouveau_notifier.h
new file mode 100644 (file)
index 0000000..35adde1
--- /dev/null
+++ b/src/mesa/pipe/nouveau/nouveau_notifier.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2007 Nouveau Project
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef __NOUVEAU_NOTIFIER_H__
+#define __NOUVEAU_NOTIFIER_H__
+
+#define NV_NOTIFIER_SIZE                                                      32
+#define NV_NOTIFY_TIME_0                                              0x00000000
+#define NV_NOTIFY_TIME_1                                              0x00000004
+#define NV_NOTIFY_RETURN_VALUE                                        0x00000008
+#define NV_NOTIFY_STATE                                               0x0000000C
+#define NV_NOTIFY_STATE_STATUS_MASK                                   0xFF000000
+#define NV_NOTIFY_STATE_STATUS_SHIFT                                          24
+#define NV_NOTIFY_STATE_STATUS_COMPLETED                                    0x00
+#define NV_NOTIFY_STATE_STATUS_IN_PROCESS                                   0x01
+#define NV_NOTIFY_STATE_ERROR_CODE_MASK                               0x0000FFFF
+#define NV_NOTIFY_STATE_ERROR_CODE_SHIFT                                       0
+
+struct nouveau_notifier {
+       struct nouveau_channel *channel;
+       uint32_t handle;
+};
+
+#endif

diff --git a/src/mesa/pipe/nouveau/nouveau_winsys.h b/src/mesa/pipe/nouveau/nouveau_winsys.h
new file mode 100644 (file)
index 0000000..beee49a
--- /dev/null
+++ b/src/mesa/pipe/nouveau/nouveau_winsys.h
@@ -0,0 +1,53 @@
+#ifndef NOUVEAU_WINSYS_H
+#define NOUVEAU_WINSYS_H
+
+#include <stdint.h>
+#include "pipe/p_winsys.h"
+
+#include "pipe/nouveau/nouveau_bo.h"
+#include "pipe/nouveau/nouveau_channel.h"
+#include "pipe/nouveau/nouveau_class.h"
+#include "pipe/nouveau/nouveau_grobj.h"
+#include "pipe/nouveau/nouveau_notifier.h"
+
+struct nouveau_winsys {
+       struct nouveau_context *nv;
+
+       struct nouveau_channel *channel;
+
+       /*XXX: this is crappy, and bound to be slow.. however, it's nice and
+        *     simple, it'll do for the moment*/
+       uint32_t *(*begin_ring)(struct nouveau_grobj *, int mthd, int size);
+       void      (*out_reloc)(struct nouveau_channel *, void *ptr,
+                              struct nouveau_bo *, uint32_t data,
+                              uint32_t flags, uint32_t vor, uint32_t tor);
+       void      (*fire_ring)(struct nouveau_channel *);
+                              
+       int       (*grobj_alloc)(struct nouveau_winsys *, int grclass,
+                                struct nouveau_grobj **);
+       void      (*grobj_free)(struct nouveau_grobj **);
+
+       int       (*notifier_alloc)(struct nouveau_winsys *, int count,
+                                   struct nouveau_notifier **);
+       void      (*notifier_free)(struct nouveau_notifier **);
+       void      (*notifier_reset)(struct nouveau_notifier *, int id);
+       uint32_t  (*notifier_status)(struct nouveau_notifier *, int id);
+       uint32_t  (*notifier_retval)(struct nouveau_notifier *, int id);
+       int       (*notifier_wait)(struct nouveau_notifier *, int id,
+                                  int status, int timeout);
+
+       int (*region_copy)(struct nouveau_context *, struct pipe_region *,
+                          unsigned, unsigned, unsigned, struct pipe_region *,
+                          unsigned, unsigned, unsigned, unsigned, unsigned);
+       int (*region_fill)(struct nouveau_context *, struct pipe_region *,
+                          unsigned, unsigned, unsigned, unsigned, unsigned,
+                          unsigned);
+       int (*region_data)(struct nouveau_context *, struct pipe_region *,
+                          unsigned, unsigned, unsigned, const void *,
+                          unsigned, unsigned, unsigned, unsigned, unsigned);
+};
+
+extern struct pipe_context *
+nv40_create(struct pipe_winsys *, struct nouveau_winsys *, unsigned chipset);
+
+#endif

diff --git a/src/mesa/pipe/nv40/Makefile b/src/mesa/pipe/nv40/Makefile
new file mode 100644 (file)
index 0000000..90c8542
--- /dev/null
+++ b/src/mesa/pipe/nv40/Makefile
@@ -0,0 +1,30 @@
+TOP = ../../../..
+include $(TOP)/configs/current
+
+LIBNAME = nv40
+
+DRIVER_SOURCES = \
+       nv40_clear.c \
+       nv40_context.c \
+       nv40_draw.c \
+       nv40_fragprog.c \
+       nv40_miptree.c \
+       nv40_query.c \
+       nv40_region.c \
+       nv40_state.c \
+       nv40_state_emit.c \
+       nv40_state_tex.c \
+       nv40_surface.c \
+       nv40_vbo.c \
+       nv40_vertprog.c
+
+C_SOURCES = \
+       $(COMMON_SOURCES) \
+       $(DRIVER_SOURCES)
+
+ASM_SOURCES = 
+
+include ../Makefile.template
+
+symlinks:
+

diff --git a/src/mesa/pipe/nv40/nv40_clear.c b/src/mesa/pipe/nv40/nv40_clear.c
new file mode 100644 (file)
index 0000000..f3b7a23
--- /dev/null
+++ b/src/mesa/pipe/nv40/nv40_clear.c
@@ -0,0 +1,21 @@
+#include "pipe/p_context.h"
+#include "pipe/p_defines.h"
+#include "pipe/p_state.h"
+
+#include "nv40_context.h"
+#include "nv40_dma.h"
+
+
+void
+nv40_clear(struct pipe_context *pipe, struct pipe_surface *ps,
+          unsigned clearValue)
+{
+       /*XXX: We're actually Z24_S8... */
+       if (ps->format == PIPE_FORMAT_S8_Z24) {
+               clearValue = (((clearValue & 0xff000000) >> 24) |
+                             ((clearValue & 0x00ffffff) <<  8));
+       }
+
+       pipe->region_fill(pipe, ps->region, 0, 0, 0, ps->width, ps->height,
+                         clearValue);
+}

diff --git a/src/mesa/pipe/nv40/nv40_context.c b/src/mesa/pipe/nv40/nv40_context.c
new file mode 100644 (file)
index 0000000..ff66095
--- /dev/null
+++ b/src/mesa/pipe/nv40/nv40_context.c
@@ -0,0 +1,277 @@
+#include "pipe/draw/draw_context.h"
+#include "pipe/p_defines.h"
+#include "pipe/p_winsys.h"
+#include "pipe/p_util.h"
+
+#include "nv40_context.h"
+#include "nv40_dma.h"
+
+static boolean
+nv40_is_format_supported(struct pipe_context *pipe, uint format)
+{
+       switch (format) {
+       case PIPE_FORMAT_U_A8_R8_G8_B8:
+       case PIPE_FORMAT_U_R5_G6_B5: 
+       case PIPE_FORMAT_S8_Z24: 
+               return TRUE;
+       default:
+               break;
+       };
+
+       return FALSE;
+}
+
+static const char *
+nv40_get_name(struct pipe_context *pipe)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       static char buffer[128];
+
+       snprintf(buffer, sizeof(buffer), "NV%02X", nv40->chipset);
+       return buffer;
+}
+
+static const char *
+nv40_get_vendor(struct pipe_context *pipe)
+{
+       return "nouveau";
+}
+
+static int
+nv40_get_param(struct pipe_context *pipe, int param)
+{
+       switch (param) {
+       case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
+               return 16;
+       case PIPE_CAP_NPOT_TEXTURES:
+               return 1;
+       case PIPE_CAP_TWO_SIDED_STENCIL:
+               return 1;
+       case PIPE_CAP_GLSL:
+               return 0;
+       case PIPE_CAP_S3TC:
+               return 0;
+       case PIPE_CAP_ANISOTROPIC_FILTER:
+               return 0;
+       case PIPE_CAP_POINT_SPRITE:
+               return 0;
+       case PIPE_CAP_MAX_RENDER_TARGETS:
+               return 4;
+       case PIPE_CAP_OCCLUSION_QUERY:
+               return 1;
+       case PIPE_CAP_TEXTURE_SHADOW_MAP:
+               return 0;
+       case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
+               return 13;
+       case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
+               return 10;
+       case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
+               return 13;
+       default:
+               NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
+               return 0;
+       }
+}
+
+static float
+nv40_get_paramf(struct pipe_context *pipe, int param)
+{
+       switch (param) {
+       case PIPE_CAP_MAX_LINE_WIDTH:
+       case PIPE_CAP_MAX_LINE_WIDTH_AA:
+       case PIPE_CAP_MAX_POINT_WIDTH:
+       case PIPE_CAP_MAX_POINT_WIDTH_AA:
+       case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
+       case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
+       default:
+               NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
+               return 0.0;
+       }
+}
+
+static void
+nv40_flush(struct pipe_context *pipe, unsigned flags)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       struct nouveau_winsys *nvws = nv40->nvws;
+       
+       if (flags & PIPE_FLUSH_TEXTURE_CACHE) {
+               BEGIN_RING(curie, 0x1fd8, 1);
+               OUT_RING  (2);
+               BEGIN_RING(curie, 0x1fd8, 1);
+               OUT_RING  (1);
+       }
+
+       if (flags & PIPE_FLUSH_WAIT) {
+               nvws->notifier_reset(nv40->sync, 0);
+               BEGIN_RING(curie, 0x104, 1);
+               OUT_RING  (0);
+               BEGIN_RING(curie, 0x100, 1);
+               OUT_RING  (0);
+       }
+
+       FIRE_RING();
+
+       if (flags & PIPE_FLUSH_WAIT)
+               nvws->notifier_wait(nv40->sync, 0, 0, 2000);
+}
+
+static void
+nv40_destroy(struct pipe_context *pipe)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+
+       draw_destroy(nv40->draw);
+       free(nv40);
+}
+
+static boolean
+nv40_init_hwctx(struct nv40_context *nv40, int curie_class)
+{
+       struct nouveau_winsys *nvws = nv40->nvws;
+       int ret;
+
+       if ((ret = nvws->notifier_alloc(nvws, nv40->num_query_objects,
+                                       &nv40->query))) {
+               NOUVEAU_ERR("Error creating query notifier objects: %d\n", ret);
+               return FALSE;
+       }
+
+       if ((ret = nvws->grobj_alloc(nvws, curie_class,
+                                    &nv40->curie))) {
+               NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
+               return FALSE;
+       }
+
+       BEGIN_RING(curie, NV40TCL_DMA_NOTIFY, 1);
+       OUT_RING  (nv40->sync->handle);
+       BEGIN_RING(curie, NV40TCL_DMA_TEXTURE0, 2);
+       OUT_RING  (nvws->channel->vram->handle);
+       OUT_RING  (nvws->channel->gart->handle);
+       BEGIN_RING(curie, NV40TCL_DMA_COLOR1, 1);
+       OUT_RING  (nvws->channel->vram->handle);
+       BEGIN_RING(curie, NV40TCL_DMA_COLOR0, 2);
+       OUT_RING  (nvws->channel->vram->handle);
+       OUT_RING  (nvws->channel->vram->handle);
+       BEGIN_RING(curie, NV40TCL_DMA_VTXBUF0, 2);
+       OUT_RING  (nvws->channel->vram->handle);
+       OUT_RING  (nvws->channel->gart->handle);
+       BEGIN_RING(curie, NV40TCL_DMA_FENCE, 2);
+       OUT_RING  (0);
+       OUT_RING  (nv40->query->handle);
+       BEGIN_RING(curie, NV40TCL_DMA_UNK01AC, 2);
+       OUT_RING  (nvws->channel->vram->handle);
+       OUT_RING  (nvws->channel->vram->handle);
+       BEGIN_RING(curie, NV40TCL_DMA_COLOR2, 2);
+       OUT_RING  (nvws->channel->vram->handle);
+       OUT_RING  (nvws->channel->vram->handle);
+
+       BEGIN_RING(curie, 0x1ea4, 3);
+       OUT_RING  (0x00000010);
+       OUT_RING  (0x01000100);
+       OUT_RING  (0xff800006);
+
+       /* vtxprog output routing */
+       BEGIN_RING(curie, 0x1fc4, 1);
+       OUT_RING  (0x06144321);
+       BEGIN_RING(curie, 0x1fc8, 2);
+       OUT_RING  (0xedcba987);
+       OUT_RING  (0x00000021);
+       BEGIN_RING(curie, 0x1fd0, 1);
+       OUT_RING  (0x00171615);
+       BEGIN_RING(curie, 0x1fd4, 1);
+       OUT_RING  (0x001b1a19);
+
+       BEGIN_RING(curie, 0x1ef8, 1);
+       OUT_RING  (0x0020ffff);
+       BEGIN_RING(curie, 0x1d64, 1);
+       OUT_RING  (0x00d30000);
+       BEGIN_RING(curie, 0x1e94, 1);
+       OUT_RING  (0x00000001);
+
+       FIRE_RING ();
+       return TRUE;
+}
+
+#define GRCLASS4097_CHIPSETS 0x00000baf
+#define GRCLASS4497_CHIPSETS 0x00005450
+struct pipe_context *
+nv40_create(struct pipe_winsys *pipe_winsys, struct nouveau_winsys *nvws,
+           unsigned chipset)
+{
+       struct nv40_context *nv40;
+       int curie_class, ret;
+
+       if ((chipset & 0xf0) != 0x40) {
+               NOUVEAU_ERR("Not a NV4X chipset\n");
+               return NULL;
+       }
+
+       if (GRCLASS4097_CHIPSETS & (1 << (chipset & 0x0f))) {
+               curie_class = 0x4097;
+       } else
+       if (GRCLASS4497_CHIPSETS & (1 << (chipset & 0x0f))) {
+               curie_class = 0x4497;
+       } else {
+               NOUVEAU_ERR("Unknown NV4X chipset: NV%02x\n", chipset);
+               return NULL;
+       }
+
+       nv40 = CALLOC_STRUCT(nv40_context);
+       if (!nv40)
+               return NULL;
+       nv40->chipset = chipset;
+       nv40->nvws = nvws;
+
+       if ((ret = nvws->notifier_alloc(nvws, 1, &nv40->sync))) {
+               NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
+               free(nv40);
+               return NULL;
+       }
+
+       nv40->num_query_objects = 32;
+       nv40->query_objects = calloc(nv40->num_query_objects,
+                                    sizeof(struct pipe_query_object *));
+       if (!nv40->query_objects) {
+               free(nv40);
+               return NULL;
+       }
+
+       if (!nv40_init_hwctx(nv40, curie_class)) {
+               free(nv40);
+               return NULL;
+       }
+
+       nv40->pipe.winsys = pipe_winsys;
+
+       nv40->pipe.destroy = nv40_destroy;
+       nv40->pipe.is_format_supported = nv40_is_format_supported;
+       nv40->pipe.get_name = nv40_get_name;
+       nv40->pipe.get_vendor = nv40_get_vendor;
+       nv40->pipe.get_param = nv40_get_param;
+       nv40->pipe.get_paramf = nv40_get_paramf;
+
+       nv40->pipe.draw_arrays = nv40_draw_arrays;
+       nv40->pipe.draw_elements = nv40_draw_elements;
+       nv40->pipe.clear = nv40_clear;
+
+       nv40->pipe.begin_query = nv40_query_begin;
+       nv40->pipe.end_query = nv40_query_end;
+       nv40->pipe.wait_query = nv40_query_wait;
+
+       nv40->pipe.mipmap_tree_layout = nv40_miptree_layout;
+
+       nv40->pipe.flush = nv40_flush;
+
+       nv40_init_region_functions(nv40);
+       nv40_init_surface_functions(nv40);
+       nv40_init_state_functions(nv40);
+
+       nv40->draw = draw_create();
+       assert(nv40->draw);
+       draw_set_rasterize_stage(nv40->draw, nv40_draw_render_stage(nv40));
+
+       return &nv40->pipe;
+}
+
+               

diff --git a/src/mesa/pipe/nv40/nv40_context.h b/src/mesa/pipe/nv40/nv40_context.h
new file mode 100644 (file)
index 0000000..63be382
--- /dev/null
+++ b/src/mesa/pipe/nv40/nv40_context.h
@@ -0,0 +1,111 @@
+#ifndef __NV40_CONTEXT_H__
+#define __NV40_CONTEXT_H__
+
+#include "pipe/p_context.h"
+#include "pipe/p_defines.h"
+#include "pipe/p_state.h"
+
+#include "pipe/draw/draw_vertex.h"
+
+#include "pipe/nouveau/nouveau_winsys.h"
+
+#include "nv40_state.h"
+
+#define NOUVEAU_ERR(fmt, args...) \
+       fprintf(stderr, "%s:%d -  "fmt, __func__, __LINE__, ##args);
+#define NOUVEAU_MSG(fmt, args...) \
+       fprintf(stderr, "nouveau: "fmt, ##args);
+
+#define NV40_NEW_TEXTURE       (1 << 0)
+#define NV40_NEW_VERTPROG      (1 << 1)
+#define NV40_NEW_FRAGPROG      (1 << 2)
+#define NV40_NEW_ARRAYS                (1 << 3)
+
+struct nv40_context {
+       struct pipe_context pipe;
+       struct nouveau_winsys *nvws;
+
+       struct draw_context *draw;
+
+       int chipset;
+       struct nouveau_grobj *curie;
+       struct nouveau_notifier *sync;
+       uint32_t *pushbuf;
+
+       /* query objects */
+       struct nouveau_notifier *query;
+       struct pipe_query_object **query_objects;
+       uint num_query_objects;
+
+       uint32_t dirty;
+
+       struct nv40_sampler_state *tex_sampler[PIPE_MAX_SAMPLERS];
+       struct pipe_mipmap_tree   *tex_miptree[PIPE_MAX_SAMPLERS];
+       uint32_t                   tex_dirty;
+
+       struct {
+               struct nv40_vertex_program *vp;
+               struct nv40_vertex_program *active_vp;
+
+               struct pipe_buffer_handle *constant_buf;
+       } vertprog;
+
+       struct {
+               struct nv40_fragment_program *fp;
+               struct nv40_fragment_program *active_fp;
+
+               struct pipe_buffer_handle *constant_buf;
+       } fragprog;
+
+       struct pipe_vertex_buffer  vtxbuf[PIPE_ATTRIB_MAX];
+       struct pipe_vertex_element vtxelt[PIPE_ATTRIB_MAX];
+};
+
+
+extern void nv40_init_region_functions(struct nv40_context *nv40);
+extern void nv40_init_surface_functions(struct nv40_context *nv40);
+extern void nv40_init_state_functions(struct nv40_context *nv40);
+
+/* nv40_draw.c */
+extern struct draw_stage *nv40_draw_render_stage(struct nv40_context *nv40);
+
+/* nv40_miptree.c */
+extern boolean nv40_miptree_layout(struct pipe_context *,
+                                  struct pipe_mipmap_tree *);
+
+/* nv40_vertprog.c */
+extern void nv40_vertprog_translate(struct nv40_context *,
+                                   struct nv40_vertex_program *);
+extern void nv40_vertprog_bind(struct nv40_context *,
+                              struct nv40_vertex_program *);
+
+/* nv40_fragprog.c */
+extern void nv40_fragprog_translate(struct nv40_context *,
+                                   struct nv40_fragment_program *);
+extern void nv40_fragprog_bind(struct nv40_context *,
+                              struct nv40_fragment_program *);
+
+/* nv40_state.c and friends */
+extern void nv40_emit_hw_state(struct nv40_context *nv40);
+extern void nv40_state_tex_update(struct nv40_context *nv40);
+
+/* nv40_vbo.c */
+extern boolean nv40_draw_arrays(struct pipe_context *, unsigned mode,
+                               unsigned start, unsigned count);
+extern boolean nv40_draw_elements(struct pipe_context *pipe,
+                                 struct pipe_buffer_handle *indexBuffer,
+                                 unsigned indexSize,
+                                 unsigned mode, unsigned start,
+                                 unsigned count);
+extern void nv40_vbo_arrays_update(struct nv40_context *nv40);
+
+/* nv40_clear.c */
+extern void nv40_clear(struct pipe_context *pipe, struct pipe_surface *ps,
+                      unsigned clearValue);
+
+/* nv40_query.c */
+extern void nv40_query_begin(struct pipe_context *, struct pipe_query_object *);
+extern void nv40_query_end(struct pipe_context *, struct pipe_query_object *);
+extern void nv40_query_wait(struct pipe_context *, struct pipe_query_object *);
+
+#endif

diff --git a/src/mesa/pipe/nv40/nv40_dma.h b/src/mesa/pipe/nv40/nv40_dma.h
new file mode 100644 (file)
index 0000000..3775ce6
--- /dev/null
+++ b/src/mesa/pipe/nv40/nv40_dma.h
@@ -0,0 +1,62 @@
+#ifndef __NV40_DMA_H__
+#define __NV40_DMA_H__
+
+#include "pipe/nouveau/nouveau_winsys.h"
+
+#define BEGIN_RING(obj,mthd,size) do {                                         \
+       nv40->pushbuf = nv40->nvws->begin_ring(nv40->obj, (mthd), (size));     \
+} while(0)
+
+#define BEGIN_RING_NI(obj,mthd,size) do {                                      \
+       BEGIN_RING(obj, (mthd) | 0x40000000, (size));                          \
+} while(0)
+
+#define OUT_RING(data) do {                                                    \
+       (*nv40->pushbuf++) = (data);                                           \
+} while(0)
+
+#define OUT_RINGp(src,size) do {                                               \
+       memcpy(nv40->pushbuf, (src), (size) * 4);                              \
+       nv40->pushbuf += (size);                                               \
+} while(0)
+
+#define OUT_RINGf(data) do {                                                   \
+       union { float v; uint32_t u; } c;                                      \
+       c.v = (data);                                                          \
+       OUT_RING(c.u);                                                         \
+} while(0)
+
+#define FIRE_RING() do {                                                       \
+       nv40->nvws->fire_ring(nv40->nvws->channel);                            \
+} while(0)
+
+#define OUT_RELOC(bo,data,flags,vor,tor) do {                                  \
+       nv40->nvws->out_reloc(nv40->nvws->channel, nv40->pushbuf,              \
+                             (struct nouveau_bo *)(bo),                       \
+                             (data), (flags), (vor), (tor));                  \
+       OUT_RING(0);                                                           \
+} while(0)
+
+/* Raw data + flags depending on FB/TT buffer */
+#define OUT_RELOCd(bo,data,flags,vor,tor) do {                                 \
+       OUT_RELOC((bo), (data), (flags) | NOUVEAU_BO_OR, (vor), (tor));        \
+} while(0)
+
+/* FB/TT object handle */
+#define OUT_RELOCo(bo,flags) do {                                              \
+       OUT_RELOC((bo), 0, (flags) | NOUVEAU_BO_OR,                            \
+                 nv40->nvws->channel->vram->handle,                           \
+                 nv40->nvws->channel->gart->handle);                          \
+} while(0)
+
+/* Low 32-bits of offset */
+#define OUT_RELOCl(bo,delta,flags) do {                                        \
+       OUT_RELOC((bo), (delta), (flags) | NOUVEAU_BO_LOW, 0, 0);              \
+} while(0)
+
+/* High 32-bits of offset */
+#define OUT_RELOCh(bo,delta,flags) do {                                        \
+       OUT_RELOC((bo), (delta), (flags) | NOUVEAU_BO_HIGH, 0, 0);             \
+} while(0)
+
+#endif

diff --git a/src/mesa/pipe/nv40/nv40_draw.c b/src/mesa/pipe/nv40/nv40_draw.c
new file mode 100644 (file)
index 0000000..52ce493
--- /dev/null
+++ b/src/mesa/pipe/nv40/nv40_draw.c
@@ -0,0 +1,63 @@
+#include "pipe/draw/draw_private.h"
+#include "pipe/p_util.h"
+
+#include "nv40_context.h"
+
+struct nv40_draw_stage {
+       struct draw_stage draw;
+       struct nv40_context *nv40;
+};
+
+static void
+nv40_draw_begin(struct draw_stage *draw)
+{
+       NOUVEAU_ERR("\n");
+}
+
+static void
+nv40_draw_end(struct draw_stage *draw)
+{
+       NOUVEAU_ERR("\n");
+}
+
+static void
+nv40_draw_point(struct draw_stage *draw, struct prim_header *prim)
+{
+       NOUVEAU_ERR("\n");
+}
+
+static void
+nv40_draw_line(struct draw_stage *draw, struct prim_header *prim)
+{
+       NOUVEAU_ERR("\n");
+}
+
+static void
+nv40_draw_tri(struct draw_stage *draw, struct prim_header *prim)
+{
+       NOUVEAU_ERR("\n");
+}
+
+static void
+nv40_draw_reset_stipple_counter(struct draw_stage *draw)
+{
+       NOUVEAU_ERR("\n");
+}
+
+struct draw_stage *
+nv40_draw_render_stage(struct nv40_context *nv40)
+{
+       struct nv40_draw_stage *nv40draw = CALLOC_STRUCT(nv40_draw_stage);
+
+       nv40draw->nv40 = nv40;
+       nv40draw->draw.draw = nv40->draw;
+       nv40draw->draw.begin = nv40_draw_begin;
+       nv40draw->draw.point = nv40_draw_point;
+       nv40draw->draw.line = nv40_draw_line;
+       nv40draw->draw.tri = nv40_draw_tri;
+       nv40draw->draw.end = nv40_draw_end;
+       nv40draw->draw.reset_stipple_counter = nv40_draw_reset_stipple_counter;
+
+       return &nv40draw->draw;
+}
+

diff --git a/src/mesa/pipe/nv40/nv40_fragprog.c b/src/mesa/pipe/nv40/nv40_fragprog.c
new file mode 100644 (file)
index 0000000..48b783e
--- /dev/null
+++ b/src/mesa/pipe/nv40/nv40_fragprog.c
@@ -0,0 +1,642 @@
+#include "pipe/p_context.h"
+#include "pipe/p_defines.h"
+#include "pipe/p_state.h"
+
+#include "pipe/tgsi/exec/tgsi_token.h"
+#include "pipe/tgsi/exec/tgsi_parse.h"
+
+#include "nv40_context.h"
+#include "nv40_dma.h"
+
+#define SWZ_X 0
+#define SWZ_Y 1
+#define SWZ_Z 2
+#define SWZ_W 3
+#define MASK_X 1
+#define MASK_Y 2
+#define MASK_Z 4
+#define MASK_W 8
+#define MASK_ALL (MASK_X|MASK_Y|MASK_Z|MASK_W)
+#define DEF_SCALE NV40_FP_OP_DST_SCALE_1X
+#define DEF_CTEST NV40_FP_OP_COND_TR
+#include "nv40_shader.h"
+
+#define swz(s,x,y,z,w) nv40_sr_swz((s), SWZ_##x, SWZ_##y, SWZ_##z, SWZ_##w)
+#define neg(s) nv40_sr_neg((s))
+#define abs(s) nv40_sr_abs((s))
+#define scale(s,v) nv40_sr_scale((s), NV40_FP_OP_DST_SCALE_##v)
+
+static uint32_t
+passthrough_fp_data[] = {
+       0x01403e81, 0x1c9dc801, 0x0001c800, 0x3fe1c800
+};
+
+static struct nv40_fragment_program
+passthrough_fp = {
+       .pipe = NULL,
+       .translated = TRUE,
+       .insn = passthrough_fp_data,
+       .insn_len = sizeof(passthrough_fp_data) / sizeof(uint32_t),
+       .buffer = NULL,
+       .uses_kil = 0,
+       .num_regs = 2,
+};
+
+struct nv40_fpc {
+       struct nv40_fragment_program *fp;
+
+       uint attrib_map[PIPE_MAX_SHADER_INPUTS];
+
+       int high_temp;
+       int temp_temp_count;
+
+       uint depth_id;
+       uint colour_id;
+
+       boolean inst_has_const;
+       int     inst_const_id;
+};
+
+static INLINE struct nv40_sreg
+nv40_sr_temp(struct nv40_fpc *fpc)
+{
+       int idx;
+
+       idx  = fpc->temp_temp_count++;
+       idx += fpc->high_temp + 1;
+       return nv40_sr(0, NV40_FP_REG_TYPE_TEMP, idx);
+}
+
+#define arith(cc,s,o,d,m,s0,s1,s2) \
+       nv40_fp_arith((cc), (s), NV40_FP_OP_OPCODE_##o, \
+                       (d), (m), (s0), (s1), (s2))
+#define tex(cc,s,o,u,d,m,s0,s1,s2) \
+       nv40_fp_tex((cc), (s), NV40_FP_OP_OPCODE_##o, (u), \
+                   (d), (m), (s0), none, none)
+#define temp(fpc) nv40_sr_temp((fpc))
+
+static void
+emit_src(struct nv40_fpc *fpc, uint32_t *hw, int pos, struct nv40_sreg src)
+{
+       uint32_t sr = 0;
+
+       sr |= (src.type << NV40_FP_REG_TYPE_SHIFT);
+       if (src.type == NV40_FP_REG_TYPE_INPUT) {
+               hw[0] |= (src.index << NV40_FP_OP_INPUT_SRC_SHIFT);
+       } else
+       if (src.type == NV40_FP_REG_TYPE_CONST) {
+               fpc->inst_has_const = TRUE;
+       } else
+       if (src.type == NV40_FP_REG_TYPE_TEMP) {
+               sr |= (src.index << NV40_FP_REG_SRC_SHIFT);
+       }
+
+       if (src.negate)
+               sr |= NV40_FP_REG_NEGATE;
+
+       if (src.abs)
+               hw[1] |= (1 << (29 + pos));
+
+       sr |= ((src.swz[0] << NV40_FP_REG_SWZ_X_SHIFT) |
+              (src.swz[1] << NV40_FP_REG_SWZ_Y_SHIFT) |
+              (src.swz[2] << NV40_FP_REG_SWZ_Z_SHIFT) |
+              (src.swz[3] << NV40_FP_REG_SWZ_W_SHIFT));
+
+       hw[pos + 1] |= sr;
+}
+
+static void
+emit_dst(struct nv40_fpc *fpc, uint32_t *hw, struct nv40_sreg dst)
+{
+       struct nv40_fragment_program *fp = fpc->fp;
+
+       if (dst.output) {
+               if (dst.index == 1) {
+                       fp->writes_depth = 1;
+               } else {
+                       hw[0] |= NV40_FP_OP_UNK0_7;
+               }
+       } else {
+               if (fp->num_regs < (dst.index + 1))
+                       fp->num_regs = dst.index + 1;
+       }
+       hw[0] |= (dst.index << NV40_FP_OP_OUT_REG_SHIFT);
+}
+
+static void
+nv40_fp_arith(struct nv40_fpc *fpc, int sat, int op,
+             struct nv40_sreg dst, int mask,
+             struct nv40_sreg s0, struct nv40_sreg s1, struct nv40_sreg s2)
+{
+       struct nv40_fragment_program *fp = fpc->fp;
+       uint32_t *hw = &fp->insn[fp->insn_len];
+
+       fpc->inst_has_const = FALSE;
+
+       if (op == NV40_FP_OP_OPCODE_KIL)
+               fp->uses_kil = TRUE;
+       hw[0] |= (op << NV40_FP_OP_OPCODE_SHIFT);
+       hw[0] |= (mask << NV40_FP_OP_OUTMASK_SHIFT);
+       hw[2] |= (dst.dst_scale << NV40_FP_OP_DST_SCALE_SHIFT);
+
+       if (sat)
+               hw[0] |= NV40_FP_OP_OUT_SAT;
+
+       if (dst.cc_update)
+               hw[0] |= NV40_FP_OP_COND_WRITE_ENABLE;
+       hw[1] |= (dst.cc_test << NV40_FP_OP_COND_SHIFT);
+       hw[1] |= ((dst.cc_swz[0] << NV40_FP_OP_COND_SWZ_X_SHIFT) |
+                 (dst.cc_swz[1] << NV40_FP_OP_COND_SWZ_Y_SHIFT) |
+                 (dst.cc_swz[2] << NV40_FP_OP_COND_SWZ_Z_SHIFT) |
+                 (dst.cc_swz[3] << NV40_FP_OP_COND_SWZ_W_SHIFT));
+
+       emit_dst(fpc, hw, dst);
+       emit_src(fpc, hw, 0, s0);
+       emit_src(fpc, hw, 1, s1);
+       emit_src(fpc, hw, 2, s2);
+
+       fp->insn_len += 4;
+       if (fpc->inst_has_const) {
+               fp->consts[fp->num_consts].pipe_id = fpc->inst_const_id;
+               fp->consts[fp->num_consts].hw_id = fp->insn_len;
+               fp->num_consts++;
+               fp->insn_len += 4;
+       }
+}
+
+static void
+nv40_fp_tex(struct nv40_fpc *fpc, int sat, int op, int unit,
+           struct nv40_sreg dst, int mask,
+           struct nv40_sreg s0, struct nv40_sreg s1, struct nv40_sreg s2)
+{
+       struct nv40_fragment_program *fp = fpc->fp;
+       uint32_t *hw = &fp->insn[fp->insn_len];
+
+       nv40_fp_arith(fpc, sat, op, dst, mask, s0, s1, s2);
+       hw[0] |= (unit << NV40_FP_OP_TEX_UNIT_SHIFT);
+}
+
+static INLINE struct nv40_sreg
+tgsi_src(struct nv40_fpc *fpc, const struct tgsi_full_src_register *fsrc)
+{
+       struct nv40_sreg src;
+       uint type, index;
+
+       switch (fsrc->SrcRegister.File) {
+       case TGSI_FILE_INPUT:
+               type   = NV40_FP_REG_TYPE_INPUT;
+               index  = fpc->attrib_map[fsrc->SrcRegister.Index];
+               break;
+       case TGSI_FILE_CONSTANT:
+               type   = NV40_FP_REG_TYPE_CONST;
+               index  = fsrc->SrcRegister.Index;
+               break;
+       case TGSI_FILE_TEMPORARY:
+               type   = NV40_FP_REG_TYPE_TEMP;
+               index  = fsrc->SrcRegister.Index + 1;
+               if (fpc->high_temp < index)
+                       fpc->high_temp = index;
+               break;
+       default:
+               NOUVEAU_ERR("bad src file\n");
+               break;
+       }
+
+       src = nv40_sr(0, type, index);
+       src.abs = fsrc->SrcRegisterExtMod.Absolute;
+       src.negate = fsrc->SrcRegister.Negate;
+       src.swz[0] = fsrc->SrcRegister.SwizzleX;
+       src.swz[1] = fsrc->SrcRegister.SwizzleY;
+       src.swz[2] = fsrc->SrcRegister.SwizzleZ;
+       src.swz[3] = fsrc->SrcRegister.SwizzleW;
+       return src;
+}
+
+static INLINE struct nv40_sreg
+tgsi_dst(struct nv40_fpc *fpc, const struct tgsi_full_dst_register *fdst) {
+       int out, idx;
+
+       switch (fdst->DstRegister.File) {
+       case TGSI_FILE_OUTPUT:
+               out = 1;
+               if (fdst->DstRegister.Index == fpc->colour_id)
+                       idx = 0;
+               else
+                       idx = 1;
+               break;
+       case TGSI_FILE_TEMPORARY:
+               out = 0;
+               idx = fdst->DstRegister.Index + 1;
+               if (fpc->high_temp < idx)
+                       fpc->high_temp = idx;
+               break;
+       case TGSI_FILE_NULL:
+               break;
+       default:
+               NOUVEAU_ERR("bad dst file %d\n", fdst->DstRegister.File);
+               break;
+       }
+
+       return nv40_sr(out, NV40_FP_REG_TYPE_TEMP, idx);
+}
+
+static INLINE int
+tgsi_mask(uint tgsi)
+{
+       int mask = 0;
+
+       if (tgsi & TGSI_WRITEMASK_X) mask |= MASK_X;
+       if (tgsi & TGSI_WRITEMASK_Y) mask |= MASK_Y;
+       if (tgsi & TGSI_WRITEMASK_Z) mask |= MASK_Z;
+       if (tgsi & TGSI_WRITEMASK_W) mask |= MASK_W;
+       return mask;
+}
+
+static boolean
+nv40_fragprog_parse_instruction(struct nv40_fpc *fpc,
+                               const struct tgsi_full_instruction *finst)
+{
+       struct nv40_sreg src[3], dst, tmp;
+       struct nv40_sreg none = nv40_sr(0, NV40_FP_REG_TYPE_INPUT, 0);
+       int mask, sat, unit;
+       int ai = -1, ci = -1;
+       int i;
+
+       if (finst->Instruction.Opcode == TGSI_OPCODE_RET)
+               return TRUE;
+
+       fpc->temp_temp_count = 0;
+       for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
+               const struct tgsi_full_src_register *fsrc;
+
+               fsrc = &finst->FullSrcRegisters[i];
+               if (fsrc->SrcRegister.File == TGSI_FILE_TEMPORARY) {
+                       src[i] = tgsi_src(fpc, fsrc);
+               }
+       }
+
+       for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
+               const struct tgsi_full_src_register *fsrc;
+
+               fsrc = &finst->FullSrcRegisters[i];
+               switch (fsrc->SrcRegister.File) {
+               case TGSI_FILE_INPUT:
+                       if (ai == -1 || ai == fsrc->SrcRegister.Index) {
+                               ai = fsrc->SrcRegister.Index;
+                               src[i] = tgsi_src(fpc, fsrc);
+                       } else {
+                               NOUVEAU_MSG("extra src attr %d\n",
+                                        fsrc->SrcRegister.Index);
+                               src[i] = temp(fpc);
+                               arith(fpc, 0, MOV, src[i], MASK_ALL,
+                                     tgsi_src(fpc, fsrc), none, none);
+                       }
+                       break;
+               case TGSI_FILE_CONSTANT:
+                       if (ci == -1 || ci == fsrc->SrcRegister.Index) {
+                               ci = fsrc->SrcRegister.Index;
+                               src[i] = tgsi_src(fpc, fsrc);
+                       } else {
+                               src[i] = temp(fpc);
+                               arith(fpc, 0, MOV, src[i], MASK_ALL,
+                                     tgsi_src(fpc, fsrc), none, none);
+                       }
+                       break;
+               case TGSI_FILE_TEMPORARY:
+                       /* handled above */
+                       break;
+               case TGSI_FILE_SAMPLER:
+                       unit = fsrc->SrcRegister.Index;
+                       break;
+               default:
+                       NOUVEAU_ERR("bad src file\n");
+                       return FALSE;
+               }
+       }
+
+       dst  = tgsi_dst(fpc, &finst->FullDstRegisters[0]);
+       mask = tgsi_mask(finst->FullDstRegisters[0].DstRegister.WriteMask);
+       sat  = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE);
+
+       switch (finst->Instruction.Opcode) {
+       case TGSI_OPCODE_ABS:
+               arith(fpc, sat, MOV, dst, mask, abs(src[0]), none, none);
+               break;
+       case TGSI_OPCODE_ADD:
+               arith(fpc, sat, ADD, dst, mask, src[0], src[1], none);
+               break;
+       case TGSI_OPCODE_CMP:
+               tmp = temp(fpc);
+               arith(fpc, sat, MOV, dst, mask, src[2], none, none);
+               tmp.cc_update = 1;
+               arith(fpc, 0, MOV, tmp, 0xf, src[0], none, none);
+               dst.cc_test = NV40_VP_INST_COND_LT;
+               arith(fpc, sat, MOV, dst, mask, src[1], none, none);
+               break;
+       case TGSI_OPCODE_COS:
+               arith(fpc, sat, COS, dst, mask, src[0], none, none);
+               break;
+       case TGSI_OPCODE_DP3:
+               arith(fpc, sat, DP3, dst, mask, src[0], src[1], none);
+               break;
+       case TGSI_OPCODE_DP4:
+               arith(fpc, sat, DP4, dst, mask, src[0], src[1], none);
+               break;
+       case TGSI_OPCODE_DPH:
+               tmp = temp(fpc);
+               arith(fpc, 0, DP3, tmp, MASK_X, src[0], src[1], none);
+               arith(fpc, sat, ADD, dst, mask, swz(tmp, X, X, X, X),
+                     swz(src[1], W, W, W, W), none);
+               break;
+       case TGSI_OPCODE_DST:
+               arith(fpc, sat, DST, dst, mask, src[0], src[1], none);
+               break;
+       case TGSI_OPCODE_EX2:
+               arith(fpc, sat, EX2, dst, mask, src[0], none, none);
+               break;
+       case TGSI_OPCODE_FLR:
+               arith(fpc, sat, FLR, dst, mask, src[0], none, none);
+               break;
+       case TGSI_OPCODE_FRC:
+               arith(fpc, sat, FRC, dst, mask, src[0], none, none);
+               break;
+       case TGSI_OPCODE_KIL:
+       case TGSI_OPCODE_KILP:
+               /*XXX: Which is NV, which is ARB kil? ARB implemented here.
+                *XXX: Don't need temp, can update CC0 without writing dst
+                */
+               tmp = temp(fpc);
+               tmp.cc_update = 1;
+               arith(fpc, 0, MOV, tmp, MASK_ALL, src[0], none, none);
+               dst.cc_test = NV40_FP_OP_COND_LT;
+               arith(fpc, 0, KIL, dst, 0, none, none, none);
+               break;
+       case TGSI_OPCODE_LG2:
+               arith(fpc, sat, LG2, dst, mask, src[0], none, none);
+               break;
+//     case TGSI_OPCODE_LIT:
+       case TGSI_OPCODE_LRP:
+               tmp = temp(fpc);
+               arith(fpc, 0, MAD, tmp, mask, neg(src[0]), src[2], src[2]);
+               arith(fpc, sat, MAD, dst, mask, src[0], src[1], tmp);
+               break;
+       case TGSI_OPCODE_MAD:
+               arith(fpc, sat, MAD, dst, mask, src[0], src[1], src[2]);
+               break;
+       case TGSI_OPCODE_MAX:
+               arith(fpc, sat, MAX, dst, mask, src[0], src[1], none);
+               break;
+       case TGSI_OPCODE_MIN:
+               arith(fpc, sat, MIN, dst, mask, src[0], src[1], none);
+               break;
+       case TGSI_OPCODE_MOV:
+               arith(fpc, sat, MOV, dst, mask, src[0], none, none);
+               break;
+       case TGSI_OPCODE_MUL:
+               arith(fpc, sat, MUL, dst, mask, src[0], src[1], none);
+               break;
+       case TGSI_OPCODE_POW:
+               tmp = temp(fpc);
+               arith(fpc, 0, LG2, tmp, MASK_X,
+                     swz(src[0], X, X, X, X), none, none);
+               arith(fpc, 0, MUL, tmp, MASK_X, swz(tmp, X, X, X, X),
+                     swz(src[1], X, X, X, X), none);
+               arith(fpc, sat, EX2, dst, mask,
+                     swz(tmp, X, X, X, X), none, none);
+               break;
+       case TGSI_OPCODE_RCP:
+               arith(fpc, sat, RCP, dst, mask, src[0], none, none);
+               break;
+       case TGSI_OPCODE_RFL:
+               tmp = temp(fpc);
+               arith(fpc, 0, DP3, tmp, MASK_X, src[0], src[0], none);
+               arith(fpc, 0, DP3, tmp, MASK_Y, src[0], src[1], none);
+               arith(fpc, 0, DIV, scale(tmp, 2X), MASK_Z,
+                     swz(tmp, Y, Y, Y, Y), swz(tmp, X, X, X, X), none);
+               arith(fpc, sat, MAD, dst, mask,
+                     swz(tmp, Z, Z, Z, Z), src[0], neg(src[1]));
+               break;
+       case TGSI_OPCODE_RSQ:
+               tmp = temp(fpc);
+               arith(fpc, 0, LG2, scale(tmp, INV_2X), MASK_X,
+                     abs(swz(src[0], X, X, X, X)), none, none);
+               arith(fpc, sat, EX2, dst, mask,
+                     neg(swz(tmp, X, X, X, X)), none, none);
+               break;
+       case TGSI_OPCODE_SCS:
+               if (mask & MASK_X) {
+                       arith(fpc, sat, COS, dst, MASK_X,
+                             swz(src[0], X, X, X, X), none, none);
+               }
+               if (mask & MASK_Y) {
+                       arith(fpc, sat, SIN, dst, MASK_Y,
+                             swz(src[0], X, X, X, X), none, none);
+               }
+               break;
+       case TGSI_OPCODE_SIN:
+               arith(fpc, sat, SIN, dst, mask, src[0], none, none);
+               break;
+       case TGSI_OPCODE_SGE:
+               arith(fpc, sat, SGE, dst, mask, src[0], src[1], none);
+               break;
+       case TGSI_OPCODE_SLT:
+               arith(fpc, sat, SLT, dst, mask, src[0], src[1], none);
+               break;
+       case TGSI_OPCODE_SUB:
+               arith(fpc, sat, ADD, dst, mask, src[0], neg(src[1]), none);
+               break;
+       case TGSI_OPCODE_TEX:
+               tex(fpc, sat, TEX, unit, dst, mask, src[0], none, none);
+               break;
+       case TGSI_OPCODE_TXB:
+               tex(fpc, sat, TXB, unit, dst, mask, src[0], none, none);
+               break;
+#if 0 /* XXX: reimplement on top of TEX */
+       case TGSI_OPCODE_TXP:
+               tex(fpc, sat, TXP, unit, dst, mask, src[0], none, none);
+               break;
+#endif
+       case TGSI_OPCODE_XPD:
+               tmp = temp(fpc);
+               arith(fpc, 0, MUL, tmp, mask,
+                     swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
+               arith(fpc, sat, MAD, dst, (mask & ~MASK_W),
+                     swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
+                     neg(tmp));
+               break;
+       default:
+               NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
+               return FALSE;
+       }
+
+       return TRUE;
+}
+
+static boolean
+nv40_fragprog_parse_decl_attrib(struct nv40_fpc *fpc,
+                               const struct tgsi_full_declaration *fdec)
+{
+       int hw;
+
+       switch (fdec->Semantic.SemanticName) {
+       case TGSI_SEMANTIC_POSITION:
+               hw = NV40_FP_OP_INPUT_SRC_POSITION;
+               break;
+       case TGSI_SEMANTIC_COLOR:
+               if (fdec->Semantic.SemanticIndex == 0) {
+                       hw = NV40_FP_OP_INPUT_SRC_COL0;
+               } else
+               if (fdec->Semantic.SemanticIndex == 1) {
+                       hw = NV40_FP_OP_INPUT_SRC_COL1;
+               } else {
+                       NOUVEAU_ERR("bad colour semantic index\n");
+                       return FALSE;
+               }
+               break;
+       case TGSI_SEMANTIC_FOG:
+               hw = NV40_FP_OP_INPUT_SRC_FOGC;
+               break;
+       case TGSI_SEMANTIC_GENERIC:
+               if (fdec->Semantic.SemanticIndex <= 7) {
+                       hw = NV40_FP_OP_INPUT_SRC_TC(fdec->Semantic.
+                                                    SemanticIndex);
+               } else {
+                       NOUVEAU_ERR("bad generic semantic index\n");
+                       return FALSE;
+               }
+               break;
+       default:
+               NOUVEAU_ERR("bad input semantic\n");
+               return FALSE;
+       }
+
+       fpc->attrib_map[fdec->u.DeclarationRange.First] = hw;
+       return TRUE;
+}
+
+static boolean
+nv40_fragprog_parse_decl_output(struct nv40_fpc *fpc,
+                               const struct tgsi_full_declaration *fdec)
+{
+       switch (fdec->Semantic.SemanticName) {
+       case TGSI_SEMANTIC_POSITION:
+               fpc->depth_id = fdec->u.DeclarationRange.First;
+               break;
+       case TGSI_SEMANTIC_COLOR:
+               fpc->colour_id = fdec->u.DeclarationRange.First;
+               break;
+       default:
+               NOUVEAU_ERR("bad output semantic\n");
+               return FALSE;
+       }
+
+       return TRUE;
+}
+
+void
+nv40_fragprog_translate(struct nv40_context *nv40,
+                       struct nv40_fragment_program *fp)
+{
+       struct tgsi_parse_context parse;
+       struct nv40_fpc *fpc = NULL;
+       int i;
+
+       fpc = calloc(1, sizeof(struct nv40_fpc));
+       if (!fpc)
+               return;
+       fp->insn = calloc(1, 128*4*sizeof(uint32_t));
+       fpc->fp = fp;
+       fpc->high_temp = -1;
+       fp->num_regs = 2;
+
+       tgsi_parse_init(&parse, fp->pipe->tokens);
+
+       while (!tgsi_parse_end_of_tokens(&parse)) {
+               tgsi_parse_token(&parse);
+
+               switch (parse.FullToken.Token.Type) {
+               case TGSI_TOKEN_TYPE_DECLARATION:
+               {
+                       const struct tgsi_full_declaration *fdec;
+                       fdec = &parse.FullToken.FullDeclaration;
+                       switch (fdec->Declaration.File) {
+                       case TGSI_FILE_INPUT:
+                               if (!nv40_fragprog_parse_decl_attrib(fpc, fdec))
+                                       goto out_err;
+                               break;
+                       case TGSI_FILE_OUTPUT:
+                               if (!nv40_fragprog_parse_decl_output(fpc, fdec))
+                                       goto out_err;
+                               break;
+                       default:
+                               break;
+                       }
+               }
+                       break;
+               case TGSI_TOKEN_TYPE_IMMEDIATE:
+                       break;
+               case TGSI_TOKEN_TYPE_INSTRUCTION:
+               {
+                       const struct tgsi_full_instruction *finst;
+
+                       finst = &parse.FullToken.FullInstruction;
+                       if (!nv40_fragprog_parse_instruction(fpc, finst))
+                               goto out_err;
+               }
+                       break;
+               default:
+                       break;
+               }
+       }
+
+       if (fpc->inst_has_const == FALSE)
+               fp->insn[fp->insn_len - 4] |= 0x00000001;
+       else
+               fp->insn[fp->insn_len - 8] |= 0x00000001;
+       fp->insn[fp->insn_len++]  = 0x00000001;
+
+       fp->translated = TRUE;
+       fp->on_hw = FALSE;
+out_err:
+       tgsi_parse_free(&parse);
+       free(fpc);
+}
+
+void
+nv40_fragprog_bind(struct nv40_context *nv40, struct nv40_fragment_program *fp)
+{
+       struct pipe_winsys *ws = nv40->pipe.winsys;
+       uint32_t fp_control;
+
+       if (!fp->translated) {
+               NOUVEAU_ERR("fragprog invalid, using passthrough shader\n");
+               fp = &passthrough_fp;
+       }
+
+       if (!fp->on_hw) {
+               if (!fp->buffer)
+                       fp->buffer = ws->buffer_create(ws, 0x100);
+
+               nv40->pipe.winsys->buffer_data(nv40->pipe.winsys, fp->buffer,
+                                              fp->insn_len * sizeof(uint32_t),
+                                              fp->insn,
+                                              PIPE_BUFFER_USAGE_PIXEL);
+               fp->on_hw = TRUE;
+       }
+
+       fp_control = fp->num_regs << NV40TCL_FP_CONTROL_TEMP_COUNT_SHIFT;
+       if (fp->uses_kil)
+               fp_control |= NV40TCL_FP_CONTROL_KIL;
+       if (fp->writes_depth)
+               fp_control |= 0xe;
+
+       BEGIN_RING(curie, NV40TCL_FP_ADDRESS, 1);
+       OUT_RELOC (fp->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART |
+                  NOUVEAU_BO_RD | NOUVEAU_BO_LOW | NOUVEAU_BO_OR,
+                  NV40TCL_FP_ADDRESS_DMA0, NV40TCL_FP_ADDRESS_DMA1);
+       BEGIN_RING(curie, NV40TCL_FP_CONTROL, 1);
+       OUT_RING  (fp_control);
+
+       nv40->fragprog.active_fp = fp;
+}
+

diff --git a/src/mesa/pipe/nv40/nv40_miptree.c b/src/mesa/pipe/nv40/nv40_miptree.c
new file mode 100644 (file)
index 0000000..6b85823
--- /dev/null
+++ b/src/mesa/pipe/nv40/nv40_miptree.c
@@ -0,0 +1,60 @@
+#include "pipe/p_state.h"
+#include "pipe/p_defines.h"
+#include "pipe/p_util.h"
+
+#include "nv40_context.h"
+
+boolean
+nv40_miptree_layout(struct pipe_context *pipe, struct pipe_mipmap_tree *mt)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       uint width, height, depth, offset;
+       boolean swizzled = FALSE;
+       int l;
+
+       mt->pitch = mt->width0;
+       mt->total_height = 0;
+
+       width = mt->width0;
+       height = mt->height0;
+       depth = mt->depth0;
+       offset = 0;
+       for (l = mt->first_level; l <= mt->last_level; l++) {
+               uint pitch, f;
+
+               mt->level[l].width = width;
+               mt->level[l].height = height;
+               mt->level[l].depth = depth;
+               mt->level[l].level_offset = offset;
+
+               if (!swizzled)
+                       pitch = mt->width0;
+               else
+                       pitch = width;
+
+               if (mt->target == PIPE_TEXTURE_CUBE)
+                       mt->level[l].nr_images = 6;
+               else
+               if (mt->target == PIPE_TEXTURE_3D)
+                       mt->level[l].nr_images = 3;
+               else
+                       mt->level[l].nr_images = 1;
+               mt->level[l].image_offset =
+                       malloc(mt->level[l].nr_images * sizeof(unsigned));
+
+               for (f = 0; f < mt->level[l].nr_images; f++) {
+                       mt->level[l].image_offset[f] =
+                               (offset - mt->level[l].level_offset) / mt->cpp;
+                       mt->total_height += height;
+
+                       offset += (pitch * mt->cpp * height);
+               }
+
+               width  = MAX2(1, width  >> 1);
+               height = MAX2(1, height >> 1);
+               depth  = MAX2(1, depth  >> 1);
+       }
+
+       return TRUE;
+}
+

diff --git a/src/mesa/pipe/nv40/nv40_query.c b/src/mesa/pipe/nv40/nv40_query.c
new file mode 100644 (file)
index 0000000..efd81e6
--- /dev/null
+++ b/src/mesa/pipe/nv40/nv40_query.c
@@ -0,0 +1,98 @@
+#include "pipe/p_context.h"
+
+#include "nv40_context.h"
+#include "nv40_dma.h"
+
+static uint
+nv40_query_object_find(struct nv40_context *nv40, struct pipe_query_object *q)
+{
+       int id;
+
+       for (id = 0; id < nv40->num_query_objects; id++) {
+               if (nv40->query_objects[id] == q)
+                       return id;
+       }
+
+       return -1;
+}
+
+void
+nv40_query_begin(struct pipe_context *pipe, struct pipe_query_object *q)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       int id;
+
+       assert(q->type == PIPE_QUERY_OCCLUSION_COUNTER);
+
+       id = nv40_query_object_find(nv40, NULL);
+       assert(id >= 0);
+       nv40->query_objects[id] = q;
+
+       nv40->nvws->notifier_reset(nv40->query, id);
+       q->ready = 0;
+
+       BEGIN_RING(curie, NV40TCL_QUERY_RESET, 1);
+       OUT_RING  (1);
+       BEGIN_RING(curie, NV40TCL_QUERY_UNK17CC, 1);
+       OUT_RING  (1);
+}
+
+static void
+nv40_query_update(struct pipe_context *pipe, struct pipe_query_object *q)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       int id;
+
+       id = nv40_query_object_find(nv40, q);
+       assert(id >= 0);
+
+       if (nv40->nvws->notifier_status(nv40->query, id) == 0) {
+               q->ready = 1;
+               q->count = nv40->nvws->notifier_retval(nv40->query, id);
+               nv40->query_objects[id] = NULL;
+       }
+}
+
+void
+nv40_query_end(struct pipe_context *pipe, struct pipe_query_object *q)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       int id;
+
+       id = nv40_query_object_find(nv40, q);
+       assert(id >= 0);
+
+       BEGIN_RING(curie, NV40TCL_QUERY_GET, 1);
+       OUT_RING  ((0x01 << NV40TCL_QUERY_GET_UNK24_SHIFT) |
+                  ((id * 32) << NV40TCL_QUERY_GET_OFFSET_SHIFT));
+       FIRE_RING ();
+
+       /*XXX: Some apps spin waiting for GL_QUERY_RESULT_AVAILABLE_ARB.
+        *     Core mesa won't ask the driver to update the query object's
+        *     status in this case, so the app waits forever.. fix this some
+        *     day.
+        */
+#if 0
+       nv40_query_update(pipe, q);
+#else
+       nv40_query_wait(pipe, q);
+#endif
+}
+
+void
+nv40_query_wait(struct pipe_context *pipe, struct pipe_query_object *q)
+{
+       nv40_query_update(pipe, q);
+       if (!q->ready) {
+               struct nv40_context *nv40 = (struct nv40_context *)pipe;
+               int id;
+               
+               id = nv40_query_object_find(nv40, q);
+               assert(id >= 0);
+
+               nv40->nvws->notifier_wait(nv40->query, id, 0, 0);
+               nv40_query_update(pipe, q);
+               assert(q->ready);
+       }
+}
+

diff --git a/src/mesa/pipe/nv40/nv40_region.c b/src/mesa/pipe/nv40/nv40_region.c
new file mode 100644 (file)
index 0000000..f62bf89
--- /dev/null
+++ b/src/mesa/pipe/nv40/nv40_region.c
@@ -0,0 +1,85 @@
+#include "pipe/p_defines.h"
+#include "pipe/p_winsys.h"
+
+#include "nv40_context.h"
+#include "nv40_dma.h"
+
+static ubyte *
+nv40_region_map(struct pipe_context *pipe, struct pipe_region *region)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       struct pipe_winsys *ws = nv40->pipe.winsys;
+
+       if (!region->map_refcount++) {
+               region->map = ws->buffer_map(ws, region->buffer,
+                                            PIPE_BUFFER_FLAG_WRITE |
+                                            PIPE_BUFFER_FLAG_READ);
+       }
+
+       return region->map;
+}
+
+static void
+nv40_region_unmap(struct pipe_context *pipe, struct pipe_region *region)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       struct pipe_winsys *ws = nv40->pipe.winsys;
+
+       if (!--region->map_refcount) {
+               ws->buffer_unmap(ws, region->buffer);
+               region->map = NULL;
+       }
+}
+
+static void
+nv40_region_data(struct pipe_context *pipe,
+              struct pipe_region *dst,
+              unsigned dst_offset,
+              unsigned dstx, unsigned dsty,
+              const void *src, unsigned src_pitch,
+              unsigned srcx, unsigned srcy, unsigned width, unsigned height)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       struct nouveau_winsys *nvws = nv40->nvws;
+
+       nvws->region_data(nvws->nv, dst, dst_offset, dstx, dsty,
+                         src, src_pitch, srcx, srcy, width, height);
+}
+
+
+static void
+nv40_region_copy(struct pipe_context *pipe, struct pipe_region *dst,
+                unsigned dst_offset, unsigned dstx, unsigned dsty,
+                struct pipe_region *src, unsigned src_offset,
+                unsigned srcx, unsigned srcy, unsigned width, unsigned height)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       struct nouveau_winsys *nvws = nv40->nvws;
+
+       nvws->region_copy(nvws->nv, dst, dst_offset, dstx, dsty,
+                         src, src_offset, srcx, srcy, width, height);
+}
+
+static void
+nv40_region_fill(struct pipe_context *pipe,
+                struct pipe_region *dst, unsigned dst_offset,
+                unsigned dstx, unsigned dsty,
+                unsigned width, unsigned height, unsigned value)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       struct nouveau_winsys *nvws = nv40->nvws;
+
+       nvws->region_fill(nvws->nv, dst, dst_offset, dstx, dsty,
+                         width, height, value);
+}
+
+void
+nv40_init_region_functions(struct nv40_context *nv40)
+{
+       nv40->pipe.region_map = nv40_region_map;
+       nv40->pipe.region_unmap = nv40_region_unmap;
+       nv40->pipe.region_data = nv40_region_data;
+       nv40->pipe.region_copy = nv40_region_copy;
+       nv40->pipe.region_fill = nv40_region_fill;
+}
+

diff --git a/src/mesa/pipe/nv40/nv40_shader.h b/src/mesa/pipe/nv40/nv40_shader.h
new file mode 100644 (file)
index 0000000..5b2cf3e
--- /dev/null
+++ b/src/mesa/pipe/nv40/nv40_shader.h
@@ -0,0 +1,546 @@
+#ifndef __NV40_SHADER_H__
+#define __NV40_SHADER_H__
+
+/* Vertex programs instruction set
+ *
+ * The NV40 instruction set is very similar to NV30.  Most fields are in
+ * a slightly different position in the instruction however.
+ *
+ * Merged instructions
+ *     In some cases it is possible to put two instructions into one opcode
+ *     slot.  The rules for when this is OK is not entirely clear to me yet.
+ *
+ *     There are separate writemasks and dest temp register fields for each
+ *     grouping of instructions.  There is however only one field with the
+ *     ID of a result register.  Writing to temp/result regs is selected by
+ *     setting VEC_RESULT/SCA_RESULT.
+ *
+ * Temporary registers
+ *     The source/dest temp register fields have been extended by 1 bit, to
+ *     give a total of 32 temporary registers.
+ *
+ * Relative Addressing
+ *     NV40 can use an address register to index into vertex attribute regs.
+ *     This is done by putting the offset value into INPUT_SRC and setting
+ *     the INDEX_INPUT flag.
+ *
+ * Conditional execution (see NV_vertex_program{2,3} for details)
+ *     There is a second condition code register on NV40, it's use is enabled
+ *     by setting the COND_REG_SELECT_1 flag.
+ *
+ * Texture lookup
+ *     TODO
+ */
+
+/* ---- OPCODE BITS 127:96 / data DWORD 0 --- */
+#define NV40_VP_INST_VEC_RESULT                                        (1 << 30)
+/* uncertain.. */
+#define NV40_VP_INST_COND_UPDATE_ENABLE                        ((1 << 14)|1<<29)
+/* use address reg as index into attribs */
+#define NV40_VP_INST_INDEX_INPUT                                       (1 << 27)
+#define NV40_VP_INST_COND_REG_SELECT_1                                 (1 << 25)
+#define NV40_VP_INST_ADDR_REG_SELECT_1                                 (1 << 24)
+#define NV40_VP_INST_SRC2_ABS                                          (1 << 23)
+#define NV40_VP_INST_SRC1_ABS                                          (1 << 22)
+#define NV40_VP_INST_SRC0_ABS                                          (1 << 21)
+#define NV40_VP_INST_VEC_DEST_TEMP_SHIFT                                      15
+#define NV40_VP_INST_VEC_DEST_TEMP_MASK                             (0x1F << 15)
+#define NV40_VP_INST_COND_TEST_ENABLE                                  (1 << 13)
+#define NV40_VP_INST_COND_SHIFT                                               10
+#define NV40_VP_INST_COND_MASK                                       (0x7 << 10)
+#    define NV40_VP_INST_COND_FL                                               0
+#    define NV40_VP_INST_COND_LT                                               1
+#    define NV40_VP_INST_COND_EQ                                               2
+#    define NV40_VP_INST_COND_LE                                               3
+#    define NV40_VP_INST_COND_GT                                               4
+#    define NV40_VP_INST_COND_NE                                               5
+#    define NV40_VP_INST_COND_GE                                               6
+#    define NV40_VP_INST_COND_TR                                               7
+#define NV40_VP_INST_COND_SWZ_X_SHIFT                                          8
+#define NV40_VP_INST_COND_SWZ_X_MASK                                    (3 << 8)
+#define NV40_VP_INST_COND_SWZ_Y_SHIFT                                          6
+#define NV40_VP_INST_COND_SWZ_Y_MASK                                    (3 << 6)
+#define NV40_VP_INST_COND_SWZ_Z_SHIFT                                          4
+#define NV40_VP_INST_COND_SWZ_Z_MASK                                    (3 << 4)
+#define NV40_VP_INST_COND_SWZ_W_SHIFT                                          2
+#define NV40_VP_INST_COND_SWZ_W_MASK                                    (3 << 2)
+#define NV40_VP_INST_COND_SWZ_ALL_SHIFT                                        2
+#define NV40_VP_INST_COND_SWZ_ALL_MASK                               (0xFF << 2)
+#define NV40_VP_INST_ADDR_SWZ_SHIFT                                            0
+#define NV40_VP_INST_ADDR_SWZ_MASK                                   (0x03 << 0)
+#define NV40_VP_INST0_KNOWN ( \
+                NV40_VP_INST_INDEX_INPUT | \
+                NV40_VP_INST_COND_REG_SELECT_1 | \
+                NV40_VP_INST_ADDR_REG_SELECT_1 | \
+                NV40_VP_INST_SRC2_ABS | \
+                NV40_VP_INST_SRC1_ABS | \
+                NV40_VP_INST_SRC0_ABS | \
+                NV40_VP_INST_VEC_DEST_TEMP_MASK | \
+                NV40_VP_INST_COND_TEST_ENABLE | \
+                NV40_VP_INST_COND_MASK | \
+                NV40_VP_INST_COND_SWZ_ALL_MASK | \
+                NV40_VP_INST_ADDR_SWZ_MASK)
+
+/* ---- OPCODE BITS 95:64 / data DWORD 1 --- */
+#define NV40_VP_INST_VEC_OPCODE_SHIFT                                         22
+#define NV40_VP_INST_VEC_OPCODE_MASK                                (0x1F << 22)
+#    define NV40_VP_INST_OP_NOP                                             0x00
+#    define NV40_VP_INST_OP_MOV                                             0x01
+#    define NV40_VP_INST_OP_MUL                                             0x02
+#    define NV40_VP_INST_OP_ADD                                             0x03
+#    define NV40_VP_INST_OP_MAD                                             0x04
+#    define NV40_VP_INST_OP_DP3                                             0x05
+#    define NV40_VP_INST_OP_DP4                                             0x07
+#    define NV40_VP_INST_OP_DPH                                             0x06
+#    define NV40_VP_INST_OP_DST                                             0x08
+#    define NV40_VP_INST_OP_MIN                                             0x09
+#    define NV40_VP_INST_OP_MAX                                             0x0A
+#    define NV40_VP_INST_OP_SLT                                             0x0B
+#    define NV40_VP_INST_OP_SGE                                             0x0C
+#    define NV40_VP_INST_OP_ARL                                             0x0D
+#    define NV40_VP_INST_OP_FRC                                             0x0E
+#    define NV40_VP_INST_OP_FLR                                             0x0F
+#    define NV40_VP_INST_OP_SEQ                                             0x10
+#    define NV40_VP_INST_OP_SFL                                             0x11
+#    define NV40_VP_INST_OP_SGT                                             0x12
+#    define NV40_VP_INST_OP_SLE                                             0x13
+#    define NV40_VP_INST_OP_SNE                                             0x14
+#    define NV40_VP_INST_OP_STR                                             0x15
+#    define NV40_VP_INST_OP_SSG                                             0x16
+#    define NV40_VP_INST_OP_ARR                                             0x17
+#    define NV40_VP_INST_OP_ARA                                             0x18
+#    define NV40_VP_INST_OP_TXWHAT                                          0x19
+#define NV40_VP_INST_SCA_OPCODE_SHIFT                                         27
+#define NV40_VP_INST_SCA_OPCODE_MASK                                (0x1F << 27)
+#    define NV40_VP_INST_OP_RCP                                             0x02
+#    define NV40_VP_INST_OP_RCC                                             0x03
+#    define NV40_VP_INST_OP_RSQ                                             0x04
+#    define NV40_VP_INST_OP_EXP                                             0x05
+#    define NV40_VP_INST_OP_LOG                                             0x06
+#    define NV40_VP_INST_OP_LIT                                             0x07
+#    define NV40_VP_INST_OP_BRA                                             0x09
+#    define NV40_VP_INST_OP_CAL                                             0x0B
+#    define NV40_VP_INST_OP_RET                                             0x0C
+#    define NV40_VP_INST_OP_LG2                                             0x0D
+#    define NV40_VP_INST_OP_EX2                                             0x0E
+#    define NV40_VP_INST_OP_SIN                                             0x0F
+#    define NV40_VP_INST_OP_COS                                             0x10
+#    define NV40_VP_INST_OP_PUSHA                                           0x13
+#    define NV40_VP_INST_OP_POPA                                            0x14
+#define NV40_VP_INST_CONST_SRC_SHIFT                                          12
+#define NV40_VP_INST_CONST_SRC_MASK                                 (0xFF << 12)
+#define NV40_VP_INST_INPUT_SRC_SHIFT                                           8
+#define NV40_VP_INST_INPUT_SRC_MASK                                  (0x0F << 8)
+#    define NV40_VP_INST_IN_POS                                                0
+#    define NV40_VP_INST_IN_WEIGHT                                             1
+#    define NV40_VP_INST_IN_NORMAL                                             2
+#    define NV40_VP_INST_IN_COL0                                               3
+#    define NV40_VP_INST_IN_COL1                                               4
+#    define NV40_VP_INST_IN_FOGC                                               5
+#    define NV40_VP_INST_IN_TC0                                                8
+#    define NV40_VP_INST_IN_TC(n)                                          (8+n)
+#define NV40_VP_INST_SRC0H_SHIFT                                               0
+#define NV40_VP_INST_SRC0H_MASK                                      (0xFF << 0)
+#define NV40_VP_INST1_KNOWN ( \
+                NV40_VP_INST_VEC_OPCODE_MASK | \
+                NV40_VP_INST_SCA_OPCODE_MASK | \
+                NV40_VP_INST_CONST_SRC_MASK  | \
+                NV40_VP_INST_INPUT_SRC_MASK  | \
+                NV40_VP_INST_SRC0H_MASK \
+                )
+
+/* ---- OPCODE BITS 63:32 / data DWORD 2 --- */
+#define NV40_VP_INST_SRC0L_SHIFT                                              23
+#define NV40_VP_INST_SRC0L_MASK                                    (0x1FF << 23)
+#define NV40_VP_INST_SRC1_SHIFT                                                6
+#define NV40_VP_INST_SRC1_MASK                                    (0x1FFFF << 6)
+#define NV40_VP_INST_SRC2H_SHIFT                                               0
+#define NV40_VP_INST_SRC2H_MASK                                      (0x3F << 0)
+#define NV40_VP_INST_IADDRH_SHIFT                                              0
+#define NV40_VP_INST_IADDRH_MASK                                     (0x1F << 0)
+
+/* ---- OPCODE BITS 31:0 / data DWORD 3 --- */
+#define NV40_VP_INST_IADDRL_SHIFT                                             29
+#define NV40_VP_INST_IADDRL_MASK                                       (7 << 29)
+#define NV40_VP_INST_SRC2L_SHIFT                                              21
+#define NV40_VP_INST_SRC2L_MASK                                    (0x7FF << 21)
+#define NV40_VP_INST_SCA_WRITEMASK_SHIFT                                      17
+#define NV40_VP_INST_SCA_WRITEMASK_MASK                              (0xF << 17)
+#    define NV40_VP_INST_SCA_WRITEMASK_X                               (1 << 20)
+#    define NV40_VP_INST_SCA_WRITEMASK_Y                               (1 << 19)
+#    define NV40_VP_INST_SCA_WRITEMASK_Z                               (1 << 18)
+#    define NV40_VP_INST_SCA_WRITEMASK_W                               (1 << 17)
+#define NV40_VP_INST_VEC_WRITEMASK_SHIFT                                      13
+#define NV40_VP_INST_VEC_WRITEMASK_MASK                              (0xF << 13)
+#    define NV40_VP_INST_VEC_WRITEMASK_X                               (1 << 16)
+#    define NV40_VP_INST_VEC_WRITEMASK_Y                               (1 << 15)
+#    define NV40_VP_INST_VEC_WRITEMASK_Z                               (1 << 14)
+#    define NV40_VP_INST_VEC_WRITEMASK_W                               (1 << 13)
+#define NV40_VP_INST_SCA_RESULT                                        (1 << 12)
+#define NV40_VP_INST_SCA_DEST_TEMP_SHIFT                                       7
+#define NV40_VP_INST_SCA_DEST_TEMP_MASK                              (0x1F << 7)
+#define NV40_VP_INST_DEST_SHIFT                                                2
+#define NV40_VP_INST_DEST_MASK                                         (31 << 2)
+#    define NV40_VP_INST_DEST_POS                                              0
+#    define NV40_VP_INST_DEST_COL0                                             1
+#    define NV40_VP_INST_DEST_COL1                                             2
+#    define NV40_VP_INST_DEST_BFC0                                             3
+#    define NV40_VP_INST_DEST_BFC1                                             4
+#    define NV40_VP_INST_DEST_FOGC                                             5
+#    define NV40_VP_INST_DEST_PSZ                                              6
+#    define NV40_VP_INST_DEST_TC0                                              7
+#    define NV40_VP_INST_DEST_TC(n)                                        (7+n)
+#    define NV40_VP_INST_DEST_TEMP                                          0x1F
+#define NV40_VP_INST_INDEX_CONST                                        (1 << 1)
+#define NV40_VP_INST_LAST                                               (1 << 0)
+#define NV40_VP_INST3_KNOWN ( \
+                NV40_VP_INST_SRC2L_MASK |\
+                NV40_VP_INST_SCA_WRITEMASK_MASK |\
+                NV40_VP_INST_VEC_WRITEMASK_MASK |\
+                NV40_VP_INST_SCA_DEST_TEMP_MASK |\
+                NV40_VP_INST_DEST_MASK |\
+                NV40_VP_INST_INDEX_CONST)
+
+/* Useful to split the source selection regs into their pieces */
+#define NV40_VP_SRC0_HIGH_SHIFT                                                9
+#define NV40_VP_SRC0_HIGH_MASK                                        0x0001FE00
+#define NV40_VP_SRC0_LOW_MASK                                         0x000001FF
+#define NV40_VP_SRC2_HIGH_SHIFT                                               11
+#define NV40_VP_SRC2_HIGH_MASK                                        0x0001F800
+#define NV40_VP_SRC2_LOW_MASK                                         0x000007FF
+
+/* Source selection - these are the bits you fill NV40_VP_INST_SRCn with */
+#define NV40_VP_SRC_NEGATE                                             (1 << 16)
+#define NV40_VP_SRC_SWZ_X_SHIFT                                               14
+#define NV40_VP_SRC_SWZ_X_MASK                                         (3 << 14)
+#define NV40_VP_SRC_SWZ_Y_SHIFT                                               12
+#define NV40_VP_SRC_SWZ_Y_MASK                                         (3 << 12)
+#define NV40_VP_SRC_SWZ_Z_SHIFT                                               10
+#define NV40_VP_SRC_SWZ_Z_MASK                                         (3 << 10)
+#define NV40_VP_SRC_SWZ_W_SHIFT                                                8
+#define NV40_VP_SRC_SWZ_W_MASK                                          (3 << 8)
+#define NV40_VP_SRC_SWZ_ALL_SHIFT                                              8
+#define NV40_VP_SRC_SWZ_ALL_MASK                                     (0xFF << 8)
+#define NV40_VP_SRC_TEMP_SRC_SHIFT                                             2
+#define NV40_VP_SRC_TEMP_SRC_MASK                                    (0x1F << 2)
+#define NV40_VP_SRC_REG_TYPE_SHIFT                                             0
+#define NV40_VP_SRC_REG_TYPE_MASK                                       (3 << 0)
+#    define NV40_VP_SRC_REG_TYPE_UNK0                                          0
+#    define NV40_VP_SRC_REG_TYPE_TEMP                                          1
+#    define NV40_VP_SRC_REG_TYPE_INPUT                                         2
+#    define NV40_VP_SRC_REG_TYPE_CONST                                         3
+
+
+/*
+ * Each fragment program opcode appears to be comprised of 4 32-bit values.
+ *
+ *         0 - Opcode, output reg/mask, ATTRIB source
+ *         1 - Source 0
+ *         2 - Source 1
+ *         3 - Source 2
+ *
+ * There appears to be no special difference between result regs and temp regs.
+ *                 result.color == R0.xyzw
+ *                 result.depth == R1.z
+ * When the fragprog contains instructions to write depth,
+ * NV30_TCL_PRIMITIVE_3D_UNK1D78=0 otherwise it is set to 1.
+ *
+ * Constants are inserted directly after the instruction that uses them.
+ * 
+ * It appears that it's not possible to use two input registers in one
+ * instruction as the input sourcing is done in the instruction dword
+ * and not the source selection dwords.  As such instructions such as:
+ * 
+ *                 ADD result.color, fragment.color, fragment.texcoord[0];
+ *
+ * must be split into two MOV's and then an ADD (nvidia does this) but
+ * I'm not sure why it's not just one MOV and then source the second input
+ * in the ADD instruction..
+ *
+ * Negation of the full source is done with NV30_FP_REG_NEGATE, arbitrary
+ * negation requires multiplication with a const.
+ *
+ * Arbitrary swizzling is supported with the exception of SWIZZLE_ZERO and
+ * SWIZZLE_ONE.
+ *
+ * The temp/result regs appear to be initialised to (0.0, 0.0, 0.0, 0.0) as
+ * SWIZZLE_ZERO is implemented simply by not writing to the relevant components
+ * of the destination.
+ *
+ * Looping
+ *   Loops appear to be fairly expensive on NV40 at least, the proprietary
+ *   driver goes to a lot of effort to avoid using the native looping
+ *   instructions.  If the total number of *executed* instructions between
+ *   REP/ENDREP or LOOP/ENDLOOP is <=500, the driver will unroll the loop.
+ *   The maximum loop count is 255.
+ *
+ * Conditional execution
+ *   TODO
+ * 
+ * Non-native instructions:
+ *         LIT
+ *         LRP - MAD+MAD
+ *         SUB - ADD, negate second source
+ *         RSQ - LG2 + EX2
+ *         POW - LG2 + MUL + EX2
+ *         SCS - COS + SIN
+ *         XPD
+ *         DP2 - MUL + ADD
+ *         NRM
+ */
+
+//== Opcode / Destination selection ==
+#define NV40_FP_OP_PROGRAM_END                                          (1 << 0)
+#define NV40_FP_OP_OUT_REG_SHIFT                                               1
+#define NV40_FP_OP_OUT_REG_MASK                                        (31 << 1)
+/* Needs to be set when writing outputs to get expected result.. */
+#define NV40_FP_OP_UNK0_7                                               (1 << 7)
+#define NV40_FP_OP_COND_WRITE_ENABLE                                    (1 << 8)
+#define NV40_FP_OP_OUTMASK_SHIFT                                               9
+#define NV40_FP_OP_OUTMASK_MASK                                       (0xF << 9)
+#    define NV40_FP_OP_OUT_X                                            (1 << 9)
+#    define NV40_FP_OP_OUT_Y                                            (1 <<10)
+#    define NV40_FP_OP_OUT_Z                                            (1 <<11)
+#    define NV40_FP_OP_OUT_W                                            (1 <<12)
+/* Uncertain about these, especially the input_src values.. it's possible that
+ * they can be dynamically changed.
+ */
+#define NV40_FP_OP_INPUT_SRC_SHIFT                                            13
+#define NV40_FP_OP_INPUT_SRC_MASK                                     (15 << 13)
+#    define NV40_FP_OP_INPUT_SRC_POSITION                                    0x0
+#    define NV40_FP_OP_INPUT_SRC_COL0                                        0x1
+#    define NV40_FP_OP_INPUT_SRC_COL1                                        0x2
+#    define NV40_FP_OP_INPUT_SRC_FOGC                                        0x3
+#    define NV40_FP_OP_INPUT_SRC_TC0                                         0x4
+#    define NV40_FP_OP_INPUT_SRC_TC(n)                                 (0x4 + n)
+#    define NV40_FP_OP_INPUT_SRC_FACING                                      0xE
+#define NV40_FP_OP_TEX_UNIT_SHIFT                                             17
+#define NV40_FP_OP_TEX_UNIT_MASK                                     (0xF << 17)
+#define NV40_FP_OP_PRECISION_SHIFT                                            22
+#define NV40_FP_OP_PRECISION_MASK                                      (3 << 22)
+#   define NV40_FP_PRECISION_FP32                                              0
+#   define NV40_FP_PRECISION_FP16                                              1
+#   define NV40_FP_PRECISION_FX12                                              2
+#define NV40_FP_OP_OPCODE_SHIFT                                               24
+#define NV40_FP_OP_OPCODE_MASK                                      (0x3F << 24)
+#        define NV40_FP_OP_OPCODE_NOP                                       0x00
+#        define NV40_FP_OP_OPCODE_MOV                                       0x01
+#        define NV40_FP_OP_OPCODE_MUL                                       0x02
+#        define NV40_FP_OP_OPCODE_ADD                                       0x03
+#        define NV40_FP_OP_OPCODE_MAD                                       0x04
+#        define NV40_FP_OP_OPCODE_DP3                                       0x05
+#        define NV40_FP_OP_OPCODE_DP4                                       0x06
+#        define NV40_FP_OP_OPCODE_DST                                       0x07
+#        define NV40_FP_OP_OPCODE_MIN                                       0x08
+#        define NV40_FP_OP_OPCODE_MAX                                       0x09
+#        define NV40_FP_OP_OPCODE_SLT                                       0x0A
+#        define NV40_FP_OP_OPCODE_SGE                                       0x0B
+#        define NV40_FP_OP_OPCODE_SLE                                       0x0C
+#        define NV40_FP_OP_OPCODE_SGT                                       0x0D
+#        define NV40_FP_OP_OPCODE_SNE                                       0x0E
+#        define NV40_FP_OP_OPCODE_SEQ                                       0x0F
+#        define NV40_FP_OP_OPCODE_FRC                                       0x10
+#        define NV40_FP_OP_OPCODE_FLR                                       0x11
+#        define NV40_FP_OP_OPCODE_KIL                                       0x12
+#        define NV40_FP_OP_OPCODE_PK4B                                      0x13
+#        define NV40_FP_OP_OPCODE_UP4B                                      0x14
+/* DDX/DDY can only write to XY */
+#        define NV40_FP_OP_OPCODE_DDX                                       0x15
+#        define NV40_FP_OP_OPCODE_DDY                                       0x16
+#        define NV40_FP_OP_OPCODE_TEX                                       0x17
+#        define NV40_FP_OP_OPCODE_TXP                                       0x18
+#        define NV40_FP_OP_OPCODE_TXD                                       0x19
+#        define NV40_FP_OP_OPCODE_RCP                                       0x1A
+#        define NV40_FP_OP_OPCODE_EX2                                       0x1C
+#        define NV40_FP_OP_OPCODE_LG2                                       0x1D
+#        define NV40_FP_OP_OPCODE_COS                                       0x22
+#        define NV40_FP_OP_OPCODE_SIN                                       0x23
+#        define NV40_FP_OP_OPCODE_PK2H                                      0x24
+#        define NV40_FP_OP_OPCODE_UP2H                                      0x25
+#        define NV40_FP_OP_OPCODE_PK4UB                                     0x27
+#        define NV40_FP_OP_OPCODE_UP4UB                                     0x28
+#        define NV40_FP_OP_OPCODE_PK2US                                     0x29
+#        define NV40_FP_OP_OPCODE_UP2US                                     0x2A
+#        define NV40_FP_OP_OPCODE_DP2A                                      0x2E
+#        define NV40_FP_OP_OPCODE_TXL                                       0x2F
+#        define NV40_FP_OP_OPCODE_TXB                                       0x31
+#        define NV40_FP_OP_OPCODE_DIV                                       0x3A
+#        define NV40_FP_OP_OPCODE_UNK_LIT                                   0x3C
+/* The use of these instructions appears to be indicated by bit 31 of DWORD 2.*/
+#        define NV40_FP_OP_BRA_OPCODE_BRK                                    0x0
+#        define NV40_FP_OP_BRA_OPCODE_CAL                                    0x1
+#        define NV40_FP_OP_BRA_OPCODE_IF                                     0x2
+#        define NV40_FP_OP_BRA_OPCODE_LOOP                                   0x3
+#        define NV40_FP_OP_BRA_OPCODE_REP                                    0x4
+#        define NV40_FP_OP_BRA_OPCODE_RET                                    0x5
+#define NV40_FP_OP_OUT_SAT                                             (1 << 31)
+
+/* high order bits of SRC0 */
+#define NV40_FP_OP_OUT_ABS                                             (1 << 29)
+#define NV40_FP_OP_COND_SWZ_W_SHIFT                                           27
+#define NV40_FP_OP_COND_SWZ_W_MASK                                     (3 << 27)
+#define NV40_FP_OP_COND_SWZ_Z_SHIFT                                           25
+#define NV40_FP_OP_COND_SWZ_Z_MASK                                     (3 << 25)
+#define NV40_FP_OP_COND_SWZ_Y_SHIFT                                           23
+#define NV40_FP_OP_COND_SWZ_Y_MASK                                     (3 << 23)
+#define NV40_FP_OP_COND_SWZ_X_SHIFT                                           21
+#define NV40_FP_OP_COND_SWZ_X_MASK                                     (3 << 21)
+#define NV40_FP_OP_COND_SWZ_ALL_SHIFT                                         21
+#define NV40_FP_OP_COND_SWZ_ALL_MASK                                (0xFF << 21)
+#define NV40_FP_OP_COND_SHIFT                                                 18
+#define NV40_FP_OP_COND_MASK                                        (0x07 << 18)
+#        define NV40_FP_OP_COND_FL                                             0
+#        define NV40_FP_OP_COND_LT                                             1
+#        define NV40_FP_OP_COND_EQ                                             2
+#        define NV40_FP_OP_COND_LE                                             3
+#        define NV40_FP_OP_COND_GT                                             4
+#        define NV40_FP_OP_COND_NE                                             5
+#        define NV40_FP_OP_COND_GE                                             6
+#        define NV40_FP_OP_COND_TR                                             7
+
+/* high order bits of SRC1 */
+#define NV40_FP_OP_OPCODE_IS_BRANCH                                      (1<<31)
+#define NV40_FP_OP_DST_SCALE_SHIFT                                            28
+#define NV40_FP_OP_DST_SCALE_MASK                                      (3 << 28)
+#define NV40_FP_OP_DST_SCALE_1X                                                0
+#define NV40_FP_OP_DST_SCALE_2X                                                1
+#define NV40_FP_OP_DST_SCALE_4X                                                2
+#define NV40_FP_OP_DST_SCALE_8X                                                3
+#define NV40_FP_OP_DST_SCALE_INV_2X                                            5
+#define NV40_FP_OP_DST_SCALE_INV_4X                                            6
+#define NV40_FP_OP_DST_SCALE_INV_8X                                            7
+
+/* SRC1 LOOP */
+#define NV40_FP_OP_LOOP_INCR_SHIFT                                            19
+#define NV40_FP_OP_LOOP_INCR_MASK                                   (0xFF << 19)
+#define NV40_FP_OP_LOOP_INDEX_SHIFT                                           10
+#define NV40_FP_OP_LOOP_INDEX_MASK                                  (0xFF << 10)
+#define NV40_FP_OP_LOOP_COUNT_SHIFT                                            2
+#define NV40_FP_OP_LOOP_COUNT_MASK                                   (0xFF << 2)
+
+/* SRC1 IF */
+#define NV40_FP_OP_ELSE_ID_SHIFT                                               2
+#define NV40_FP_OP_ELSE_ID_MASK                                      (0xFF << 2)
+
+/* SRC1 CAL */
+#define NV40_FP_OP_IADDR_SHIFT                                                 2
+#define NV40_FP_OP_IADDR_MASK                                        (0xFF << 2)
+
+/* SRC1 REP
+ *   I have no idea why there are 3 count values here..  but they
+ *   have always been filled with the same value in my tests so
+ *   far..
+ */
+#define NV40_FP_OP_REP_COUNT1_SHIFT                                            2
+#define NV40_FP_OP_REP_COUNT1_MASK                                   (0xFF << 2)
+#define NV40_FP_OP_REP_COUNT2_SHIFT                                           10
+#define NV40_FP_OP_REP_COUNT2_MASK                                  (0xFF << 10)
+#define NV40_FP_OP_REP_COUNT3_SHIFT                                           19
+#define NV40_FP_OP_REP_COUNT3_MASK                                  (0xFF << 19)
+
+/* SRC2 REP/IF */
+#define NV40_FP_OP_END_ID_SHIFT                                                2
+#define NV40_FP_OP_END_ID_MASK                                       (0xFF << 2)
+
+// SRC2 high-order
+#define NV40_FP_OP_INDEX_INPUT                                         (1 << 30)
+#define NV40_FP_OP_ADDR_INDEX_SHIFT                                           19
+#define NV40_FP_OP_ADDR_INDEX_MASK                                   (0xF << 19)
+
+//== Register selection ==
+#define NV40_FP_REG_TYPE_SHIFT                                                 0
+#define NV40_FP_REG_TYPE_MASK                                           (3 << 0)
+#        define NV40_FP_REG_TYPE_TEMP                                          0
+#        define NV40_FP_REG_TYPE_INPUT                                         1
+#        define NV40_FP_REG_TYPE_CONST                                         2
+#define NV40_FP_REG_SRC_SHIFT                                                  2
+#define NV40_FP_REG_SRC_MASK                                           (31 << 2)
+#define NV40_FP_REG_UNK_0                                               (1 << 8)
+#define NV40_FP_REG_SWZ_ALL_SHIFT                                              9
+#define NV40_FP_REG_SWZ_ALL_MASK                                      (255 << 9)
+#define NV40_FP_REG_SWZ_X_SHIFT                                                9
+#define NV40_FP_REG_SWZ_X_MASK                                          (3 << 9)
+#define NV40_FP_REG_SWZ_Y_SHIFT                                               11
+#define NV40_FP_REG_SWZ_Y_MASK                                         (3 << 11)
+#define NV40_FP_REG_SWZ_Z_SHIFT                                               13
+#define NV40_FP_REG_SWZ_Z_MASK                                         (3 << 13)
+#define NV40_FP_REG_SWZ_W_SHIFT                                               15
+#define NV40_FP_REG_SWZ_W_MASK                                         (3 << 15)
+#        define NV40_FP_SWIZZLE_X                                              0
+#        define NV40_FP_SWIZZLE_Y                                              1
+#        define NV40_FP_SWIZZLE_Z                                              2
+#        define NV40_FP_SWIZZLE_W                                              3
+#define NV40_FP_REG_NEGATE                                             (1 << 17)
+
+struct nv40_sreg {
+       int output;
+       int type;
+       int index;
+
+       int dst_scale;
+
+       int negate;
+       int abs;
+       int swz[4];
+
+       int cc_update;
+       int cc_update_reg;
+       int cc_test;
+       int cc_test_reg;
+       int cc_swz[4];
+};
+
+static INLINE struct nv40_sreg
+nv40_sr(int out, int type, int index)
+{
+       struct nv40_sreg temp = {
+               .output = out,
+               .type = type,
+               .index = index,
+               .dst_scale = DEF_SCALE,
+               .abs = 0,
+               .negate = 0,
+               .swz = { 0, 1, 2, 3 },
+               .cc_update = 0,
+               .cc_update_reg = 0,
+               .cc_test = DEF_CTEST,
+               .cc_test_reg = 0,
+               .cc_swz = { 0, 1, 2, 3 },
+       };
+       return temp;
+}
+
+static INLINE struct nv40_sreg
+nv40_sr_swz(struct nv40_sreg src, int x, int y, int z, int w)
+{
+       struct nv40_sreg dst = src;
+
+       dst.swz[SWZ_X] = src.swz[x];
+       dst.swz[SWZ_Y] = src.swz[y];
+       dst.swz[SWZ_Z] = src.swz[z];
+       dst.swz[SWZ_W] = src.swz[w];
+       return dst;
+}
+
+static INLINE struct nv40_sreg
+nv40_sr_neg(struct nv40_sreg src)
+{
+       src.negate = !src.negate;
+       return src;
+}
+
+static INLINE struct nv40_sreg
+nv40_sr_abs(struct nv40_sreg src)
+{
+       src.abs = 1;
+       return src;
+}
+
+static INLINE struct nv40_sreg
+nv40_sr_scale(struct nv40_sreg src, int scale)
+{
+       src.dst_scale = scale;
+       return src;
+}
+
+#endif

diff --git a/src/mesa/pipe/nv40/nv40_state.c b/src/mesa/pipe/nv40/nv40_state.c
new file mode 100644 (file)
index 0000000..e38a5ea
--- /dev/null
+++ b/src/mesa/pipe/nv40/nv40_state.c
@@ -0,0 +1,674 @@
+#include "pipe/p_state.h"
+#include "pipe/p_defines.h"
+#include "pipe/p_util.h"
+
+#include "nv40_context.h"
+#include "nv40_dma.h"
+#include "nv40_state.h"
+
+#include "nvgl_pipe.h"
+
+static void *
+nv40_alpha_test_state_create(struct pipe_context *pipe,
+                            const struct pipe_alpha_test_state *cso)
+{
+       struct nv40_alpha_test_state *at;
+
+       at = malloc(sizeof(struct nv40_alpha_test_state));
+
+       at->enabled = cso->enabled ? 1 : 0;
+       if (at->enabled) {
+               at->func = nvgl_comparison_op(cso->func);
+               at->ref  = float_to_ubyte(cso->ref);
+       }
+
+       return (void *)at;
+}
+
+static void
+nv40_alpha_test_state_bind(struct pipe_context *pipe, void *hwcso)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       struct nv40_alpha_test_state *at = hwcso;
+
+       if (at->enabled) {
+               BEGIN_RING(curie, NV40TCL_ALPHA_TEST_ENABLE, 3);
+               OUT_RING  (at->enabled);
+               OUT_RING  (at->func);
+               OUT_RING  (at->ref);
+       } else {
+               BEGIN_RING(curie, NV40TCL_ALPHA_TEST_ENABLE, 1);
+               OUT_RING  (0);
+       }
+}
+
+static void
+nv40_alpha_test_state_delete(struct pipe_context *pipe, void *hwcso)
+{
+       free(hwcso);
+}
+
+static void *
+nv40_blend_state_create(struct pipe_context *pipe,
+                       const struct pipe_blend_state *cso)
+{
+       struct nv40_blend_state *cb;
+
+       cb = malloc(sizeof(struct nv40_blend_state));
+
+       cb->b_enable = cso->blend_enable ? 1 : 0;
+       if (cb->b_enable) {
+               cb->b_srcfunc = ((nvgl_blend_func(cso->alpha_src_factor)<<16) |
+                                (nvgl_blend_func(cso->rgb_src_factor)));
+               cb->b_dstfunc = ((nvgl_blend_func(cso->alpha_dst_factor)<<16) |
+                                (nvgl_blend_func(cso->rgb_dst_factor)));
+               cb->b_eqn = ((nvgl_blend_eqn(cso->alpha_func) << 16) |
+                            (nvgl_blend_eqn(cso->rgb_func)));
+       }
+
+       cb->l_enable = cso->logicop_enable ? 1 : 0;
+       if (cb->l_enable) {
+               cb->l_op = nvgl_logicop_func(cso->logicop_func);
+       }
+
+       cb->c_mask = (((cso->colormask & PIPE_MASK_A) ? (0x01<<24) : 0) |
+                     ((cso->colormask & PIPE_MASK_R) ? (0x01<<16) : 0) |
+                     ((cso->colormask & PIPE_MASK_G) ? (0x01<< 8) : 0) |
+                     ((cso->colormask & PIPE_MASK_B) ? (0x01<< 0) : 0));
+
+       cb->d_enable = cso->dither ? 1 : 0;
+
+       return (void *)cb;
+}
+
+static void
+nv40_blend_state_bind(struct pipe_context *pipe, void *hwcso)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       struct nv40_blend_state *cb = hwcso;
+
+       BEGIN_RING(curie, NV40TCL_DITHER_ENABLE, 1);
+       OUT_RING  (cb->d_enable);
+
+       if (cb->b_enable) {
+               BEGIN_RING(curie, NV40TCL_BLEND_ENABLE, 3);
+               OUT_RING  (cb->b_enable);
+               OUT_RING  (cb->b_srcfunc);
+               OUT_RING  (cb->b_dstfunc);
+               BEGIN_RING(curie, NV40TCL_BLEND_EQUATION, 2);
+               OUT_RING  (cb->b_eqn);
+               OUT_RING  (cb->c_mask);
+       } else {
+               BEGIN_RING(curie, NV40TCL_BLEND_ENABLE, 1);
+               OUT_RING  (0);
+       }
+
+       if (cb->l_enable) {
+               BEGIN_RING(curie, NV40TCL_COLOR_LOGIC_OP_ENABLE, 2);
+               OUT_RING  (cb->l_enable);
+               OUT_RING  (cb->l_op);
+       } else {
+               BEGIN_RING(curie, NV40TCL_COLOR_LOGIC_OP_ENABLE, 1);
+               OUT_RING  (0);
+       }
+}
+
+static void
+nv40_blend_state_delete(struct pipe_context *pipe, void *hwcso)
+{
+       free(hwcso);
+}
+
+static void *
+nv40_sampler_state_create(struct pipe_context *pipe,
+                         const struct pipe_sampler_state *cso)
+{
+       struct nv40_sampler_state *ps;
+       
+       ps = malloc(sizeof(struct nv40_sampler_state));
+       
+       ps->wrap = ((nv40_tex_wrap_mode(cso->wrap_r) << 16) |
+                   (nv40_tex_wrap_mode(cso->wrap_t) <<  8) |
+                   (nv40_tex_wrap_mode(cso->wrap_s) <<  0));
+       ps->filt = ((nv40_tex_filter(cso->min_img_filter,
+                                    cso->min_mip_filter) << 16) |
+                   (nv40_tex_filter(cso->mag_img_filter,
+                                    PIPE_TEX_MIPFILTER_NONE) << 24));
+       ps->bcol = ((float_to_ubyte(cso->border_color[3]) << 24) |
+                   (float_to_ubyte(cso->border_color[0]) << 16) |
+                   (float_to_ubyte(cso->border_color[1]) <<  8) |
+                   (float_to_ubyte(cso->border_color[2]) <<  0));
+
+       return (void *)ps;
+}
+
+static void
+nv40_sampler_state_bind(struct pipe_context *pipe, unsigned unit,
+                       void *hwcso)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       struct nv40_sampler_state *ps = hwcso;
+
+       nv40->tex_sampler[unit]  = ps;
+       nv40->tex_dirty         |= (1 << unit);
+
+       nv40->dirty |= NV40_NEW_TEXTURE;
+}
+
+static void
+nv40_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
+{
+       free(hwcso);
+}
+
+static void *
+nv40_rasterizer_state_create(struct pipe_context *pipe,
+                            const struct pipe_rasterizer_state *cso)
+{
+       struct nv40_rasterizer_state *rs;
+
+       /*XXX: ignored:
+        *      light_twoside
+        *      offset_cw/ccw -nohw
+        *      scissor
+        *      point_smooth -nohw
+        *      multisample
+        *      offset_units / offset_scale
+        */
+       rs = malloc(sizeof(struct nv40_rasterizer_state));
+
+       rs->shade_model = cso->flatshade ? 0x1d00 : 0x1d01;
+
+       rs->line_width = (unsigned char)(cso->line_width * 8.0) & 0xff;
+       rs->line_smooth_en = cso->line_smooth ? 1 : 0;
+       rs->line_stipple_en = cso->line_stipple_enable ? 1 : 0;
+       rs->line_stipple = (cso->line_stipple_pattern << 16) |
+                           cso->line_stipple_factor;
+
+       rs->point_size = *(uint32_t*)&cso->point_size;
+
+       rs->poly_smooth_en = cso->poly_smooth ? 1 : 0;
+       rs->poly_stipple_en = cso->poly_stipple_enable ? 1 : 0;
+
+       if (cso->front_winding == PIPE_WINDING_CCW) {
+               rs->front_face = 0x0901;
+               rs->poly_mode_front = nvgl_polygon_mode(cso->fill_ccw);
+               rs->poly_mode_back  = nvgl_polygon_mode(cso->fill_cw);
+       } else {
+               rs->front_face = 0x0900;
+               rs->poly_mode_front = nvgl_polygon_mode(cso->fill_cw);
+               rs->poly_mode_back  = nvgl_polygon_mode(cso->fill_ccw);
+       }
+
+       rs->cull_face_en = 0;
+       rs->cull_face    = 0x0900;
+       switch (cso->cull_mode) {
+       case PIPE_WINDING_CCW:
+               rs->cull_face = 0x0901;
+               /* fall-through */
+       case PIPE_WINDING_CW:
+               rs->cull_face_en = 1;
+               break;
+       case PIPE_WINDING_NONE:
+       default:
+               break;
+       }
+
+       return (void *)rs;
+}
+
+static void
+nv40_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       struct nv40_rasterizer_state *rs = hwcso;
+
+       BEGIN_RING(curie, NV40TCL_SHADE_MODEL, 1);
+       OUT_RING  (rs->shade_model);
+
+       BEGIN_RING(curie, NV40TCL_LINE_WIDTH, 2);
+       OUT_RING  (rs->line_width);
+       OUT_RING  (rs->line_smooth_en);
+       BEGIN_RING(curie, NV40TCL_LINE_STIPPLE_ENABLE, 2);
+       OUT_RING  (rs->line_stipple_en);
+       OUT_RING  (rs->line_stipple);
+
+       BEGIN_RING(curie, NV40TCL_POINT_SIZE, 1);
+       OUT_RING  (rs->point_size);
+
+       BEGIN_RING(curie, NV40TCL_POLYGON_MODE_FRONT, 6);
+       OUT_RING  (rs->poly_mode_front);
+       OUT_RING  (rs->poly_mode_back);
+       OUT_RING  (rs->cull_face);
+       OUT_RING  (rs->front_face);
+       OUT_RING  (rs->poly_smooth_en);
+       OUT_RING  (rs->cull_face_en);
+
+       BEGIN_RING(curie, NV40TCL_POLYGON_STIPPLE_ENABLE, 1);
+       OUT_RING  (rs->poly_stipple_en);
+}
+
+static void
+nv40_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
+{
+       free(hwcso);
+}
+
+static void *
+nv40_depth_stencil_state_create(struct pipe_context *pipe,
+                               const struct pipe_depth_stencil_state *cso)
+{
+       struct nv40_depth_stencil_state *zs;
+
+       /*XXX: ignored:
+        *      depth.occlusion_count
+        *      depth.clear
+        *      stencil.clear_value
+        */
+       zs = malloc(sizeof(struct nv40_depth_stencil_state));
+
+       zs->depth.func          = nvgl_comparison_op(cso->depth.func);
+       zs->depth.write_enable  = cso->depth.writemask ? 1 : 0;
+       zs->depth.test_enable   = cso->depth.enabled ? 1 : 0;
+
+       zs->stencil.back.enable = cso->stencil.back_enabled ? 1 : 0;
+       zs->stencil.back.wmask  = cso->stencil.write_mask[1];
+       zs->stencil.back.func   =
+               nvgl_comparison_op(cso->stencil.back_func);
+       zs->stencil.back.ref    = cso->stencil.ref_value[1];
+       zs->stencil.back.vmask  = cso->stencil.value_mask[1];
+       zs->stencil.back.fail   = nvgl_stencil_op(cso->stencil.back_fail_op);
+       zs->stencil.back.zfail  = nvgl_stencil_op(cso->stencil.back_zfail_op);
+       zs->stencil.back.zpass  = nvgl_stencil_op(cso->stencil.back_zpass_op);
+
+       zs->stencil.front.enable= cso->stencil.front_enabled ? 1 : 0;
+       zs->stencil.front.wmask = cso->stencil.write_mask[0];
+       zs->stencil.front.func  =
+               nvgl_comparison_op(cso->stencil.front_func);
+       zs->stencil.front.ref   = cso->stencil.ref_value[0];
+       zs->stencil.front.vmask = cso->stencil.value_mask[0];
+       zs->stencil.front.fail  = nvgl_stencil_op(cso->stencil.front_fail_op);
+       zs->stencil.front.zfail = nvgl_stencil_op(cso->stencil.front_zfail_op);
+       zs->stencil.front.zpass = nvgl_stencil_op(cso->stencil.front_zpass_op);
+
+       return (void *)zs;
+}
+
+static void
+nv40_depth_stencil_state_bind(struct pipe_context *pipe, void *hwcso)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       struct nv40_depth_stencil_state *zs = hwcso;
+
+       BEGIN_RING(curie, NV40TCL_DEPTH_FUNC, 3);
+       OUT_RINGp ((uint32_t *)&zs->depth, 3);
+       BEGIN_RING(curie, NV40TCL_STENCIL_BACK_ENABLE, 16);
+       OUT_RINGp ((uint32_t *)&zs->stencil.back, 8);
+       OUT_RINGp ((uint32_t *)&zs->stencil.front, 8);
+}
+
+static void
+nv40_depth_stencil_state_delete(struct pipe_context *pipe, void *hwcso)
+{
+       free(hwcso);
+}
+
+static void *
+nv40_vp_state_create(struct pipe_context *pipe,
+                    const struct pipe_shader_state *cso)
+{
+       struct nv40_vertex_program *vp;
+
+       vp = calloc(1, sizeof(struct nv40_vertex_program));
+       vp->pipe = cso;
+
+       return (void *)vp;
+}
+
+static void
+nv40_vp_state_bind(struct pipe_context *pipe, void *hwcso)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       struct nv40_vertex_program *vp = hwcso;
+
+       nv40->vertprog.vp = vp;
+       nv40->dirty |= NV40_NEW_VERTPROG;
+}
+
+static void
+nv40_vp_state_delete(struct pipe_context *pipe, void *hwcso)
+{
+       free(hwcso);
+}
+
+static void *
+nv40_fp_state_create(struct pipe_context *pipe,
+                    const struct pipe_shader_state *cso)
+{
+       struct nv40_fragment_program *fp;
+
+       fp = calloc(1, sizeof(struct nv40_fragment_program));
+       fp->pipe = cso;
+
+       return (void *)fp;
+}
+
+static void
+nv40_fp_state_bind(struct pipe_context *pipe, void *hwcso)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       struct nv40_fragment_program *fp = hwcso;
+
+       nv40->fragprog.fp = fp;
+       nv40->dirty |= NV40_NEW_FRAGPROG;
+}
+
+static void
+nv40_fp_state_delete(struct pipe_context *pipe, void *hwcso)
+{
+       free(hwcso);
+}
+
+static void
+nv40_set_blend_color(struct pipe_context *pipe,
+                    const struct pipe_blend_color *bcol)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+
+       BEGIN_RING(curie, NV40TCL_BLEND_COLOR, 1);
+       OUT_RING  ((float_to_ubyte(bcol->color[3]) << 24) |
+                  (float_to_ubyte(bcol->color[0]) << 16) |
+                  (float_to_ubyte(bcol->color[1]) <<  8) |
+                  (float_to_ubyte(bcol->color[2]) <<  0));
+}
+
+static void
+nv40_set_clip_state(struct pipe_context *pipe,
+                   const struct pipe_clip_state *clip)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       
+       nv40->dirty |= NV40_NEW_VERTPROG;
+}
+
+static void
+nv40_set_clear_color_state(struct pipe_context *pipe,
+                          const struct pipe_clear_color_state *ccol)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+
+       BEGIN_RING(curie, NV40TCL_CLEAR_VALUE_COLOR, 1);
+       OUT_RING  ((float_to_ubyte(ccol->color[3]) << 24) |
+                  (float_to_ubyte(ccol->color[0]) << 16) |
+                  (float_to_ubyte(ccol->color[1]) <<  8) |
+                  (float_to_ubyte(ccol->color[2]) <<  0));
+}
+
+static void
+nv40_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
+                        const struct pipe_constant_buffer *buf )
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+
+       if (shader == PIPE_SHADER_VERTEX) {
+               nv40->vertprog.constant_buf = buf->buffer;
+               nv40->dirty |= NV40_NEW_VERTPROG;
+       } else
+       if (shader == PIPE_SHADER_FRAGMENT) {
+               nv40->fragprog.constant_buf = buf->buffer;
+               nv40->dirty |= NV40_NEW_FRAGPROG;
+       }
+}
+
+static void
+nv40_set_feedback_state(struct pipe_context *pipe,
+                       const struct pipe_feedback_state *feedback)
+{
+       NOUVEAU_ERR("\n");
+}
+
+#define get_region(surf) ((surf) ? surf->region : NULL)
+static void
+nv40_set_framebuffer_state(struct pipe_context *pipe,
+                          const struct pipe_framebuffer_state *fb)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       struct nouveau_winsys *nvws = nv40->nvws;
+       struct pipe_region *region;
+       uint32_t rt_enable = 0, rt_format = 0;
+
+       if ((region = get_region(fb->cbufs[0]))) {
+               rt_enable |= NV40TCL_RT_ENABLE_COLOR0;
+
+               BEGIN_RING(curie, NV40TCL_DMA_COLOR0, 1);
+               OUT_RELOCo(region->buffer, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+               BEGIN_RING(curie, NV40TCL_COLOR0_PITCH, 2);
+               OUT_RING  (region->pitch * region->cpp);
+               OUT_RELOCl(region->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+       }
+
+       if ((region = get_region(fb->cbufs[1]))) {
+               rt_enable |= NV40TCL_RT_ENABLE_COLOR1;
+
+               BEGIN_RING(curie, NV40TCL_DMA_COLOR1, 1);
+               OUT_RELOCo(region->buffer, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+               BEGIN_RING(curie, NV40TCL_COLOR1_OFFSET, 2);
+               OUT_RELOCl(region->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+               OUT_RING  (region->pitch * region->cpp);
+       }
+
+       if ((region = get_region(fb->cbufs[2]))) {
+               rt_enable |= NV40TCL_RT_ENABLE_COLOR2;
+
+               BEGIN_RING(curie, NV40TCL_DMA_COLOR2, 1);
+               OUT_RELOCo(region->buffer, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+               BEGIN_RING(curie, NV40TCL_COLOR2_OFFSET, 1);
+               OUT_RELOCl(region->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+               BEGIN_RING(curie, NV40TCL_COLOR2_PITCH, 1);
+               OUT_RING  (region->pitch * region->cpp);
+       }
+
+       if ((region = get_region(fb->cbufs[3]))) {
+               rt_enable |= NV40TCL_RT_ENABLE_COLOR3;
+
+               BEGIN_RING(curie, NV40TCL_DMA_COLOR3, 1);
+               OUT_RELOCo(region->buffer, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+               BEGIN_RING(curie, NV40TCL_COLOR3_OFFSET, 1);
+               OUT_RELOCl(region->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+               BEGIN_RING(curie, NV40TCL_COLOR3_PITCH, 1);
+               OUT_RING  (region->pitch * region->cpp);
+       }
+
+       if ((region = get_region(fb->zbuf))) {
+               BEGIN_RING(curie, NV40TCL_DMA_ZETA, 1);
+               OUT_RELOCo(region->buffer,
+                          NOUVEAU_BO_VRAM | NOUVEAU_BO_WR | NOUVEAU_BO_RD);
+               BEGIN_RING(curie, NV40TCL_ZETA_OFFSET, 1);
+               OUT_RELOCl(region->buffer, 0,
+                          NOUVEAU_BO_VRAM | NOUVEAU_BO_WR | NOUVEAU_BO_RD);
+               BEGIN_RING(curie, NV40TCL_ZETA_PITCH, 1);
+               OUT_RING  (region->pitch * region->cpp);
+       }
+
+       if (rt_enable & (NV40TCL_RT_ENABLE_COLOR1 | NV40TCL_RT_ENABLE_COLOR2 |
+                        NV40TCL_RT_ENABLE_COLOR3))
+               rt_enable |= NV40TCL_RT_ENABLE_MRT;
+       BEGIN_RING(curie, NV40TCL_RT_ENABLE, 1);
+       OUT_RING  (rt_enable);
+
+       if (0) {
+#if 0
+               rt_format |= (log2width <<
+                             NV40TCL_RT_FORMAT_LOG2_WIDTH_SHIFT);
+               rt_format |= (log2height <<
+                             NV40TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT);
+#endif
+               rt_format |= (NV40TCL_RT_FORMAT_TYPE_SWIZZLED <<
+                             NV40TCL_RT_FORMAT_TYPE_SHIFT);
+       } else {
+               rt_format |= (NV40TCL_RT_FORMAT_TYPE_LINEAR <<
+                             NV40TCL_RT_FORMAT_TYPE_SHIFT);
+       }
+
+       if (fb->cbufs[0]->format == PIPE_FORMAT_U_R5_G6_B5) {
+               rt_format |= (NV40TCL_RT_FORMAT_COLOR_R5G6B5 <<
+                             NV40TCL_RT_FORMAT_COLOR_SHIFT);
+       } else {
+               rt_format |= (NV40TCL_RT_FORMAT_COLOR_A8R8G8B8 <<
+                             NV40TCL_RT_FORMAT_COLOR_SHIFT);
+       }
+
+       if (fb->zbuf && fb->zbuf->format == PIPE_FORMAT_U_Z16) {
+               rt_format |= (NV40TCL_RT_FORMAT_DEPTH_Z16 <<
+                             NV40TCL_RT_FORMAT_DEPTH_SHIFT);
+       } else {
+               rt_format |= (NV40TCL_RT_FORMAT_DEPTH_Z24S8 <<
+                             NV40TCL_RT_FORMAT_DEPTH_SHIFT);
+       }
+
+       BEGIN_RING(curie, NV40TCL_RT_HORIZ, 3);
+       OUT_RING  ((fb->cbufs[0]->width  << 16) | 0);
+       OUT_RING  ((fb->cbufs[0]->height << 16) | 0);
+       OUT_RING  (rt_format);
+       BEGIN_RING(curie, NV40TCL_VIEWPORT_HORIZ, 2);
+       OUT_RING  ((fb->cbufs[0]->width  << 16) | 0);
+       OUT_RING  ((fb->cbufs[0]->height << 16) | 0);
+       BEGIN_RING(curie, NV40TCL_VIEWPORT_CLIP_HORIZ(0), 2);
+       OUT_RING  (((fb->cbufs[0]->width - 1)  << 16) | 0);
+       OUT_RING  (((fb->cbufs[0]->height - 1) << 16) | 0);
+}
+
+static void
+nv40_set_polygon_stipple(struct pipe_context *pipe,
+                        const struct pipe_poly_stipple *stipple)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+
+       BEGIN_RING(curie, NV40TCL_POLYGON_STIPPLE_PATTERN(0), 32);
+       OUT_RINGp ((uint32_t *)stipple->stipple, 32);
+}
+
+static void
+nv40_set_sampler_units(struct pipe_context *pipe,
+                      uint num_samplers, const uint *units)
+{
+}
+
+static void
+nv40_set_scissor_state(struct pipe_context *pipe,
+                      const struct pipe_scissor_state *s)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+
+       BEGIN_RING(curie, NV40TCL_SCISSOR_HORIZ, 2);
+       OUT_RING  (((s->maxx - s->minx) << 16) | s->minx);
+       OUT_RING  (((s->maxy - s->miny) << 16) | s->miny);
+}
+
+static void
+nv40_set_texture_state(struct pipe_context *pipe, unsigned unit,
+                      struct pipe_mipmap_tree *miptree)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+
+       nv40->tex_miptree[unit]  = miptree;
+       nv40->tex_dirty         |= unit;
+
+       nv40->dirty |= NV40_NEW_TEXTURE;
+}
+
+static void
+nv40_set_viewport_state(struct pipe_context *pipe,
+                       const struct pipe_viewport_state *vpt)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+
+       BEGIN_RING(curie, NV40TCL_VIEWPORT_TRANSLATE_X, 8);
+       OUT_RINGf (vpt->translate[0]);
+       OUT_RINGf (vpt->translate[1]);
+       OUT_RINGf (vpt->translate[2]);
+       OUT_RINGf (vpt->translate[3]);
+       OUT_RINGf (vpt->scale[0]);
+       OUT_RINGf (vpt->scale[1]);
+       OUT_RINGf (vpt->scale[2]);
+       OUT_RINGf (vpt->scale[3]);
+}
+
+static void
+nv40_set_vertex_buffer(struct pipe_context *pipe, unsigned index,
+                      const struct pipe_vertex_buffer *vb)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+
+       nv40->vtxbuf[index] = *vb;
+
+       nv40->dirty |= NV40_NEW_ARRAYS;
+}
+
+static void
+nv40_set_vertex_element(struct pipe_context *pipe, unsigned index,
+                       const struct pipe_vertex_element *ve)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+
+       nv40->vtxelt[index] = *ve;
+
+       nv40->dirty |= NV40_NEW_ARRAYS;
+}
+
+static void
+nv40_set_feedback_buffer(struct pipe_context *pipe, unsigned index,
+                        const struct pipe_feedback_buffer *fbb)
+{
+       NOUVEAU_ERR("\n");
+}
+
+void
+nv40_init_state_functions(struct nv40_context *nv40)
+{
+       nv40->pipe.create_alpha_test_state = nv40_alpha_test_state_create;
+       nv40->pipe.bind_alpha_test_state = nv40_alpha_test_state_bind;
+       nv40->pipe.delete_alpha_test_state = nv40_alpha_test_state_delete;
+
+       nv40->pipe.create_blend_state = nv40_blend_state_create;
+       nv40->pipe.bind_blend_state = nv40_blend_state_bind;
+       nv40->pipe.delete_blend_state = nv40_blend_state_delete;
+
+       nv40->pipe.create_sampler_state = nv40_sampler_state_create;
+       nv40->pipe.bind_sampler_state = nv40_sampler_state_bind;
+       nv40->pipe.delete_sampler_state = nv40_sampler_state_delete;
+
+       nv40->pipe.create_rasterizer_state = nv40_rasterizer_state_create;
+       nv40->pipe.bind_rasterizer_state = nv40_rasterizer_state_bind;
+       nv40->pipe.delete_rasterizer_state = nv40_rasterizer_state_delete;
+
+       nv40->pipe.create_depth_stencil_state = nv40_depth_stencil_state_create;
+       nv40->pipe.bind_depth_stencil_state = nv40_depth_stencil_state_bind;
+       nv40->pipe.delete_depth_stencil_state = nv40_depth_stencil_state_delete;
+
+       nv40->pipe.create_vs_state = nv40_vp_state_create;
+       nv40->pipe.bind_vs_state = nv40_vp_state_bind;
+       nv40->pipe.delete_vs_state = nv40_vp_state_delete;
+
+       nv40->pipe.create_fs_state = nv40_fp_state_create;
+       nv40->pipe.bind_fs_state = nv40_fp_state_bind;
+       nv40->pipe.delete_fs_state = nv40_fp_state_delete;
+
+       nv40->pipe.set_blend_color = nv40_set_blend_color;
+       nv40->pipe.set_clip_state = nv40_set_clip_state;
+       nv40->pipe.set_clear_color_state = nv40_set_clear_color_state;
+       nv40->pipe.set_constant_buffer = nv40_set_constant_buffer;
+//     nv40->pipe.set_feedback_state = nv40_set_feedback_state;
+       nv40->pipe.set_framebuffer_state = nv40_set_framebuffer_state;
+       nv40->pipe.set_polygon_stipple = nv40_set_polygon_stipple;
+       nv40->pipe.set_sampler_units = nv40_set_sampler_units;
+       nv40->pipe.set_scissor_state = nv40_set_scissor_state;
+       nv40->pipe.set_texture_state = nv40_set_texture_state;
+       nv40->pipe.set_viewport_state = nv40_set_viewport_state;
+
+       nv40->pipe.set_vertex_buffer = nv40_set_vertex_buffer;
+       nv40->pipe.set_vertex_element = nv40_set_vertex_element;
+
+//     nv40->pipe.set_feedback_buffer = nv40_set_feedback_buffer;
+}
+

diff --git a/src/mesa/pipe/nv40/nv40_state.h b/src/mesa/pipe/nv40/nv40_state.h
new file mode 100644 (file)
index 0000000..1535037
--- /dev/null
+++ b/src/mesa/pipe/nv40/nv40_state.h
@@ -0,0 +1,173 @@
+#ifndef __NV40_STATE_H__
+#define __NV40_STATE_H__
+
+#include "pipe/p_state.h"
+
+struct nv40_alpha_test_state {
+       uint32_t enabled;
+       uint32_t func;
+       uint32_t ref;
+};
+
+struct nv40_blend_state {
+       uint32_t b_enable;
+       uint32_t b_srcfunc;
+       uint32_t b_dstfunc;
+       uint32_t b_eqn;
+
+       uint32_t l_enable;
+       uint32_t l_op;
+
+       uint32_t c_mask;
+
+       uint32_t d_enable;
+};
+
+struct nv40_sampler_state {
+       uint32_t wrap;
+       uint32_t filt;
+       uint32_t bcol;
+};
+
+struct nv40_rasterizer_state {
+       uint32_t shade_model;
+
+       uint32_t line_width;
+       uint32_t line_smooth_en;
+       uint32_t line_stipple_en;
+       uint32_t line_stipple;
+
+       uint32_t point_size;
+
+       uint32_t poly_smooth_en;
+       uint32_t poly_stipple_en;
+       
+       uint32_t poly_mode_front;
+       uint32_t poly_mode_back;
+
+       uint32_t front_face;
+       uint32_t cull_face;
+       uint32_t cull_face_en;
+
+};
+
+struct nv40_vertex_program {
+       const struct pipe_shader_state *pipe;
+
+       boolean translated;
+       boolean on_hw;
+       int start_ip;
+
+       uint32_t *insn;
+       int       insn_len;
+
+       struct {
+               int pipe_id;
+               int hw_id;
+               float value[4];
+       } consts[256];
+       int num_consts;
+
+       uint32_t ir;
+       uint32_t or;
+};
+
+struct nv40_fragment_program {
+       const struct pipe_shader_state *pipe;
+
+       boolean translated;
+       boolean on_hw;
+
+       uint32_t *insn;
+       int       insn_len;
+
+       struct {
+               int pipe_id;
+               int hw_id;
+       } consts[256];
+       int num_consts;
+
+       struct pipe_buffer_handle *buffer;
+
+       boolean uses_kil;
+       boolean writes_depth;
+       int     num_regs;
+};
+
+struct nv40_depth_push {
+       uint32_t func;
+       uint32_t write_enable;
+       uint32_t test_enable;
+};
+
+struct nv40_stencil_push {
+       uint32_t enable;
+       uint32_t wmask;
+       uint32_t func;
+       uint32_t ref;
+       uint32_t vmask;
+       uint32_t fail;
+       uint32_t zfail;
+       uint32_t zpass;
+};
+
+struct nv40_depth_stencil_state {
+       struct nv40_depth_push depth;
+       union {
+               struct nv40_stencil_push back;
+               struct nv40_stencil_push front;
+       } stencil;
+};
+
+static INLINE unsigned
+nv40_tex_wrap_mode(unsigned wrap) {
+       switch (wrap) {
+       case PIPE_TEX_WRAP_REPEAT:
+               return NV40TCL_TEX_WRAP_S_REPEAT;
+       case PIPE_TEX_WRAP_MIRROR_REPEAT:
+               return NV40TCL_TEX_WRAP_S_MIRRORED_REPEAT;
+       case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
+               return NV40TCL_TEX_WRAP_S_CLAMP_TO_EDGE;
+       case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
+               return NV40TCL_TEX_WRAP_S_CLAMP_TO_BORDER;
+       case PIPE_TEX_WRAP_CLAMP:
+               return NV40TCL_TEX_WRAP_S_CLAMP;
+       case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
+               return NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE;
+       case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
+               return NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER;
+       case PIPE_TEX_WRAP_MIRROR_CLAMP:
+               return NV40TCL_TEX_WRAP_S_MIRROR_CLAMP;
+       default:
+               return NV40TCL_TEX_WRAP_S_REPEAT;
+       }
+}
+
+static INLINE unsigned
+nv40_tex_filter(unsigned f0, unsigned f1) {
+       switch (f0) {
+       case PIPE_TEX_FILTER_NEAREST:
+               switch (f1) {
+               case PIPE_TEX_MIPFILTER_NEAREST:
+                       return NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_NEAREST;
+               case PIPE_TEX_MIPFILTER_LINEAR:
+                       return NV40TCL_TEX_FILTER_MIN_NEAREST_MIPMAP_LINEAR;
+               case PIPE_TEX_MIPFILTER_NONE:
+               default:
+                       return NV40TCL_TEX_FILTER_MIN_NEAREST;
+               }
+       case PIPE_TEX_FILTER_LINEAR:
+       default:
+               switch (f1) {
+               case PIPE_TEX_MIPFILTER_NEAREST:
+                       return NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_NEAREST;
+               case PIPE_TEX_MIPFILTER_LINEAR:
+                       return NV40TCL_TEX_FILTER_MIN_LINEAR_MIPMAP_LINEAR;
+               case PIPE_TEX_MIPFILTER_NONE:
+               default:
+                       return NV40TCL_TEX_FILTER_MIN_LINEAR;
+               }
+       }
+}
+
+#endif

diff --git a/src/mesa/pipe/nv40/nv40_state_emit.c b/src/mesa/pipe/nv40/nv40_state_emit.c
new file mode 100644 (file)
index 0000000..a29c705
--- /dev/null
+++ b/src/mesa/pipe/nv40/nv40_state_emit.c
@@ -0,0 +1,112 @@
+#include "nv40_context.h"
+#include "nv40_dma.h"
+#include "nv40_state.h"
+
+static INLINE void
+nv40_state_update_fragprog(struct nv40_context *nv40)
+{
+       struct pipe_context *pipe = (struct pipe_context *)nv40;
+       struct nv40_fragment_program *fp = nv40->fragprog.fp;
+       float *map;
+       int i;
+
+       if (!fp->translated)
+               nv40_fragprog_translate(nv40, fp);
+
+       if (fp->num_consts) {
+               map = pipe->winsys->buffer_map(pipe->winsys,
+                                              nv40->fragprog.constant_buf,
+                                              PIPE_BUFFER_FLAG_READ);
+               for (i = 0; i < fp->num_consts; i++) {
+                       uint pid = fp->consts[i].pipe_id;
+
+                       if (pid == -1)
+                               continue;
+
+                       if (!memcmp(&fp->insn[fp->consts[i].hw_id], &map[pid*4],
+                                   4 * sizeof(float)))
+                               continue;
+
+                       memcpy(&fp->insn[fp->consts[i].hw_id], &map[pid*4],
+                              4 * sizeof(float));
+                       fp->on_hw = 0;
+               }
+               pipe->winsys->buffer_unmap(pipe->winsys,
+                                          nv40->fragprog.constant_buf);
+       }
+}
+
+static INLINE void
+nv40_state_update_vertprog(struct nv40_context *nv40)
+{
+       struct pipe_context *pipe = (struct pipe_context *)nv40;
+       struct nv40_vertex_program *vp = nv40->vertprog.vp;
+       float *map;
+       int i;
+
+       if (!nv40->vertprog.vp->translated)
+               nv40_vertprog_translate(nv40, nv40->vertprog.vp);
+
+       if (vp->num_consts) {
+               map = pipe->winsys->buffer_map(pipe->winsys,
+                                              nv40->vertprog.constant_buf,
+                                              PIPE_BUFFER_FLAG_READ);
+               for (i = 0; i < vp->num_consts; i++) {
+                       uint pid = vp->consts[i].pipe_id;
+
+                       if (pid >= 0) {
+                               if (!memcmp(vp->consts[i].value, &map[pid*4],
+                                           4 * sizeof(float)))
+                                       continue;
+                               memcpy(vp->consts[i].value, &map[pid*4],
+                                      4 * sizeof(float));
+                       }
+
+                       BEGIN_RING(curie, NV40TCL_VP_UPLOAD_CONST_ID, 5);
+                       OUT_RING  (vp->consts[i].hw_id);
+                       OUT_RINGp ((uint32_t *)vp->consts[i].value, 4);
+               }
+               pipe->winsys->buffer_unmap(pipe->winsys,
+                                          nv40->vertprog.constant_buf);
+       }
+}
+
+void
+nv40_emit_hw_state(struct nv40_context *nv40)
+{
+       if (nv40->dirty & NV40_NEW_FRAGPROG) {
+               struct nv40_fragment_program *cur = nv40->fragprog.fp;
+
+               nv40_state_update_fragprog(nv40);
+       
+               if (cur->on_hw)
+                       nv40->dirty &= ~NV40_NEW_FRAGPROG;
+
+               if (!cur->on_hw || cur != nv40->fragprog.active_fp)
+                       nv40_fragprog_bind(nv40, cur);
+       }
+
+       if (nv40->dirty & NV40_NEW_TEXTURE)
+               nv40_state_tex_update(nv40);
+
+       if (nv40->dirty & (NV40_NEW_TEXTURE | NV40_NEW_FRAGPROG)) {
+               BEGIN_RING(curie, NV40TCL_TEX_CACHE_CTL, 1);
+               OUT_RING  (2);
+               BEGIN_RING(curie, NV40TCL_TEX_CACHE_CTL, 1);
+               OUT_RING  (1);
+               nv40->dirty &= ~(NV40_NEW_TEXTURE | NV40_NEW_FRAGPROG);
+       }
+
+       if (nv40->dirty & NV40_NEW_VERTPROG) {
+               nv40_state_update_vertprog(nv40);
+               if (nv40->vertprog.vp != nv40->vertprog.active_vp)
+                       nv40_vertprog_bind(nv40, nv40->vertprog.vp);
+               nv40->dirty &= ~NV40_NEW_VERTPROG;
+       }
+
+       if (nv40->dirty & NV40_NEW_ARRAYS) {
+               nv40_vbo_arrays_update(nv40);
+               nv40->dirty &= ~NV40_NEW_ARRAYS;
+       }
+}
+

diff --git a/src/mesa/pipe/nv40/nv40_state_tex.c b/src/mesa/pipe/nv40/nv40_state_tex.c
new file mode 100644 (file)
index 0000000..a92d625
--- /dev/null
+++ b/src/mesa/pipe/nv40/nv40_state_tex.c
@@ -0,0 +1,140 @@
+#include "nv40_context.h"
+#include "nv40_dma.h"
+
+#define _(m,tf,ts0x,ts0y,ts0z,ts0w,ts1x,ts1y,ts1z,ts1w)                        \
+{                                                                              \
+  TRUE,                                                                        \
+  PIPE_FORMAT_##m,                                                             \
+  NV40TCL_TEX_FORMAT_FORMAT_##tf,                                              \
+  (NV40TCL_TEX_SWIZZLE_S0_X_##ts0x << NV40TCL_TEX_SWIZZLE_S0_X_SHIFT) |        \
+  (NV40TCL_TEX_SWIZZLE_S0_X_##ts0y << NV40TCL_TEX_SWIZZLE_S0_Y_SHIFT) |        \
+  (NV40TCL_TEX_SWIZZLE_S0_X_##ts0z << NV40TCL_TEX_SWIZZLE_S0_Z_SHIFT) |        \
+  (NV40TCL_TEX_SWIZZLE_S0_X_##ts0w << NV40TCL_TEX_SWIZZLE_S0_W_SHIFT) |        \
+  (NV40TCL_TEX_SWIZZLE_S1_X_##ts1x << NV40TCL_TEX_SWIZZLE_S1_X_SHIFT) |        \
+  (NV40TCL_TEX_SWIZZLE_S1_X_##ts1y << NV40TCL_TEX_SWIZZLE_S1_Y_SHIFT) |        \
+  (NV40TCL_TEX_SWIZZLE_S1_X_##ts1z << NV40TCL_TEX_SWIZZLE_S1_Z_SHIFT) |        \
+  (NV40TCL_TEX_SWIZZLE_S1_X_##ts1w << NV40TCL_TEX_SWIZZLE_S1_W_SHIFT),         \
+}
+
+struct nv40_texture_format {
+       boolean defined;
+       uint    pipe;
+       int     format;
+       int     swizzle;
+};
+
+static struct nv40_texture_format
+nv40_texture_formats[] = {
+       _(U_A8_R8_G8_B8, A8R8G8B8,   S1,   S1,   S1,   S1, X, Y, Z, W),
+       _(U_A1_R5_G5_B5, A1R5G5B5,   S1,   S1,   S1,   S1, X, Y, Z, W),
+       _(U_A4_R4_G4_B4, A4R4G4B4,   S1,   S1,   S1,   S1, X, Y, Z, W),
+       _(U_R5_G6_B5   , R5G6B5  ,   S1,   S1,   S1,  ONE, X, Y, Z, W),
+       _(U_L8         , L8      ,   S1,   S1,   S1,  ONE, X, X, X, X),
+       _(U_A8         , L8      , ZERO, ZERO, ZERO,   S1, X, X, X, X),
+       _(U_I8         , L8      ,   S1,   S1,   S1,   S1, X, X, X, X),
+       _(U_A8_L8      , A8L8    ,   S1,   S1,   S1,   S1, Z, W, X, Y),
+//     _(RGB_DXT1    , 0x86,   S1,   S1,   S1,  ONE, X, Y, Z, W, 0x00, 0x00),
+//     _(RGBA_DXT1   , 0x86,   S1,   S1,   S1,   S1, X, Y, Z, W, 0x00, 0x00),
+//     _(RGBA_DXT3   , 0x87,   S1,   S1,   S1,   S1, X, Y, Z, W, 0x00, 0x00),
+//     _(RGBA_DXT5   , 0x88,   S1,   S1,   S1,   S1, X, Y, Z, W, 0x00, 0x00),
+};
+
+static struct nv40_texture_format *
+nv40_tex_format(uint pipe_format)
+{
+       struct nv40_texture_format *tf = nv40_texture_formats;
+
+       while (tf->defined) {
+               if (tf->pipe == pipe_format)
+                       return tf;
+               tf++;
+       }
+
+       return NULL;
+}
+
+static INLINE int
+nv40_tex_dims(uint pipe_target)
+{
+       switch (pipe_target) {
+       case PIPE_TEXTURE_1D: return 1;
+       case PIPE_TEXTURE_2D: return 2;
+       case PIPE_TEXTURE_3D: return 3;
+       case PIPE_TEXTURE_CUBE: return 2;
+       default:
+               NOUVEAU_ERR("AII unknown pipe target: %d\n", pipe_target);
+               return 2;
+       }
+}
+
+static void
+nv40_tex_unit_enable(struct nv40_context *nv40, int unit)
+{
+       struct nouveau_winsys *nvws = nv40->nvws;
+       struct nv40_sampler_state *ps = nv40->tex_sampler[unit];
+       struct pipe_mipmap_tree *mt = nv40->tex_miptree[unit];
+       struct nv40_texture_format *tf;
+       uint32_t txf, txs, txp;
+       int swizzled = 0; /*XXX: implement in region code? */
+
+       tf = nv40_tex_format(mt->format);
+       if (!tf->defined) {
+               NOUVEAU_ERR("Unsupported texture format: 0x%x\n", mt->format);
+               return;
+       }
+
+       txf  = (tf->format | 0x80) << NV40TCL_TEX_FORMAT_FORMAT_SHIFT;
+       txf |= ((mt->last_level - mt->first_level + 1) <<
+               NV40TCL_TEX_FORMAT_MIPMAP_COUNT_SHIFT);
+       if (1) /* XXX */
+               txf |= NV40TCL_TEX_FORMAT_NO_BORDER;
+
+       txf |= (nv40_tex_dims(mt->target) << NV40TCL_TEX_FORMAT_DIMS_SHIFT);
+       if (0) /*XXX*/
+               txf |= NV40TCL_TEX_FORMAT_RECT;
+
+       if (swizzled) {
+               txp = 0;
+       } else {
+               txp  = mt->pitch * mt->cpp;
+               txf |= NV40TCL_TEX_FORMAT_LINEAR;
+       }
+
+       txs = tf->swizzle;
+       if (mt->format == PIPE_FORMAT_U_A8_L8)
+               txs |= (1<<16); /*nfi*/
+
+       BEGIN_RING(curie, NV40TCL_TEX_OFFSET(unit), 8);
+       OUT_RELOCl(mt->region->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART |
+                  NOUVEAU_BO_RD);
+       OUT_RELOCd(mt->region->buffer, txf, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART |
+                  NOUVEAU_BO_OR | NOUVEAU_BO_RD, NV40TCL_TEX_FORMAT_DMA0,
+                  NV40TCL_TEX_FORMAT_DMA1);
+       OUT_RING  (ps->wrap);
+       OUT_RING  (NV40TCL_TEX_ENABLE_ENABLE |
+                  (0x00078000) /* mipmap related? */);
+       OUT_RING  (txs);
+       OUT_RING  (ps->filt | 0x3fd6 /*voodoo*/);
+       OUT_RING  ((mt->width0 << NV40TCL_TEX_SIZE0_W_SHIFT) | mt->height0);
+       OUT_RING  (ps->bcol);
+       BEGIN_RING(curie, NV40TCL_TEX_SIZE1(unit), 1);
+       OUT_RING  ((mt->depth0 << NV40TCL_TEX_SIZE1_DEPTH_SHIFT) | txp);
+}
+
+void
+nv40_state_tex_update(struct nv40_context *nv40)
+{
+       while (nv40->tex_dirty) {
+               int unit = ffs(nv40->tex_dirty) - 1;
+
+               if (nv40->tex_miptree[unit]) {
+                       nv40_tex_unit_enable(nv40, unit);
+               } else {
+                       BEGIN_RING(curie, NV40TCL_TEX_ENABLE(unit), 1);
+                       OUT_RING  (0);
+               }
+
+               nv40->tex_dirty &= ~(1 << unit);
+       }
+}
+

diff --git a/src/mesa/pipe/nv40/nv40_surface.c b/src/mesa/pipe/nv40/nv40_surface.c
new file mode 100644 (file)
index 0000000..84e0d79
--- /dev/null
+++ b/src/mesa/pipe/nv40/nv40_surface.c
@@ -0,0 +1,229 @@
+
+/**************************************************************************
+ * 
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ * 
+ **************************************************************************/
+
+#include "nv40_context.h"
+#include "pipe/p_defines.h"
+#include "pipe/p_util.h"
+#include "pipe/p_winsys.h"
+#include "pipe/p_inlines.h"
+
+
+#define CLIP_TILE \
+   do { \
+      if (x >= ps->width) \
+         return; \
+      if (y >= ps->height) \
+         return; \
+      if (x + w > ps->width) \
+         w = ps->width - x; \
+      if (y + h > ps->height) \
+         h = ps->height -y; \
+   } while(0)
+
+
+/**
+ * Note: this is exactly like a8r8g8b8_get_tile() in sp_surface.c
+ * Share it someday.
+ */
+static void
+nv40_get_tile_rgba(struct pipe_context *pipe,
+                   struct pipe_surface *ps,
+                   uint x, uint y, uint w, uint h, float *p)
+{
+   const unsigned *src
+      = ((const unsigned *) (ps->region->map + ps->offset))
+      + y * ps->region->pitch + x;
+   unsigned i, j;
+   unsigned w0 = w;
+
+   CLIP_TILE;
+
+   switch (ps->format) {
+   case PIPE_FORMAT_U_A8_R8_G8_B8:
+      for (i = 0; i < h; i++) {
+         float *pRow = p;
+         for (j = 0; j < w; j++) {
+            const unsigned pixel = src[j];
+            pRow[0] = UBYTE_TO_FLOAT((pixel >> 16) & 0xff);
+            pRow[1] = UBYTE_TO_FLOAT((pixel >>  8) & 0xff);
+            pRow[2] = UBYTE_TO_FLOAT((pixel >>  0) & 0xff);
+            pRow[3] = UBYTE_TO_FLOAT((pixel >> 24) & 0xff);
+            pRow += 4;
+         }
+         src += ps->region->pitch;
+         p += w0 * 4;
+      }
+      break;
+   case PIPE_FORMAT_S8_Z24:
+      {
+         const float scale = 1.0 / (float) 0xffffff;
+         for (i = 0; i < h; i++) {
+            float *pRow = p;
+            for (j = 0; j < w; j++) {
+               const unsigned pixel = src[j];
+               pRow[0] =
+               pRow[1] =
+               pRow[2] =
+               pRow[3] = (pixel & 0xffffff) * scale;
+               pRow += 4;
+            }
+            src += ps->region->pitch;
+            p += w0 * 4;
+         }
+      }
+      break;
+   default:
+      assert(0);
+   }
+}
+
+
+static void
+nv40_put_tile_rgba(struct pipe_context *pipe,
+                   struct pipe_surface *ps,
+                   uint x, uint y, uint w, uint h, const float *p)
+{
+   /* TODO */
+   assert(0);
+}
+
+
+/*
+ * XXX note: same as code in sp_surface.c
+ */
+static void
+nv40_get_tile(struct pipe_context *pipe,
+              struct pipe_surface *ps,
+              uint x, uint y, uint w, uint h,
+              void *p, int dst_stride)
+{
+   const uint cpp = ps->region->cpp;
+   const uint w0 = w;
+   const ubyte *pSrc;
+   ubyte *pDest;
+   uint i;
+
+   assert(ps->region->map);
+
+   CLIP_TILE;
+
+   if (dst_stride == 0) {
+      dst_stride = w0 * cpp;
+   }
+
+   pSrc = ps->region->map + ps->offset + (y * ps->region->pitch + x) * cpp;
+   pDest = (ubyte *) p;
+
+   for (i = 0; i < h; i++) {
+      memcpy(pDest, pSrc, w0 * cpp);
+      pDest += dst_stride;
+      pSrc += ps->region->pitch * cpp;
+   }
+}
+
+
+/*
+ * XXX note: same as code in sp_surface.c
+ */
+static void
+nv40_put_tile(struct pipe_context *pipe,
+              struct pipe_surface *ps,
+              uint x, uint y, uint w, uint h,
+              const void *p, int src_stride)
+{
+   const uint cpp = ps->region->cpp;
+   const uint w0 = w;
+   const ubyte *pSrc;
+   ubyte *pDest;
+   uint i;
+
+   assert(ps->region->map);
+
+   CLIP_TILE;
+
+   if (src_stride == 0) {
+      src_stride = w0 * cpp;
+   }
+
+   pSrc = (const ubyte *) p;
+   pDest = ps->region->map + ps->offset + (y * ps->region->pitch + x) * cpp;
+
+   for (i = 0; i < h; i++) {
+      memcpy(pDest, pSrc, w0 * cpp);
+      pDest += ps->region->pitch * cpp;
+      pSrc += src_stride;
+   }
+}
+
+
+/*
+ * XXX note: same as code in sp_surface.c
+ */
+static struct pipe_surface *
+nv40_get_tex_surface(struct pipe_context *pipe,
+                     struct pipe_mipmap_tree *mt,
+                     unsigned face, unsigned level, unsigned zslice)
+{
+   struct pipe_surface *ps;
+   unsigned offset;  /* in bytes */
+
+   offset = mt->level[level].level_offset;
+
+   if (mt->target == PIPE_TEXTURE_CUBE) {
+      offset += mt->level[level].image_offset[face] * mt->cpp;
+   }
+   else if (mt->target == PIPE_TEXTURE_3D) {
+      offset += mt->level[level].image_offset[zslice] * mt->cpp;
+   }
+   else {
+      assert(face == 0);
+      assert(zslice == 0);
+   }
+
+   ps = pipe->winsys->surface_alloc(pipe->winsys, mt->format);
+   if (ps) {
+      assert(ps->format);
+      assert(ps->refcount);
+      pipe_region_reference(&ps->region, mt->region);
+      ps->width = mt->level[level].width;
+      ps->height = mt->level[level].height;
+      ps->offset = offset;
+   }
+   return ps;
+}
+
+
+void
+nv40_init_surface_functions(struct nv40_context *nv40)
+{
+   nv40->pipe.get_tex_surface = nv40_get_tex_surface;
+   nv40->pipe.get_tile = nv40_get_tile;
+   nv40->pipe.put_tile = nv40_put_tile;
+   nv40->pipe.get_tile_rgba = nv40_get_tile_rgba;
+   nv40->pipe.put_tile_rgba = nv40_put_tile_rgba;
+}

diff --git a/src/mesa/pipe/nv40/nv40_vbo.c b/src/mesa/pipe/nv40/nv40_vbo.c
new file mode 100644 (file)
index 0000000..aa93047
--- /dev/null
+++ b/src/mesa/pipe/nv40/nv40_vbo.c
@@ -0,0 +1,222 @@
+#include "pipe/p_context.h"
+#include "pipe/p_state.h"
+#include "pipe/p_util.h"
+
+#include "nv40_context.h"
+#include "nv40_dma.h"
+#include "nv40_state.h"
+#include "nvgl_pipe.h"
+
+boolean
+nv40_draw_arrays(struct pipe_context *pipe, unsigned mode, unsigned start,
+                unsigned count)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       unsigned nr;
+
+       if (nv40->dirty)
+               nv40_emit_hw_state(nv40);
+
+       BEGIN_RING(curie, NV40TCL_BEGIN_END, 1);
+       OUT_RING  (nvgl_primitive(mode));
+
+       nr = (count & 0xff);
+       if (nr) {
+               BEGIN_RING(curie, NV40TCL_VB_VERTEX_BATCH, 1);
+               OUT_RING  (((nr - 1) << 24) | start);
+               start += nr;
+       }
+
+       /*XXX: large arrays (nr>2047) will blow up */
+       nr = count >> 8;
+       if (nr) {
+               assert (nr <= 2047);
+
+               BEGIN_RING_NI(curie, NV40TCL_VB_VERTEX_BATCH, nr);
+               while (nr--) {
+                       OUT_RING(((0x100 - 1) << 24) | start);
+                       start += 0x100;
+               }
+       }
+
+       BEGIN_RING(curie, NV40TCL_BEGIN_END, 1);
+       OUT_RING  (0);
+
+       pipe->flush(pipe, PIPE_FLUSH_WAIT);
+       return TRUE;
+}
+
+static INLINE void
+nv40_draw_elements_u08(struct nv40_context *nv40, void *ib,
+                      unsigned start, unsigned count)
+{
+       uint8_t *elts = (uint8_t *)ib + start;
+       int push, i;
+
+       if (count & 1) {
+               BEGIN_RING(curie, NV40TCL_VB_ELEMENT_U32, 1);
+               OUT_RING  (elts[0]);
+               elts++; count--;
+       }
+
+       while (count) {
+               push = MIN2(count, 2046);
+
+               BEGIN_RING_NI(curie, NV40TCL_VB_ELEMENT_U16, push);
+               for (i = 0; i < push; i+=2)
+                       OUT_RING((elts[i+1] << 16) | elts[i]);
+
+               count -= push;
+               elts  += push;
+       }
+}
+
+static INLINE void
+nv40_draw_elements_u16(struct nv40_context *nv40, void *ib,
+                      unsigned start, unsigned count)
+{
+       uint16_t *elts = (uint16_t *)ib + start;
+       int push, i;
+
+       if (count & 1) {
+               BEGIN_RING(curie, NV40TCL_VB_ELEMENT_U32, 1);
+               OUT_RING  (elts[0]);
+               elts++; count--;
+       }
+
+       while (count) {
+               push = MIN2(count, 2046);
+
+               BEGIN_RING_NI(curie, NV40TCL_VB_ELEMENT_U16, push);
+               for (i = 0; i < push; i+=2)
+                       OUT_RING((elts[i+1] << 16) | elts[i]);
+
+               count -= push;
+               elts  += push;
+       }
+}
+
+static INLINE void
+nv40_draw_elements_u32(struct nv40_context *nv40, void *ib,
+                      unsigned start, unsigned count)
+{
+       uint32_t *elts = (uint32_t *)ib + start;
+       int push;
+
+       while (count) {
+               push = MIN2(count, 2047);
+
+               BEGIN_RING_NI(curie, NV40TCL_VB_ELEMENT_U32, push);
+               OUT_RINGp    (elts, push);
+
+               count -= push;
+               elts  += push;
+       }
+}
+
+boolean
+nv40_draw_elements(struct pipe_context *pipe,
+                  struct pipe_buffer_handle *indexBuffer, unsigned indexSize,
+                  unsigned mode, unsigned start, unsigned count)
+{
+       struct nv40_context *nv40 = (struct nv40_context *)pipe;
+       void *ib;
+
+       if (nv40->dirty)
+               nv40_emit_hw_state(nv40);
+
+       ib = pipe->winsys->buffer_map(pipe->winsys, indexBuffer,
+                                     PIPE_BUFFER_FLAG_READ);
+       if (!ib) {
+               NOUVEAU_ERR("Couldn't map index buffer!!\n");
+               return FALSE;
+       }
+
+       BEGIN_RING(curie, NV40TCL_BEGIN_END, 1);
+       OUT_RING  (nvgl_primitive(mode));
+
+       switch (indexSize) {
+       case 1:
+               nv40_draw_elements_u08(nv40, ib, start, count);
+               break;
+       case 2:
+               nv40_draw_elements_u16(nv40, ib, start, count);
+               break;
+       case 4:
+               nv40_draw_elements_u32(nv40, ib, start, count);
+               break;
+       default:
+               NOUVEAU_ERR("unsupported elt size %d\n", indexSize);
+               break;
+       }
+
+       BEGIN_RING(curie, NV40TCL_BEGIN_END, 1);
+       OUT_RING  (0);
+
+       pipe->winsys->buffer_unmap(pipe->winsys, ib);
+       pipe->flush(pipe, PIPE_FLUSH_WAIT);
+       return TRUE;
+}
+
+static INLINE int
+nv40_vbo_format_to_ncomp(uint format)
+{
+       switch (format) {
+       case PIPE_FORMAT_R32G32B32A32_FLOAT: return 4;
+       case PIPE_FORMAT_R32G32B32_FLOAT: return 3;
+       case PIPE_FORMAT_R32G32_FLOAT: return 2;
+       case PIPE_FORMAT_R32_FLOAT: return 1;
+       default:
+              NOUVEAU_ERR("AII, unknown vbo format %d\n", format);
+              return 1;
+       }
+}
+
+void
+nv40_vbo_arrays_update(struct nv40_context *nv40)
+{
+       struct nouveau_winsys *nvws = nv40->nvws;
+       struct nv40_vertex_program *vp = nv40->vertprog.vp;
+       uint32_t inputs, vtxfmt[16];
+       int hw, num_hw;
+
+       inputs = vp->ir;
+       for (hw = 0; hw < 16 && inputs; hw++) {
+               if (inputs & (1 << hw)) {
+                       num_hw = hw;
+                       inputs &= ~(1 << hw);
+               }
+       }
+       num_hw++;
+
+       inputs = vp->ir;
+       BEGIN_RING(curie, NV40TCL_VTXBUF_ADDRESS(0), num_hw);
+       for (hw = 0; hw < num_hw; hw++) {
+               struct pipe_vertex_element *ve;
+               struct pipe_vertex_buffer *vb;
+
+               if (!(inputs & (1 << hw))) {
+                       OUT_RING(0);
+                       vtxfmt[hw] = NV40TCL_VTXFMT_TYPE_FLOAT;
+                       continue;
+               }
+
+               ve = &nv40->vtxelt[hw];
+               vb = &nv40->vtxbuf[ve->vertex_buffer_index];
+
+               OUT_RELOC(vb->buffer, vb->buffer_offset + ve->src_offset,
+                         NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_LOW |
+                         NOUVEAU_BO_OR | NOUVEAU_BO_RD, 0,
+                         NV40TCL_VTXBUF_ADDRESS_DMA1);
+               vtxfmt[hw] = ((vb->pitch << NV40TCL_VTXFMT_STRIDE_SHIFT) |
+                             (nv40_vbo_format_to_ncomp(ve->src_format) <<
+                              NV40TCL_VTXFMT_SIZE_SHIFT) |
+                             NV40TCL_VTXFMT_TYPE_FLOAT);
+       }
+
+       BEGIN_RING(curie, 0x1710, 1);
+       OUT_RING  (0); /* vtx cache flush */
+       BEGIN_RING(curie, NV40TCL_VTXFMT(0), num_hw);
+       OUT_RINGp (vtxfmt, num_hw);
+}
+

diff --git a/src/mesa/pipe/nv40/nv40_vertprog.c b/src/mesa/pipe/nv40/nv40_vertprog.c
new file mode 100644 (file)
index 0000000..be550e4
--- /dev/null
+++ b/src/mesa/pipe/nv40/nv40_vertprog.c
@@ -0,0 +1,594 @@
+#include "pipe/p_context.h"
+#include "pipe/p_defines.h"
+#include "pipe/p_state.h"
+
+#include "pipe/tgsi/exec/tgsi_token.h"
+#include "pipe/tgsi/exec/tgsi_parse.h"
+
+#include "nv40_context.h"
+#include "nv40_dma.h"
+#include "nv40_state.h"
+
+#define SWZ_X 0
+#define SWZ_Y 1
+#define SWZ_Z 2
+#define SWZ_W 3
+#define MASK_X 8
+#define MASK_Y 4
+#define MASK_Z 2
+#define MASK_W 1
+#define MASK_ALL (MASK_X|MASK_Y|MASK_Z|MASK_W)
+#define DEF_SCALE 0
+#define DEF_CTEST 0
+#include "nv40_shader.h"
+
+#define swz(s,x,y,z,w) nv40_sr_swz((s), SWZ_##x, SWZ_##y, SWZ_##z, SWZ_##w)
+#define neg(s) nv40_sr_neg((s))
+#define abs(s) nv40_sr_abs((s))
+
+static uint32_t
+passthrough_vp_data[] = {
+       0x40041c6c, 0x0040010d, 0x8106c083, 0x6041ff84,
+       0x40041c6c, 0x0040000d, 0x8106c083, 0x6041ff81,
+};
+
+static struct nv40_vertex_program
+passthrough_vp = {
+       .pipe = NULL,
+       .translated = TRUE,
+       
+       .insn     = passthrough_vp_data,
+       .insn_len = sizeof(passthrough_vp_data) / sizeof(uint32_t),
+
+       .ir = 0x00000003,
+       .or = 0x00000001,
+};
+
+struct nv40_vpc {
+       struct nv40_vertex_program *vp;
+
+       uint output_map[PIPE_MAX_SHADER_OUTPUTS];
+
+       int high_temp;
+       int temp_temp_count;
+};
+
+static INLINE struct nv40_sreg
+nv40_sr_temp(struct nv40_vpc *vpc)
+{
+       int idx;
+
+       idx  = vpc->temp_temp_count++;
+       idx += vpc->high_temp;
+       return nv40_sr(0, NV40_VP_SRC_REG_TYPE_TEMP, idx);
+}
+
+static INLINE struct nv40_sreg
+nv40_sr_const(struct nv40_vpc *vpc, int pipe,
+             float x, float y, float z, float w)
+{
+       struct nv40_vertex_program *vp = vpc->vp;
+       int idx = vp->num_consts;
+
+       vp->consts[idx].pipe_id  = pipe;
+       vp->consts[idx].hw_id    = idx;
+       vp->consts[idx].value[0] = x;
+       vp->consts[idx].value[1] = y;
+       vp->consts[idx].value[2] = z;
+       vp->consts[idx].value[3] = w;
+       vp->num_consts++;
+
+       return nv40_sr(0, NV40_VP_SRC_REG_TYPE_CONST, idx);
+}
+
+#define arith(cc,s,o,d,m,s0,s1,s2) \
+       nv40_vp_arith((cc), (s), NV40_VP_INST_##o, (d), (m), (s0), (s1), (s2))
+#define temp(vpc) nv40_sr_temp((vpc))
+#define constant(v,p,x,y,z,w) nv40_sr_const((v), (p), (x), (y), (z), (w))
+
+static void
+emit_src(struct nv40_vpc *vpc, uint32_t *hw, int pos, struct nv40_sreg src)
+{
+       struct nv40_vertex_program *vp = vpc->vp;
+       uint32_t sr = 0;
+
+       sr |= (src.type << NV40_VP_SRC_REG_TYPE_SHIFT);
+       if (src.type == NV40_VP_SRC_REG_TYPE_INPUT) {
+               vp->ir |= (1 << src.index);
+               hw[1] |= (src.index << NV40_VP_INST_INPUT_SRC_SHIFT);
+       } else
+       if (src.type == NV40_VP_SRC_REG_TYPE_CONST) {
+               hw[1] |= (src.index << NV40_VP_INST_CONST_SRC_SHIFT);
+       } else {
+               sr |= (src.index << NV40_VP_SRC_TEMP_SRC_SHIFT);
+       }
+
+       if (src.negate)
+               sr |= NV40_VP_SRC_NEGATE;
+
+       if (src.abs)
+               hw[0] |= (1 << (21 + pos));
+
+       sr |= ((src.swz[0] << NV40_VP_SRC_SWZ_X_SHIFT) |
+              (src.swz[1] << NV40_VP_SRC_SWZ_Y_SHIFT) |
+              (src.swz[2] << NV40_VP_SRC_SWZ_Z_SHIFT) |
+              (src.swz[3] << NV40_VP_SRC_SWZ_W_SHIFT));
+
+       switch (pos) {
+       case 0:
+               hw[1] |= ((sr & NV40_VP_SRC0_HIGH_MASK) >>
+                         NV40_VP_SRC0_HIGH_SHIFT) << NV40_VP_INST_SRC0H_SHIFT;
+               hw[2] |= (sr & NV40_VP_SRC0_LOW_MASK) <<
+                         NV40_VP_INST_SRC0L_SHIFT;
+               break;
+       case 1:
+               hw[2] |= sr << NV40_VP_INST_SRC1_SHIFT;
+               break;
+       case 2:
+               hw[2] |= ((sr & NV40_VP_SRC2_HIGH_MASK) >>
+                         NV40_VP_SRC2_HIGH_SHIFT) << NV40_VP_INST_SRC2H_SHIFT;
+               hw[3] |= (sr & NV40_VP_SRC2_LOW_MASK) <<
+                         NV40_VP_INST_SRC2L_SHIFT;
+               break;
+       default:
+               assert(0);
+       }
+}
+
+static void
+emit_dst(struct nv40_vpc *vpc, uint32_t *hw, int slot, struct nv40_sreg dst)
+{
+       struct nv40_vertex_program *vp = vpc->vp;
+
+       if (dst.output == 0) {
+               hw[3] |= NV40_VP_INST_DEST_MASK;
+               if (slot == 0) {
+                       hw[0] |= (dst.index <<
+                                 NV40_VP_INST_VEC_DEST_TEMP_SHIFT);
+               } else {
+                       hw[3] |= (dst.index <<
+                                 NV40_VP_INST_SCA_DEST_TEMP_SHIFT);
+               }
+       } else {
+               switch (dst.index) {
+               case NV40_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
+               case NV40_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
+               case NV40_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
+               case NV40_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
+               case NV40_VP_INST_DEST_FOGC : vp->or |= (1 << 4); break;
+               case NV40_VP_INST_DEST_PSZ  : vp->or |= (1 << 5); break;
+               case NV40_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
+               case NV40_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
+               case NV40_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
+               case NV40_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
+               case NV40_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
+               case NV40_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
+               case NV40_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
+               case NV40_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
+               default:
+                    break;
+               }
+
+               hw[3] |= (dst.index << NV40_VP_INST_DEST_SHIFT);
+               if (slot == 0) {
+                       hw[0] |= NV40_VP_INST_VEC_RESULT;
+                       hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK;
+               } else {
+                       hw[3] |= NV40_VP_INST_SCA_RESULT;
+                       hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
+               }
+       }
+}
+
+static void
+nv40_vp_arith(struct nv40_vpc *vpc, int slot, int op,
+             struct nv40_sreg dst, int mask,
+             struct nv40_sreg s0, struct nv40_sreg s1,
+             struct nv40_sreg s2)
+{
+       struct nv40_vertex_program *vp = vpc->vp;
+       uint32_t *hw = &vp->insn[vp->insn_len];
+
+       hw[0] |= (NV40_VP_INST_COND_TR << NV40_VP_INST_COND_SHIFT);
+       hw[0] |= ((0 << NV40_VP_INST_COND_SWZ_X_SHIFT) |
+                 (1 << NV40_VP_INST_COND_SWZ_Y_SHIFT) |
+                 (2 << NV40_VP_INST_COND_SWZ_Z_SHIFT) |
+                 (3 << NV40_VP_INST_COND_SWZ_W_SHIFT));
+
+       if (slot == 0) {
+               hw[1] |= (op << NV40_VP_INST_VEC_OPCODE_SHIFT);
+               hw[3] |= (NV40_VP_INST_SCA_RESULT |
+                         NV40_VP_INST_SCA_DEST_TEMP_MASK);
+               hw[3] |= (mask << NV40_VP_INST_VEC_WRITEMASK_SHIFT);
+       } else {
+               hw[1] |= (op << NV40_VP_INST_SCA_OPCODE_SHIFT);
+               hw[1] |= (NV40_VP_INST_VEC_DEST_TEMP_MASK | (1 << 20));
+               hw[3] |= (mask << NV40_VP_INST_SCA_WRITEMASK_SHIFT);
+       }
+
+       emit_dst(vpc, hw, slot, dst);
+       emit_src(vpc, hw, 0, s0);
+       emit_src(vpc, hw, 1, s1);
+       emit_src(vpc, hw, 2, s2);
+
+       vp->insn_len += 4;
+}
+
+static INLINE struct nv40_sreg
+tgsi_src(struct nv40_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
+       struct nv40_sreg src;
+
+       switch (fsrc->SrcRegister.File) {
+       case TGSI_FILE_INPUT:
+               src = nv40_sr(0, NV40_VP_SRC_REG_TYPE_INPUT,
+                             fsrc->SrcRegister.Index);
+               break;
+       case TGSI_FILE_CONSTANT:
+               src = constant(vpc, fsrc->SrcRegister.Index, 0, 0, 0, 0);
+               break;
+       case TGSI_FILE_TEMPORARY:
+               if (vpc->high_temp < fsrc->SrcRegister.Index)
+                       vpc->high_temp = fsrc->SrcRegister.Index;
+               src = nv40_sr(0, NV40_VP_SRC_REG_TYPE_TEMP,
+                             fsrc->SrcRegister.Index);
+               break;
+       default:
+               NOUVEAU_ERR("bad src file\n");
+               break;
+       }
+
+       src.abs = fsrc->SrcRegisterExtMod.Absolute;
+       src.negate = fsrc->SrcRegister.Negate;
+       src.swz[0] = fsrc->SrcRegister.SwizzleX;
+       src.swz[1] = fsrc->SrcRegister.SwizzleY;
+       src.swz[2] = fsrc->SrcRegister.SwizzleZ;
+       src.swz[3] = fsrc->SrcRegister.SwizzleW;
+       return src;
+}
+
+static INLINE struct nv40_sreg
+tgsi_dst(struct nv40_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
+       uint out, idx;
+
+       switch (fdst->DstRegister.File) {
+       case TGSI_FILE_OUTPUT:
+               out = 1;
+               idx = vpc->output_map[fdst->DstRegister.Index];
+               break;
+       case TGSI_FILE_TEMPORARY:
+               out = 0;
+               idx = fdst->DstRegister.Index;
+               if (vpc->high_temp < idx)
+                       vpc->high_temp = idx;
+               break;
+       default:
+               NOUVEAU_ERR("bad dst file\n");
+               break;
+       }
+
+       return nv40_sr(out, NV40_VP_SRC_REG_TYPE_TEMP, idx);
+}
+
+static INLINE int
+tgsi_mask(uint tgsi)
+{
+       int mask = 0;
+
+       if (tgsi & TGSI_WRITEMASK_X) mask |= MASK_X;
+       if (tgsi & TGSI_WRITEMASK_Y) mask |= MASK_Y;
+       if (tgsi & TGSI_WRITEMASK_Z) mask |= MASK_Z;
+       if (tgsi & TGSI_WRITEMASK_W) mask |= MASK_W;
+       return mask;
+}
+
+static boolean
+nv40_vertprog_parse_instruction(struct nv40_vpc *vpc,
+                               const struct tgsi_full_instruction *finst)
+{
+       struct nv40_sreg src[3], dst, tmp;
+       struct nv40_sreg none = nv40_sr(0, NV40_VP_SRC_REG_TYPE_INPUT, 0);
+       int mask;
+       int ai = -1, ci = -1;
+       int i;
+
+       if (finst->Instruction.Opcode == TGSI_OPCODE_RET)
+               return TRUE;
+
+       vpc->temp_temp_count = 0;
+       for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
+               const struct tgsi_full_src_register *fsrc;
+
+               fsrc = &finst->FullSrcRegisters[i];
+               if (fsrc->SrcRegister.File == TGSI_FILE_TEMPORARY) {
+                       src[i] = tgsi_src(vpc, fsrc);
+               }
+       }
+
+       for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
+               const struct tgsi_full_src_register *fsrc;
+
+               fsrc = &finst->FullSrcRegisters[i];
+               switch (fsrc->SrcRegister.File) {
+               case TGSI_FILE_INPUT:
+                       if (ai == -1 || ai == fsrc->SrcRegister.Index) {
+                               ai = fsrc->SrcRegister.Index;
+                               src[i] = tgsi_src(vpc, fsrc);
+                       } else {
+                               NOUVEAU_MSG("extra src attr %d\n",
+                                        fsrc->SrcRegister.Index);
+                               src[i] = temp(vpc);
+                               arith(vpc, 0, OP_MOV, src[i], MASK_ALL,
+                                     tgsi_src(vpc, fsrc), none, none);
+                       }
+                       break;
+               case TGSI_FILE_CONSTANT:
+                       if (ci == -1 || ci == fsrc->SrcRegister.Index) {
+                               ci = fsrc->SrcRegister.Index;
+                               src[i] = tgsi_src(vpc, fsrc);
+                       } else {
+                               src[i] = temp(vpc);
+                               arith(vpc, 0, OP_MOV, src[i], MASK_ALL,
+                                     tgsi_src(vpc, fsrc), none, none);
+                       }
+                       break;
+               case TGSI_FILE_TEMPORARY:
+                       /* handled above */
+                       break;
+               default:
+                       NOUVEAU_ERR("bad src file\n");
+                       return FALSE;
+               }
+       }
+
+       dst  = tgsi_dst(vpc, &finst->FullDstRegisters[0]);
+       mask = tgsi_mask(finst->FullDstRegisters[0].DstRegister.WriteMask);
+
+       switch (finst->Instruction.Opcode) {
+       case TGSI_OPCODE_ABS:
+               arith(vpc, 0, OP_MOV, dst, mask, abs(src[0]), none, none);
+               break;
+       case TGSI_OPCODE_ADD:
+               arith(vpc, 0, OP_ADD, dst, mask, src[0], none, src[1]);
+               break;
+       case TGSI_OPCODE_ARL:
+               arith(vpc, 0, OP_ARL, dst, mask, src[0], none, none);
+               break;
+       case TGSI_OPCODE_DP3:
+               arith(vpc, 0, OP_DP3, dst, mask, src[0], src[1], none);
+               break;
+       case TGSI_OPCODE_DP4:
+               arith(vpc, 0, OP_DP4, dst, mask, src[0], src[1], none);
+               break;
+       case TGSI_OPCODE_DPH:
+               arith(vpc, 0, OP_DPH, dst, mask, src[0], src[1], none);
+               break;
+       case TGSI_OPCODE_DST:
+               arith(vpc, 0, OP_DST, dst, mask, src[0], src[1], none);
+               break;
+       case TGSI_OPCODE_EX2:
+               arith(vpc, 1, OP_EX2, dst, mask, none, none, src[0]);
+               break;
+       case TGSI_OPCODE_EXP:
+               arith(vpc, 1, OP_EXP, dst, mask, none, none, src[0]);
+               break;
+       case TGSI_OPCODE_FLR:
+               arith(vpc, 0, OP_FLR, dst, mask, src[0], none, none);
+               break;
+       case TGSI_OPCODE_FRC:
+               arith(vpc, 0, OP_FRC, dst, mask, src[0], none, none);
+               break;
+       case TGSI_OPCODE_LG2:
+               arith(vpc, 1, OP_LG2, dst, mask, none, none, src[0]);
+               break;
+       case TGSI_OPCODE_LIT:
+               arith(vpc, 1, OP_LIT, dst, mask, none, none, src[0]);
+               break;
+       case TGSI_OPCODE_LOG:
+               arith(vpc, 1, OP_LOG, dst, mask, none, none, src[0]);
+               break;
+       case TGSI_OPCODE_MAD:
+               arith(vpc, 0, OP_MAD, dst, mask, src[0], src[1], src[2]);
+               break;
+       case TGSI_OPCODE_MAX:
+               arith(vpc, 0, OP_MAX, dst, mask, src[0], src[1], none);
+               break;
+       case TGSI_OPCODE_MIN:
+               arith(vpc, 0, OP_MIN, dst, mask, src[0], src[1], none);
+               break;
+       case TGSI_OPCODE_MOV:
+               arith(vpc, 0, OP_MOV, dst, mask, src[0], none, none);
+               break;
+       case TGSI_OPCODE_MUL:
+               arith(vpc, 0, OP_MUL, dst, mask, src[0], src[1], none);
+               break;
+       case TGSI_OPCODE_POW:
+               tmp = temp(vpc);
+               arith(vpc, 1, OP_LG2, tmp, MASK_X, none, none,
+                     swz(src[0], X, X, X, X));
+               arith(vpc, 0, OP_MUL, tmp, MASK_X, swz(tmp, X, X, X, X),
+                     swz(src[1], X, X, X, X), none);
+               arith(vpc, 1, OP_EX2, dst, mask, none, none,
+                     swz(tmp, X, X, X, X));
+               break;
+       case TGSI_OPCODE_RCP:
+               arith(vpc, 1, OP_RCP, dst, mask, none, none, src[0]);
+               break;
+       case TGSI_OPCODE_RSQ:
+               arith(vpc, 1, OP_RSQ, dst, mask, none, none, src[0]);
+               break;
+       case TGSI_OPCODE_SGE:
+               arith(vpc, 0, OP_SGE, dst, mask, src[0], src[1], none);
+               break;
+       case TGSI_OPCODE_SLT:
+               arith(vpc, 0, OP_SLT, dst, mask, src[0], src[1], none);
+               break;
+       case TGSI_OPCODE_SUB:
+               arith(vpc, 0, OP_ADD, dst, mask, src[0], none, neg(src[1]));
+               break;
+       case TGSI_OPCODE_XPD:
+               tmp = temp(vpc);
+               arith(vpc, 0, OP_MUL, tmp, mask,
+                     swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
+               arith(vpc, 0, OP_MAD, dst, (mask & ~MASK_W),
+                     swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
+                     neg(tmp));
+               break;
+       default:
+               NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
+               return FALSE;
+       }
+
+       return TRUE;
+}
+
+static boolean
+nv40_vertprog_parse_decl_output(struct nv40_vpc *vpc,
+                               const struct tgsi_full_declaration *fdec)
+{
+       int hw;
+
+       switch (fdec->Semantic.SemanticName) {
+       case TGSI_SEMANTIC_POSITION:
+               hw = NV40_VP_INST_DEST_POS;
+               break;
+       case TGSI_SEMANTIC_COLOR:
+               if (fdec->Semantic.SemanticIndex == 0) {
+                       hw = NV40_VP_INST_DEST_COL0;
+               } else
+               if (fdec->Semantic.SemanticIndex == 1) {
+                       hw = NV40_VP_INST_DEST_COL1;
+               } else {
+                       NOUVEAU_ERR("bad colour semantic index\n");
+                       return FALSE;
+               }
+               break;
+       case TGSI_SEMANTIC_BCOLOR:
+               if (fdec->Semantic.SemanticIndex == 0) {
+                       hw = NV40_VP_INST_DEST_BFC0;
+               } else
+               if (fdec->Semantic.SemanticIndex == 1) {
+                       hw = NV40_VP_INST_DEST_BFC1;
+               } else {
+                       NOUVEAU_ERR("bad bcolour semantic index\n");
+                       return FALSE;
+               }
+               break;
+       case TGSI_SEMANTIC_FOG:
+               hw = NV40_VP_INST_DEST_FOGC;
+               break;
+       case TGSI_SEMANTIC_PSIZE:
+               hw = NV40_VP_INST_DEST_PSZ;
+               break;
+       case TGSI_SEMANTIC_GENERIC:
+               if (fdec->Semantic.SemanticIndex <= 7) {
+                       hw = NV40_VP_INST_DEST_TC(fdec->Semantic.SemanticIndex);
+               } else {
+                       NOUVEAU_ERR("bad generic semantic index\n");
+                       return FALSE;
+               }
+               break;
+       default:
+               NOUVEAU_ERR("bad output semantic\n");
+               return FALSE;
+       }
+
+       vpc->output_map[fdec->u.DeclarationRange.First] = hw;
+       return TRUE;
+}
+
+void
+nv40_vertprog_translate(struct nv40_context *nv40,
+                       struct nv40_vertex_program *vp)
+{
+       struct tgsi_parse_context parse;
+       struct nv40_vpc *vpc = NULL;
+
+       vpc = calloc(1, sizeof(struct nv40_vpc));
+       if (!vpc)
+               return;
+       vp->insn = calloc(1, 128*4*sizeof(uint32_t));
+       vpc->vp = vp;
+       vpc->high_temp = -1;
+
+       tgsi_parse_init(&parse, vp->pipe->tokens);
+
+       while (!tgsi_parse_end_of_tokens(&parse)) {
+               tgsi_parse_token(&parse);
+
+               switch (parse.FullToken.Token.Type) {
+               case TGSI_TOKEN_TYPE_DECLARATION:
+               {
+                       const struct tgsi_full_declaration *fdec;
+                       fdec = &parse.FullToken.FullDeclaration;
+                       switch (fdec->Declaration.File) {
+                       case TGSI_FILE_OUTPUT:
+                               if (!nv40_vertprog_parse_decl_output(vpc, fdec))
+                                       goto out_err;
+                               break;
+                       default:
+                               break;
+                       }
+               }
+                       break;
+               case TGSI_TOKEN_TYPE_IMMEDIATE:
+                       break;
+               case TGSI_TOKEN_TYPE_INSTRUCTION:
+               {
+                       const struct tgsi_full_instruction *finst;
+
+                       finst = &parse.FullToken.FullInstruction;
+                       if (!nv40_vertprog_parse_instruction(vpc, finst))
+                               goto out_err;
+               }
+                       break;
+               default:
+                       break;
+               }
+       }
+
+       vp->insn[vp->insn_len - 1] |= NV40_VP_INST_LAST;
+#if 0
+       {
+               int i;
+               for (i = 0; i < vp->insn_len; i++)
+                       NOUVEAU_ERR("inst[%d] = 0x%08x\n", i, vp->insn[i]);
+       }
+#endif
+       vp->translated = TRUE;
+out_err:
+       tgsi_parse_free(&parse);
+       free(vpc);
+}
+
+void
+nv40_vertprog_bind(struct nv40_context *nv40, struct nv40_vertex_program *vp)
+{ 
+       int i;
+
+       if (!vp->translated) {
+               NOUVEAU_ERR("vtxprog invalid, using passthrough shader\n");
+               vp = &passthrough_vp;
+       }
+
+       if (!vp->on_hw) {
+               if (nv40->vertprog.active_vp)
+                       nv40->vertprog.active_vp->on_hw = FALSE;
+               vp->on_hw    = TRUE;
+               vp->start_ip = 0;
+
+               BEGIN_RING(curie, NV40TCL_VP_UPLOAD_FROM_ID, 1);
+               OUT_RING  (vp->start_ip);
+               for (i = 0; i < vp->insn_len; i += 4) {
+                       BEGIN_RING(curie, NV40TCL_VP_UPLOAD_INST(0), 4);
+                       OUT_RINGp (&vp->insn[i], 4);
+               }
+       }
+
+       BEGIN_RING(curie, NV40TCL_VP_START_FROM_ID, 1);
+       OUT_RING  (vp->start_ip);
+       BEGIN_RING(curie, NV40TCL_VP_ATTRIB_EN, 2);
+       OUT_RING  (vp->ir);
+       OUT_RING  (vp->or);
+
+       nv40->vertprog.active_vp = vp;
+}

diff --git a/src/mesa/pipe/nv40/nvgl_pipe.h b/src/mesa/pipe/nv40/nvgl_pipe.h
new file mode 100644 (file)
index 0000000..15ff318
--- /dev/null
+++ b/src/mesa/pipe/nv40/nvgl_pipe.h
@@ -0,0 +1,198 @@
+#ifndef __NVGL_PIPE_H__
+#define __NVGL_PIPE_H__
+
+#include <GL/gl.h>
+
+static INLINE unsigned
+nvgl_blend_func(unsigned factor)
+{
+       switch (factor) {
+       case PIPE_BLENDFACTOR_ONE:
+               return GL_ONE;
+       case PIPE_BLENDFACTOR_SRC_COLOR:
+               return GL_SRC_COLOR;
+       case PIPE_BLENDFACTOR_SRC_ALPHA:
+               return GL_SRC_ALPHA;
+       case PIPE_BLENDFACTOR_DST_ALPHA:
+               return GL_DST_ALPHA;
+       case PIPE_BLENDFACTOR_DST_COLOR:
+               return GL_DST_COLOR;
+       case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
+               return GL_SRC_ALPHA_SATURATE;
+       case PIPE_BLENDFACTOR_CONST_COLOR:
+               return GL_CONSTANT_COLOR;
+       case PIPE_BLENDFACTOR_CONST_ALPHA:
+               return GL_CONSTANT_ALPHA;
+       case PIPE_BLENDFACTOR_ZERO:
+               return GL_ZERO;
+       case PIPE_BLENDFACTOR_INV_SRC_COLOR:
+               return GL_ONE_MINUS_SRC_COLOR;
+       case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
+               return GL_ONE_MINUS_SRC_ALPHA;
+       case PIPE_BLENDFACTOR_INV_DST_ALPHA:
+               return GL_ONE_MINUS_DST_ALPHA;
+       case PIPE_BLENDFACTOR_INV_DST_COLOR:
+               return GL_ONE_MINUS_DST_COLOR;
+       case PIPE_BLENDFACTOR_INV_CONST_COLOR:
+               return GL_ONE_MINUS_CONSTANT_COLOR;
+       case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
+               return GL_ONE_MINUS_CONSTANT_ALPHA;
+       default:
+               return GL_ONE;
+       }
+}
+
+static INLINE unsigned
+nvgl_blend_eqn(unsigned func)
+{
+       switch (func) {
+       case PIPE_BLEND_ADD:
+               return GL_FUNC_ADD;
+       case PIPE_BLEND_SUBTRACT:
+               return GL_FUNC_SUBTRACT;
+       case PIPE_BLEND_REVERSE_SUBTRACT:
+               return GL_FUNC_REVERSE_SUBTRACT;
+       case PIPE_BLEND_MIN:
+               return GL_MIN;
+       case PIPE_BLEND_MAX:
+               return GL_MAX;
+       default:
+               return GL_FUNC_ADD;
+       }
+}
+
+static INLINE unsigned
+nvgl_logicop_func(unsigned func)
+{
+       switch (func) {
+       case PIPE_LOGICOP_CLEAR:
+               return GL_CLEAR;
+       case PIPE_LOGICOP_NOR:
+               return GL_NOR;
+       case PIPE_LOGICOP_AND_INVERTED:
+               return GL_AND_INVERTED;
+       case PIPE_LOGICOP_COPY_INVERTED:
+               return GL_COPY_INVERTED;
+       case PIPE_LOGICOP_AND_REVERSE:
+               return GL_AND_REVERSE;
+       case PIPE_LOGICOP_INVERT:
+               return GL_INVERT;
+       case PIPE_LOGICOP_XOR:
+               return GL_XOR;
+       case PIPE_LOGICOP_NAND:
+               return GL_NAND;
+       case PIPE_LOGICOP_AND:
+               return GL_AND;
+       case PIPE_LOGICOP_EQUIV:
+               return GL_EQUIV;
+       case PIPE_LOGICOP_NOOP:
+               return GL_NOOP;
+       case PIPE_LOGICOP_OR_INVERTED:
+               return GL_OR_INVERTED;
+       case PIPE_LOGICOP_COPY:
+               return GL_COPY;
+       case PIPE_LOGICOP_OR_REVERSE:
+               return GL_OR_REVERSE;
+       case PIPE_LOGICOP_OR:
+               return GL_OR;
+       case PIPE_LOGICOP_SET:
+               return GL_SET;
+       default:
+               return GL_CLEAR;
+       }
+}
+
+static INLINE unsigned
+nvgl_comparison_op(unsigned op)
+{
+       switch (op) {
+       case PIPE_FUNC_NEVER:
+               return GL_NEVER;
+       case PIPE_FUNC_LESS:
+               return GL_LESS;
+       case PIPE_FUNC_EQUAL:
+               return GL_EQUAL;
+       case PIPE_FUNC_LEQUAL:
+               return GL_LEQUAL;
+       case PIPE_FUNC_GREATER:
+               return GL_GREATER;
+       case PIPE_FUNC_NOTEQUAL:
+               return GL_NOTEQUAL;
+       case PIPE_FUNC_GEQUAL:
+               return GL_GEQUAL;
+       case PIPE_FUNC_ALWAYS:
+               return GL_ALWAYS;
+       default:
+               return GL_NEVER;
+       }
+}
+
+static INLINE unsigned
+nvgl_polygon_mode(unsigned mode)
+{
+       switch (mode) {
+       case PIPE_POLYGON_MODE_FILL:
+               return GL_FILL;
+       case PIPE_POLYGON_MODE_LINE:
+               return GL_LINE;
+       case PIPE_POLYGON_MODE_POINT:
+               return GL_POINT;
+       default:
+               return GL_FILL;
+       }
+}
+
+static INLINE unsigned
+nvgl_stencil_op(unsigned op)
+{
+       switch (op) {
+       case PIPE_STENCIL_OP_KEEP:
+               return GL_KEEP;
+       case PIPE_STENCIL_OP_ZERO:
+               return GL_ZERO;
+       case PIPE_STENCIL_OP_REPLACE:
+               return GL_REPLACE;
+       case PIPE_STENCIL_OP_INCR:
+               return GL_INCR;
+       case PIPE_STENCIL_OP_DECR:
+               return GL_DECR;
+       case PIPE_STENCIL_OP_INCR_WRAP:
+               return GL_INCR_WRAP;
+       case PIPE_STENCIL_OP_DECR_WRAP:
+               return GL_DECR_WRAP;
+       case PIPE_STENCIL_OP_INVERT:
+               return GL_INVERT;
+       default:
+               return GL_KEEP;
+       }
+}
+
+static INLINE unsigned
+nvgl_primitive(unsigned prim) {
+       switch (prim) {
+       case PIPE_PRIM_POINTS:
+               return GL_POINTS + 1;
+       case PIPE_PRIM_LINES:
+               return GL_LINES + 1;
+       case PIPE_PRIM_LINE_LOOP:
+               return GL_LINE_LOOP + 1;
+       case PIPE_PRIM_LINE_STRIP:
+               return GL_LINE_STRIP + 1;
+       case PIPE_PRIM_TRIANGLES:
+               return GL_TRIANGLES + 1;
+       case PIPE_PRIM_TRIANGLE_STRIP:
+               return GL_TRIANGLE_STRIP + 1;
+       case PIPE_PRIM_TRIANGLE_FAN:
+               return GL_TRIANGLE_FAN + 1;
+       case PIPE_PRIM_QUADS:
+               return GL_QUADS + 1;
+       case PIPE_PRIM_QUAD_STRIP:
+               return GL_QUAD_STRIP + 1;
+       case PIPE_PRIM_POLYGON:
+               return GL_POLYGON + 1;
+       default:
+               return GL_POINTS + 1;
+       }
+}
+
+#endif