pickInitiatingNode();
changeAddress(address);
m_pc = pc;
- m_access_mode = AccessModeType(random() % AccessModeType_NUM);
+ m_access_mode = RubyAccessMode(random() % RubyAccessMode_NUM);
m_store_count = 0;
}
#include <iostream>
#include "cpu/testers/rubytest/RubyTester.hh"
-#include "mem/protocol/AccessModeType.hh"
+#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/TesterStatus.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Global.hh"
NodeID m_initiatingNode;
Address m_address;
Address m_pc;
- AccessModeType m_access_mode;
+ RubyAccessMode m_access_mode;
int m_num_cpu_sequencers;
RubyTester* m_tester_ptr;
};
structure(RequestMsg, desc="...", interface="NetworkMessage") {
Address Address, desc="Physical address for this request";
CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
- AccessModeType AccessMode, desc="user/supervisor access type";
+ RubyAccessMode AccessMode, desc="user/supervisor access type";
MachineID Requestor , desc="What component request";
NetDest Destination, desc="What components receive the request, includes MachineType and num";
MessageSizeType MessageSize, desc="size category of the message";
DataBlock DataBlk, desc="data for the cache line (DMA WRITE request)";
int Acks, desc="How many acks to expect";
MessageSizeType MessageSize, desc="size category of the message";
- AccessModeType AccessMode, desc="user/supervisor access type";
+ RubyAccessMode AccessMode, desc="user/supervisor access type";
PrefetchBit Prefetch, desc="Is this a prefetch request";
}
AccessType AccessType, desc="Type of request (used for profiling)";
Time IssueTime, desc="Time the request was issued";
- AccessModeType AccessMode, desc="user/supervisor access type";
+ RubyAccessMode AccessMode, desc="user/supervisor access type";
PrefetchBit Prefetch, desc="Is this a prefetch request";
}
out_msg.Destination.add(map_Address_to_Directory(address));
out_msg.MessageSize := MessageSizeType:Persistent_Control;
out_msg.Prefetch := PrefetchBit:No;
- out_msg.AccessMode := AccessModeType:SupervisorMode;
+ out_msg.AccessMode := RubyAccessMode:Supervisor;
}
markPersistentEntries(address);
starving := true;
out_msg.RetryNum := 0;
out_msg.MessageSize := MessageSizeType:Broadcast_Control;
out_msg.Prefetch := PrefetchBit:No;
- out_msg.AccessMode := AccessModeType:SupervisorMode;
+ out_msg.AccessMode := RubyAccessMode:Supervisor;
}
}
}
out_msg.Destination.add(map_Address_to_Directory(address));
out_msg.MessageSize := MessageSizeType:Persistent_Control;
out_msg.Prefetch := PrefetchBit:No;
- out_msg.AccessMode := AccessModeType:SupervisorMode;
+ out_msg.AccessMode := RubyAccessMode:Supervisor;
}
markPersistentEntries(address);
starving := true;
out_msg.RetryNum := 0;
out_msg.MessageSize := MessageSizeType:Broadcast_Control;
out_msg.Prefetch := PrefetchBit:No;
- out_msg.AccessMode := AccessModeType:SupervisorMode;
+ out_msg.AccessMode := RubyAccessMode:Supervisor;
}
}
}
MachineID Requestor, desc="Node who initiated the request";
NetDest Destination, desc="Destination set";
MessageSizeType MessageSize, desc="size category of the message";
- AccessModeType AccessMode, desc="user/supervisor access type";
+ RubyAccessMode AccessMode, desc="user/supervisor access type";
PrefetchBit Prefetch, desc="Is this a prefetch request";
}
bool isLocal, desc="Is this request from a local L1";
int RetryNum, desc="retry sequence number";
MessageSizeType MessageSize, desc="size category of the message";
- AccessModeType AccessMode, desc="user/supervisor access type";
+ RubyAccessMode AccessMode, desc="user/supervisor access type";
PrefetchBit Prefetch, desc="Is this a prefetch request";
}
Write, desc="Writing to cache";
}
-// AccessModeType
-enumeration(AccessModeType, default="AccessModeType_UserMode", desc="...") {
- SupervisorMode, desc="Supervisor mode";
- UserMode, desc="User mode";
+// RubyAccessMode
+enumeration(RubyAccessMode, default="RubyAccessMode_User", desc="...") {
+ Supervisor, desc="Supervisor mode";
+ User, desc="User mode";
+ Device, desc="Device mode";
}
enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") {
Address PhysicalAddress, desc="Physical address for this request";
CacheRequestType Type, desc="Type of request (LD, ST, etc)";
Address ProgramCounter, desc="Program counter of the instruction that caused the miss";
- AccessModeType AccessMode, desc="user/supervisor access type";
+ RubyAccessMode AccessMode, desc="user/supervisor access type";
int Size, desc="size in bytes of access";
PrefetchBit Prefetch, desc="Is this a prefetch request";
}
Address PhysicalAddress, desc="Physical address for this request";
SequencerRequestType Type, desc="Type of request (LD, ST, etc)";
Address ProgramCounter, desc="Program counter of the instruction that caused the miss";
- AccessModeType AccessMode, desc="user/supervisor access type";
+ RubyAccessMode AccessMode, desc="user/supervisor access type";
DataBlock DataBlk, desc="Data";
int Len, desc="size in bytes of access";
PrefetchBit Prefetch, desc="Is this a prefetch request";
void profileMiss(CacheMsg);
void profileGenericRequest(GenericRequestType,
- AccessModeType,
+ RubyAccessMode,
PrefetchBit);
void setMRU(Address);
void
AccessTraceForAddress::update(CacheRequestType type,
- AccessModeType access_mode, NodeID cpu,
+ RubyAccessMode access_mode, NodeID cpu,
bool sharing_miss)
{
m_touched_by.add(cpu);
// ERROR_MSG("Trying to add invalid access to trace");
}
- if (access_mode == AccessModeType_UserMode) {
+ if (access_mode == RubyAccessMode_User) {
m_user++;
}
#include <iostream>
-#include "mem/protocol/AccessModeType.hh"
+#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Global.hh"
~AccessTraceForAddress();
void setAddress(const Address& addr) { m_addr = addr; }
- void update(CacheRequestType type, AccessModeType access_mode, NodeID cpu,
+ void update(CacheRequestType type, RubyAccessMode access_mode, NodeID cpu,
bool sharing_miss);
int getTotal() const;
int getSharing() const { return m_sharing; }
m_getx_sharing_histogram.add(num_indirections);
bool indirection_miss = (num_indirections > 0);
- addTraceSample(datablock, PC, CacheRequestType_ST, AccessModeType(0),
+ addTraceSample(datablock, PC, CacheRequestType_ST, RubyAccessMode(0),
requestor, indirection_miss);
}
m_gets_sharing_histogram.add(num_indirections);
bool indirection_miss = (num_indirections > 0);
- addTraceSample(datablock, PC, CacheRequestType_LD, AccessModeType(0),
+ addTraceSample(datablock, PC, CacheRequestType_LD, RubyAccessMode(0),
requestor, indirection_miss);
}
void
AddressProfiler::addTraceSample(Address data_addr, Address pc_addr,
CacheRequestType type,
- AccessModeType access_mode, NodeID id,
+ RubyAccessMode access_mode, NodeID id,
bool sharing_miss)
{
if (m_all_instructions) {
void clearStats();
void addTraceSample(Address data_addr, Address pc_addr,
- CacheRequestType type, AccessModeType access_mode,
+ CacheRequestType type, RubyAccessMode access_mode,
NodeID id, bool sharing_miss);
void profileRetry(const Address& data_addr, AccessType type, int count);
void profileGetX(const Address& datablock, const Address& PC,
out << endl;
- for (int i = 0; i < AccessModeType_NUM; i++){
+ for (int i = 0; i < RubyAccessMode_NUM; i++){
if (m_accessModeTypeHistogram[i] > 0) {
out << description << "_access_mode_type_"
- << (AccessModeType) i << ": "
+ << (RubyAccessMode) i << ": "
<< m_accessModeTypeHistogram[i] << " "
<< 100.0 * m_accessModeTypeHistogram[i] / requests
<< "%" << endl;
m_prefetches = 0;
m_sw_prefetches = 0;
m_hw_prefetches = 0;
- for (int i = 0; i < AccessModeType_NUM; i++) {
+ for (int i = 0; i < RubyAccessMode_NUM; i++) {
m_accessModeTypeHistogram[i] = 0;
}
}
void
CacheProfiler::addCacheStatSample(CacheRequestType requestType,
- AccessModeType accessType,
+ RubyAccessMode accessType,
PrefetchBit pfBit)
{
m_cacheRequestType[requestType]++;
void
CacheProfiler::addGenericStatSample(GenericRequestType requestType,
- AccessModeType accessType,
+ RubyAccessMode accessType,
PrefetchBit pfBit)
{
m_genericRequestType[requestType]++;
}
void
-CacheProfiler::addStatSample(AccessModeType accessType,
+CacheProfiler::addStatSample(RubyAccessMode accessType,
PrefetchBit pfBit)
{
m_misses++;
#include <string>
#include <vector>
-#include "mem/protocol/AccessModeType.hh"
+#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/GenericRequestType.hh"
#include "mem/protocol/PrefetchBit.hh"
void clearStats();
void addCacheStatSample(CacheRequestType requestType,
- AccessModeType type,
+ RubyAccessMode type,
PrefetchBit pfBit);
void addGenericStatSample(GenericRequestType requestType,
- AccessModeType type,
+ RubyAccessMode type,
PrefetchBit pfBit);
void print(std::ostream& out) const;
// Private copy constructor and assignment operator
CacheProfiler(const CacheProfiler& obj);
CacheProfiler& operator=(const CacheProfiler& obj);
- void addStatSample(AccessModeType type, PrefetchBit pfBit);
+ void addStatSample(RubyAccessMode type, PrefetchBit pfBit);
std::string m_description;
int64 m_misses;
int64 m_prefetches;
int64 m_sw_prefetches;
int64 m_hw_prefetches;
- int64 m_accessModeTypeHistogram[AccessModeType_NUM];
+ int64 m_accessModeTypeHistogram[RubyAccessMode_NUM];
std::vector<int> m_cacheRequestType;
std::vector<int> m_genericRequestType;
#include <vector>
#include "base/hashmap.hh"
-#include "mem/protocol/AccessModeType.hh"
+#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/AccessType.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/GenericMachineType.hh"
#include <ostream>
#include "mem/packet.hh"
-#include "mem/protocol/AccessModeType.hh"
+#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/Message.hh"
#include "mem/protocol/PrefetchBit.hh"
RubyRequestType_NUM
};
-enum RubyAccessMode {
- RubyAccessMode_User,
- RubyAccessMode_Supervisor,
- RubyAccessMode_Device
-};
-
class RubyRequest
{
public:
void
CacheMemory::profileGenericRequest(GenericRequestType requestType,
- AccessModeType accessType,
+ RubyAccessMode accessType,
PrefetchBit pfBit)
{
m_profiler_ptr->addGenericStatSample(requestType,
void profileMiss(const CacheMsg & msg);
void profileGenericRequest(GenericRequestType requestType,
- AccessModeType accessType,
+ RubyAccessMode accessType,
PrefetchBit pfBit);
void getMemoryValue(const Address& addr, char* value,
assert(0);
}
- AccessModeType amtype;
+ RubyAccessMode amtype;
switch(request.access_mode){
case RubyAccessMode_User:
- amtype = AccessModeType_UserMode;
+ amtype = RubyAccessMode_User;
break;
case RubyAccessMode_Supervisor:
- amtype = AccessModeType_SupervisorMode;
+ amtype = RubyAccessMode_Supervisor;
break;
case RubyAccessMode_Device:
- amtype = AccessModeType_UserMode;
+ amtype = RubyAccessMode_User;
break;
default:
assert(0);
#if 0
bool
Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type,
- AccessModeType access_mode,
+ RubyAccessMode access_mode,
int size, DataBlock*& data_ptr)
{
CacheMemory *cache =
#include <iostream>
#include "base/hashmap.hh"
-#include "mem/protocol/AccessModeType.hh"
+#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/GenericMachineType.hh"
#include "mem/protocol/PrefetchBit.hh"
private:
bool tryCacheAccess(const Address& addr, CacheRequestType type,
- const Address& pc, AccessModeType access_mode,
+ const Address& pc, RubyAccessMode access_mode,
int size, DataBlock*& data_ptr);
void issueRequest(const RubyRequest& request);