(no commit message)

diff --git a/openpower/sv/compliancy_levels.mdwn b/openpower/sv/compliancy_levels.mdwn
index 809de7f4aee9080d2e287d5c19506c0c293b3ab5..adadccb217f961eeb32cd5ba97c209bef81ca8e8 100644 (file)
--- a/openpower/sv/compliancy_levels.mdwn
+++ b/openpower/sv/compliancy_levels.mdwn
@@ -48,7 +48,7 @@ permitted to declare meeting the 3D/Advanced Level unless implementing
 # Ultra-Embedded Level
 
 This level exists as an entry-level into SVP64, most suited to resource
-constrained soft cores, or Hardware implementations where cost is a
+constrained soft cores, or Hardware implementations where cost is a much
 higher priority than execution speed.
 
 This level sets the bare minimum requirements, where everything with the
@@ -91,8 +91,9 @@ to the required total 128.
 Another important aspect is that when Rc=1 is set, CR Field Vector co-results
 are produced. Should these exceed CR7 (CR8-CR127) and the number of CR Fields
 has not been increased to 128 then an Illegal Instruction Trap must be
-raised.  In practical terms, to avoid this scenario, MAXVL should not
-exceed 8 for Arithmetic or Logical operations, when Rc=1.
+raised.  In practical terms, to avoid this occurrence in software,
+MAXVL should not
+exceed 8 for Arithmetic or Logical operations with Rc=1.
 
 Zeroing on source and destination for Predicates
 must also be supported (sz, dz) however
@@ -101,9 +102,11 @@ Iteration/Reduction) are entirely optional. Implementation of Element-Width
 Overrides is also optional.
 
 One of the important side-benefits of this SV Compliancy Level is that it
-brings Hardware-level support for Predication to the entire Scalar Power
+brings Hardware-level support for Scalar Predication (VL=MAXVL=1)
+to the entire Scalar Power
 ISA, completely without
-modifying the Scalar Power ISA.  The cost is that instructions are Prefixed
+modifying the Scalar Power ISA.  The cost in software is that Predicated
+instructions are Prefixed
 to 64-bit.
 
 # DSP / Audio / Video Level
@@ -120,3 +123,15 @@ assist with Audio/Video.
 It is not mandatory for this Level to have DCT/FFT REMAP Capability but
 due to the high prevalence of DCT and FFT in Audio, Video and DSP
 workloads it is strongly recommended.
+
+# 3D / Advanced / Supercomputing
+
+This Compliancy Level is for highest performance and energy efficiency.
+All aspects of SVP64 must be entirely implemented, in full, in Hardware.
+How that is achieved is entirely at the discretion of the implementor:
+there are no hard requirements of any kind on the level of performance,
+just as there are none in the Vulkan Specification. Throughout the SV
+Specification however there are hints to Micro-Architects: byte-level
+write-enable lines on Register Files is strongly recommended, for
+example.
+