Merge remote-tracking branch 'origin/master' into xaig_dff

diff --cc backends/aiger/xaiger.cc
Simple merge

diff --cc frontends/aiger/aigerparse.cc
index 6fd9e0432ee34a2497caa235767660fd0998ed94,ac9e31f70b58d2a879a8ee7e00ba5439b0bd4027..cb4ec618317a291c30a04a17b008e2aa0e4a0e85
--- 1/frontends/aiger/aigerparse.cc
--- 2/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@@ -428,9 -428,8 +428,9 @@@ void AigerReader::parse_xaiger(const di
                                }
                        }
                        else if (c == 'r') {
-                               uint32_t dataSize = parse_xaiger_literal(f);
+                               uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
                                flopNum = parse_xaiger_literal(f);
 +                              log_debug("flopNum: %u\n", flopNum);
                                log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
                                f.ignore(flopNum * sizeof(uint32_t));
                        }
@@@ -449,10 -448,10 +449,10 @@@
                                log_debug("coNum = %u\n", coNum);
                                piNum = parse_xaiger_literal(f);
                                log_debug("piNum = %u\n", piNum);
-                               uint32_t poNum = parse_xaiger_literal(f);
+                               uint32_t poNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
                                log_debug("poNum = %u\n", poNum);
                                uint32_t boxNum = parse_xaiger_literal(f);
 -                              log_debug("boxNum = %u\n", poNum);
 +                              log_debug("boxNum = %u\n", boxNum);
                                for (unsigned i = 0; i < boxNum; i++) {
                                        f.ignore(2*sizeof(uint32_t));
                                        uint32_t boxUniqueId = parse_xaiger_literal(f);

diff --cc passes/techmap/abc9.cc
index d52be1836f2a8e4ef3d7679749c7124faebdcf8f,c1d4fff2d33d85168d3e442292632fa89f4b83c8..398df190cd5af25c9047bf15ef3b8f1e342369b6
--- 1/passes/techmap/abc9.cc
--- 2/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@@ -570,17 -576,19 +570,17 @@@ void abc9_module(RTLIL::Design *design
                dict<SigBit, std::vector<RTLIL::Cell*>> bit2sinks;
  
                std::map<IdString, int> cell_stats;
 -              for (auto c : mapped_mod->cells())
 +              for (auto mapped_cell : mapped_mod->cells())
                {
 -                      toposort.node(c->name);
 +                      toposort.node(mapped_cell->name);
  
                        RTLIL::Cell *cell = nullptr;
 -                      if (c->type == ID($_NOT_)) {
 -                              RTLIL::SigBit a_bit = c->getPort(ID::A);
 -                              RTLIL::SigBit y_bit = c->getPort(ID::Y);
 -                              bit_users[a_bit].insert(c->name);
 -                              bit_drivers[y_bit].insert(c->name);
 +                      if (mapped_cell->type == ID($_NOT_)) {
-                               RTLIL::SigBit a_bit = mapped_cell->getPort(ID(A));
-                               RTLIL::SigBit y_bit = mapped_cell->getPort(ID(Y));
++                              RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A);
++                              RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y);
  
                                if (!a_bit.wire) {
-                                       mapped_cell->setPort(ID(Y), module->addWire(NEW_ID));
 -                                      c->setPort(ID::Y, module->addWire(NEW_ID));
++                                      mapped_cell->setPort(ID::Y, module->addWire(NEW_ID));
                                        RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
                                        log_assert(wire);
                                        module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
@@@ -608,27 -616,27 +608,27 @@@
                                                                RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
                                                                RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
                                                                RTLIL::Const::from_string("01"));
-                                               bit2sinks[cell->getPort(ID(A))].push_back(cell);
+                                               bit2sinks[cell->getPort(ID::A)].push_back(cell);
                                                cell_stats[ID($lut)]++;
 +                                              bit_users[a_bit].insert(mapped_cell->name);
 +                                              bit_drivers[y_bit].insert(mapped_cell->name);
                                        }
                                        else
 -                                              not2drivers[c] = driver_lut;
 +                                              not2drivers[mapped_cell] = driving_lut;
                                        continue;
                                }
 -                              else
 -                                      log_abort();
                                if (cell && markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
                                continue;
                        }
 -                      cell_stats[c->type]++;
 +                      cell_stats[mapped_cell->type]++;
  
                        RTLIL::Cell *existing_cell = nullptr;
 -                      if (c->type == ID($lut)) {
 -                              if (GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
 -                                      SigSpec my_a = module->wires_.at(remap_name(c->getPort(ID::A).as_wire()->name));
 -                                      SigSpec my_y = module->wires_.at(remap_name(c->getPort(ID::Y).as_wire()->name));
 +                      if (mapped_cell->type == ID($lut)) {
-                               if (GetSize(mapped_cell->getPort(ID(A))) == 1 && mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
-                                       SigSpec my_a = module->wires_.at(remap_name(mapped_cell->getPort(ID(A)).as_wire()->name));
-                                       SigSpec my_y = module->wires_.at(remap_name(mapped_cell->getPort(ID(Y)).as_wire()->name));
++                              if (GetSize(mapped_cell->getPort(ID::A)) == 1 && mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
++                                      SigSpec my_a = module->wires_.at(remap_name(mapped_cell->getPort(ID::A).as_wire()->name));
++                                      SigSpec my_y = module->wires_.at(remap_name(mapped_cell->getPort(ID::Y).as_wire()->name));
                                        module->connect(my_y, my_a);
 -                                      if (markgroups) c->attributes[ID(abcgroup)] = map_autoidx;
 +                                      if (markgroups) mapped_cell->attributes[ID(abcgroup)] = map_autoidx;
                                        log_abort();
                                        continue;
                                }
@@@ -736,21 -739,7 +736,21 @@@
                                for (auto driver_cell : bit_drivers.at(it.first))
                                for (auto user_cell : it.second)
                                        toposort.edge(driver_cell, user_cell);
-               bool no_loops = toposort.sort();
 +#if 0
 +              toposort.analyze_loops = true;
 +#endif
+               bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
 +#if 0
 +              unsigned i = 0;
 +              for (auto &it : toposort.loops) {
 +                      log("  loop %d\n", i++);
 +                      for (auto cell_name : it) {
 +                              auto cell = mapped_mod->cell(cell_name);
 +                              log_assert(cell);
 +                              log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
 +                      }
 +              }
 +#endif
                log_assert(no_loops);
  
                for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {