soc/interconnect/stream/SyncFIFO: expose fifo level

diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py
index f0a7810122a8190d49cc938ec48eb7e89835dddc..89231d1ddb7d3c018c955dafda162fc79bcd9b24 100644 (file)
--- a/litex/soc/interconnect/stream.py
+++ b/litex/soc/interconnect/stream.py
@@ -113,6 +113,7 @@ class SyncFIFO(_FIFOWrapper):
             self,
             fifo.SyncFIFOBuffered if buffered else fifo.SyncFIFO,
             layout, depth)
+        self.level = self.fifo.level
 
 
 class AsyncFIFO(_FIFOWrapper):

diff --git a/litex/soc/interconnect/stream_packet.py b/litex/soc/interconnect/stream_packet.py
index cf2309c7ba6bd02d3760b5318bbc394d117d03a0..6a4e2d4f2799c41ff2fa6a742c5ad7128c0422d1 100644 (file)
--- a/litex/soc/interconnect/stream_packet.py
+++ b/litex/soc/interconnect/stream_packet.py
@@ -379,6 +379,6 @@ class Buffer(Module):
         # compute almost full
         if almost_full is not None:
             self.almost_full = Signal()
-            self.comb += self.almost_full.eq(data_fifo.fifo.level > almost_full)
+            self.comb += self.almost_full.eq(data_fifo.level > almost_full)
 
 # XXX