union tex_tile_address addr, int x, int y)
{
const struct softpipe_tex_cached_tile *tile;
- addr.bits.x = x / TILE_SIZE;
- addr.bits.y = y / TILE_SIZE;
- y %= TILE_SIZE;
- x %= TILE_SIZE;
+ addr.bits.x = x / TEX_TILE_SIZE;
+ addr.bits.y = y / TEX_TILE_SIZE;
+ y %= TEX_TILE_SIZE;
+ x %= TEX_TILE_SIZE;
tile = sp_get_cached_tile_tex(sp_sview->cache, addr);
{
const struct softpipe_tex_cached_tile *tile;
- addr.bits.x = x / TILE_SIZE;
- addr.bits.y = y / TILE_SIZE;
- y %= TILE_SIZE;
- x %= TILE_SIZE;
+ addr.bits.x = x / TEX_TILE_SIZE;
+ addr.bits.y = y / TEX_TILE_SIZE;
+ y %= TEX_TILE_SIZE;
+ x %= TEX_TILE_SIZE;
tile = sp_get_cached_tile_tex(sp_sview->cache, addr);
{
const struct softpipe_tex_cached_tile *tile;
- addr.bits.x = x / TILE_SIZE;
- addr.bits.y = y / TILE_SIZE;
+ addr.bits.x = x / TEX_TILE_SIZE;
+ addr.bits.y = y / TEX_TILE_SIZE;
addr.bits.z = z;
- y %= TILE_SIZE;
- x %= TILE_SIZE;
+ y %= TEX_TILE_SIZE;
+ x %= TEX_TILE_SIZE;
tile = sp_get_cached_tile_tex(sp_sview->cache, addr);
{
unsigned xpot = pot_level_size(sp_sview->xpot, level);
unsigned ypot = pot_level_size(sp_sview->ypot, level);
- unsigned xmax = (xpot - 1) & (TILE_SIZE - 1); /* MIN2(TILE_SIZE, xpot) - 1; */
- unsigned ymax = (ypot - 1) & (TILE_SIZE - 1); /* MIN2(TILE_SIZE, ypot) - 1; */
+ unsigned xmax = (xpot - 1) & (TEX_TILE_SIZE - 1); /* MIN2(TEX_TILE_SIZE, xpot) - 1; */
+ unsigned ymax = (ypot - 1) & (TEX_TILE_SIZE - 1); /* MIN2(TEX_TILE_SIZE, ypot) - 1; */
union tex_tile_address addr;
int c;
uint pos;
/* make sure max texture size works */
- assert((TILE_SIZE << TEX_ADDR_BITS) >= (1 << (SP_MAX_TEXTURE_2D_LEVELS-1)));
+ assert((TEX_TILE_SIZE << TEX_ADDR_BITS) >= (1 << (SP_MAX_TEXTURE_2D_LEVELS-1)));
tc = CALLOC_STRUCT( softpipe_tex_tile_cache );
if (tc) {
if (addr.value != tile->addr.value) {
- /* cache miss. Most misses are because we've invaldiated the
+ /* cache miss. Most misses are because we've invalidated the
* texture cache previously -- most commonly on binding a new
* texture. Currently we effectively flush the cache on texture
* bind.
*/
if (!zs && util_format_is_pure_uint(tc->format)) {
pipe_get_tile_ui_format(tc->tex_trans, tc->tex_trans_map,
- addr.bits.x * TILE_SIZE,
- addr.bits.y * TILE_SIZE,
- TILE_SIZE,
- TILE_SIZE,
+ addr.bits.x * TEX_TILE_SIZE,
+ addr.bits.y * TEX_TILE_SIZE,
+ TEX_TILE_SIZE,
+ TEX_TILE_SIZE,
tc->format,
(unsigned *) tile->data.colorui);
} else if (!zs && util_format_is_pure_sint(tc->format)) {
pipe_get_tile_i_format(tc->tex_trans, tc->tex_trans_map,
- addr.bits.x * TILE_SIZE,
- addr.bits.y * TILE_SIZE,
- TILE_SIZE,
- TILE_SIZE,
+ addr.bits.x * TEX_TILE_SIZE,
+ addr.bits.y * TEX_TILE_SIZE,
+ TEX_TILE_SIZE,
+ TEX_TILE_SIZE,
tc->format,
(int *) tile->data.colori);
} else {
pipe_get_tile_rgba_format(tc->tex_trans, tc->tex_trans_map,
- addr.bits.x * TILE_SIZE,
- addr.bits.y * TILE_SIZE,
- TILE_SIZE,
- TILE_SIZE,
+ addr.bits.x * TEX_TILE_SIZE,
+ addr.bits.y * TEX_TILE_SIZE,
+ TEX_TILE_SIZE,
+ TEX_TILE_SIZE,
tc->format,
(float *) tile->data.color);
}
/**
* Cache tile size (width and height). This needs to be a power of two.
*/
-#define TILE_SIZE_LOG2 6
-#define TILE_SIZE (1 << TILE_SIZE_LOG2)
+#define TEX_TILE_SIZE_LOG2 6
+#define TEX_TILE_SIZE (1 << TEX_TILE_SIZE_LOG2)
-#define TEX_ADDR_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1 - TILE_SIZE_LOG2)
+#define TEX_ADDR_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1 - TEX_TILE_SIZE_LOG2)
#define TEX_Z_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1)
/**
{
union tex_tile_address addr;
union {
- float color[TILE_SIZE][TILE_SIZE][4];
- unsigned int colorui[TILE_SIZE][TILE_SIZE][4];
- int colori[TILE_SIZE][TILE_SIZE][4];
+ float color[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
+ unsigned int colorui[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
+ int colori[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
} data;
};
extern const struct softpipe_tex_cached_tile *
sp_find_cached_tile_tex(struct softpipe_tex_tile_cache *tc,
- union tex_tile_address addr );
+ union tex_tile_address addr );
static INLINE union tex_tile_address
tex_tile_address( unsigned x,
union tex_tile_address addr;
addr.value = 0;
- addr.bits.x = x / TILE_SIZE;
- addr.bits.y = y / TILE_SIZE;
+ addr.bits.x = x / TEX_TILE_SIZE;
+ addr.bits.y = y / TEX_TILE_SIZE;
addr.bits.z = z;
addr.bits.face = face;
addr.bits.level = level;
*/
static INLINE const struct softpipe_tex_cached_tile *
sp_get_cached_tile_tex(struct softpipe_tex_tile_cache *tc,
- union tex_tile_address addr )
+ union tex_tile_address addr )
{
if (tc->last_tile->addr.value == addr.value)
return tc->last_tile;