More formatting

diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index a95d81bfd7262fed0e03f5935321b3fe39905d17..e9b2ccded72cdc956bc70242cd9af43000718179 100644 (file)
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -1,19 +1,19 @@
 /*
- *     yosys -- Yosys Open SYnthesis Suite
+ *  yosys -- Yosys Open SYnthesis Suite
  *
- *     Copyright (C) 2012      Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
  *
- *     Permission to use, copy, modify, and/or distribute this software for any
- *     purpose with or without fee is hereby granted, provided that the above
- *     copyright notice and this permission notice appear in all copies.
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
  *
- *     THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *     WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *     MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *     ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *     WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *     ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
  */
 
@@ -31,47 +31,41 @@ struct SynthGowinPass : public ScriptPass
 
        void help() YS_OVERRIDE
        {
-               //       |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-    log("\n");
-    log("    synth_gowin [options]\n");
-    log("\n");
-    log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n");
-    log("\n");
-    log("    -top <module>\n");
-    log("        use the specified module as top module (default='top')\n");
-    log("\n");
-    log("    -vout <file>\n");
-    log("        write the design to the specified Verilog netlist file. writing of an\n");
-    log("        output file is omitted if this parameter is not specified.\n");
-    log("\n");
-    log("    -run <from_label>:<to_label>\n");
-    log("        only run the commands between the labels (see below). an empty\n");
-    log("        from label is synonymous to 'begin', and empty to label is\n");
-    log("        synonymous to the end of the command list.\n");
-    log("\n");
-    log("    -nodffe\n");
-    log("        do not use flipflops with CE in output netlist\n");
-    log("\n");
-    log("    -nobram\n");
-    log("        do not use BRAM cells in output netlist\n");
-    log("\n");
-    log("    -nodram\n");
-    log("        do not use distributed RAM cells in output netlist\n");
-    log("\n");
-    log("    -noflatten\n");
-    log("        do not flatten design before synthesis\n");
-    log("\n");
-    log("    -retime\n");
-    log("        run 'abc' with -dff option\n");
-    log("\n");
-    log("    -nowidelut\n");
-    log("        do not use muxes to implement LUTs larger than LUT4s\n");
-    log("\n");
-    log("    -abc9\n");
-    log("        use new ABC9 flow (EXPERIMENTAL)\n");
-    log("\n");
-    log("\n");
-    log("The following commands are executed by this synthesis command:\n");
+               //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+               log("\n");
+               log("    synth_gowin [options]\n");
+               log("\n");
+               log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n");
+               log("\n");
+               log("    -top <module>\n");
+               log("        use the specified module as top module (default='top')\n");
+               log("\n");
+               log("    -vout <file>\n");
+               log("        write the design to the specified Verilog netlist file. writing of an\n");
+               log("        output file is omitted if this parameter is not specified.\n");
+               log("\n");
+               log("    -run <from_label>:<to_label>\n");
+               log("        only run the commands between the labels (see below). an empty\n");
+               log("        from label is synonymous to 'begin', and empty to label is\n");
+               log("        synonymous to the end of the command list.\n");
+               log("\n");
+               log("    -nodffe\n");
+               log("        do not use flipflops with CE in output netlist\n");
+               log("\n");
+               log("    -nobram\n");
+               log("        do not use BRAM cells in output netlist\n");
+               log("\n");
+               log("    -nodram\n");
+               log("        do not use distributed RAM cells in output netlist\n");
+               log("\n");
+               log("    -noflatten\n");
+               log("        do not flatten design before synthesis\n");
+               log("\n");
+               log("    -retime\n");
+               log("        run 'abc' with -dff option\n");
+               log("\n");
+               log("\n");
+               log("The following commands are executed by this synthesis command:\n");
                help_script();
                log("\n");
        }
@@ -180,7 +174,7 @@ struct SynthGowinPass : public ScriptPass
                        run("synth -run coarse");
                }
                
-               if (!nobram && check_label("bram", "(skip if -nobram)"))
+                if (!nobram && check_label("bram", "(skip if -nobram)"))
                {
                        run("memory_bram -rules +/gowin/bram.txt");
                        run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v");
@@ -237,7 +231,7 @@ struct SynthGowinPass : public ScriptPass
                        run("setundef -undriven -params -zero");
                        run("hilomap -singleton -hicell VCC V -locell GND G");
                        run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)");
-                       run("dffinit -ff DFF Q INIT");
+                       run("dffinit  -ff DFF Q INIT");
                        run("clean");
 
                }