{ CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
};
-/* Operand references. */
-
-#define INPUT CGEN_OPERAND_INSTANCE_INPUT
-#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
-#define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
-
-static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
- { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
- { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
- { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
- { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_addn_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_addni_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_addn2_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
- { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
- { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
- { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_and_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_andm_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
- { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_andh_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
- { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_andb_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
- { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_bandl_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
- { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
- { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_btstl_ops[] = {
- { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
- { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_mul_ops[] = {
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
- { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
- { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_mulu_ops[] = {
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { INPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
- { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
- { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
- { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_mulh_ops[] = {
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
- { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_div0s_ops[] = {
- { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
- { INPUT, "d0bit", & HW_ENT (HW_H_D0BIT), CGEN_MODE_BI, 0, 0, 0 },
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "d0bit", & HW_ENT (HW_H_D0BIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_div0u_ops[] = {
- { OUTPUT, "d0bit", & HW_ENT (HW_H_D0BIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_div1_ops[] = {
- { INPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
- { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
- { INPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
- { INPUT, "d0bit", & HW_ENT (HW_H_D0BIT), CGEN_MODE_BI, 0, 0, 0 },
- { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
- { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_div2_ops[] = {
- { INPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
- { INPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, COND_REF },
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, COND_REF },
- { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_div3_ops[] = {
- { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, COND_REF },
- { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_div4s_ops[] = {
- { INPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
- { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, COND_REF },
- { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_lsl_ops[] = {
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_lsli_ops[] = {
- { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
- { INPUT, "i8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I8), 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldi20_ops[] = {
- { INPUT, "i20", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I20), 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldi32_ops[] = {
- { INPUT, "i32", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I32), 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
- { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_lduh_ops[] = {
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
- { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldub_ops[] = {
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
- { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldr13_ops[] = {
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
- { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldr13uh_ops[] = {
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
- { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldr13ub_ops[] = {
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
- { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldr14_ops[] = {
- { INPUT, "disp10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP10), 0, 0 },
- { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
- { INPUT, "h_memory_add__VM_disp10_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldr14uh_ops[] = {
- { INPUT, "disp9", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP9), 0, 0 },
- { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
- { INPUT, "h_memory_add__VM_disp9_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldr14ub_ops[] = {
- { INPUT, "disp8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP8), 0, 0 },
- { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
- { INPUT, "h_memory_add__VM_disp8_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldr15_ops[] = {
- { INPUT, "udisp6", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UDISP6), 0, 0 },
- { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { INPUT, "h_memory_add__VM_udisp6_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldr15gr_ops[] = {
- { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "f_Ri", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldr15dr_ops[] = {
- { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { OUTPUT, "Rs2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS2), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldr15ps_ops[] = {
- { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
- { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_str13_ops[] = {
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
- { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_str13h_ops[] = {
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
- { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_str13b_ops[] = {
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
- { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_str14_ops[] = {
- { INPUT, "disp10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP10), 0, 0 },
- { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "h_memory_add__VM_disp10_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_str14h_ops[] = {
- { INPUT, "disp9", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP9), 0, 0 },
- { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "h_memory_add__VM_disp9_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_str14b_ops[] = {
- { INPUT, "disp8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP8), 0, 0 },
- { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "h_memory_add__VM_disp8_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_str15_ops[] = {
- { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { INPUT, "udisp6", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UDISP6), 0, 0 },
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_15_udisp6", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_str15gr_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_str15dr_ops[] = {
- { INPUT, "Rs2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS2), 0, 0 },
- { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_str15ps_ops[] = {
- { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { INPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
- { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_mov_ops[] = {
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_movdr_ops[] = {
- { INPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS1), 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_movps_ops[] = {
- { INPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_mov2dr_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS1), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_mov2ps_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_callr_ops[] = {
- { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_call_ops[] = {
- { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
- { INPUT, "label12", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL12), 0, 0 },
- { OUTPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ret_ops[] = {
- { INPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_int_ops[] = {
- { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (U8), 0, 0 },
- { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, 0 },
- { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_inte_ops[] = {
- { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, 0 },
- { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "ilm", & HW_ENT (HW_H_ILM), CGEN_MODE_UQI, 0, 0, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_reti_ops[] = {
- { INPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
- { INPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, COND_REF },
- { INPUT, "h_memory_reg__VM_h_dr_2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 3, COND_REF },
- { INPUT, "h_memory_reg__VM_h_dr_3", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
- { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, COND_REF },
- { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, COND_REF },
- { OUTPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 3, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_brad_ops[] = {
- { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_beqd_ops[] = {
- { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_bcd_ops[] = {
- { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
- { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_bnd_ops[] = {
- { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_bvd_ops[] = {
- { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
- { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_bltd_ops[] = {
- { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
- { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_bled_ops[] = {
- { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
- { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_blsd_ops[] = {
- { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
- { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_dmovr13_ops[] = {
- { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
- { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { OUTPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_dmovr13h_ops[] = {
- { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
- { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { OUTPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_dmovr13b_ops[] = {
- { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
- { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { OUTPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_dmovr13pi_ops[] = {
- { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
- { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { INPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_dmovr13pih_ops[] = {
- { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
- { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { INPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { OUTPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_dmovr13pib_ops[] = {
- { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
- { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { INPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { OUTPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_dmovr15pi_ops[] = {
- { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
- { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_dmov2r13_ops[] = {
- { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
- { INPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_dmov2r13h_ops[] = {
- { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
- { INPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_dmov2r13b_ops[] = {
- { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
- { INPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pi_ops[] = {
- { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
- { INPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pih_ops[] = {
- { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
- { INPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { OUTPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pib_ops[] = {
- { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
- { INPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { OUTPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_dmov2r15pd_ops[] = {
- { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
- { INPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldres_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_andccr_ops[] = {
- { INPUT, "ccr", & HW_ENT (HW_H_CCR), CGEN_MODE_UQI, 0, 0, 0 },
- { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U8), 0, 0 },
- { OUTPUT, "ccr", & HW_ENT (HW_H_CCR), CGEN_MODE_UQI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stilm_ops[] = {
- { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U8), 0, 0 },
- { OUTPUT, "ilm", & HW_ENT (HW_H_ILM), CGEN_MODE_UQI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_addsp_ops[] = {
- { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { INPUT, "s10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (S10), 0, 0 },
- { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_extsb_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_extub_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_UQI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_extsh_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_extuh_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_UHI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldm0_ops[] = {
- { INPUT, "reglist_low_ld", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_LOW_LD), 0, 0 },
- { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
- { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
- { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, COND_REF },
- { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
- { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, COND_REF },
- { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, COND_REF },
- { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, COND_REF },
- { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, COND_REF },
- { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, COND_REF },
- { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, COND_REF },
- { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldm1_ops[] = {
- { INPUT, "reglist_hi_ld", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_HI_LD), 0, 0 },
- { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
- { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
- { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, COND_REF },
- { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
- { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, COND_REF },
- { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, COND_REF },
- { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, COND_REF },
- { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, COND_REF },
- { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, COND_REF },
- { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stm0_ops[] = {
- { INPUT, "reglist_low_st", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_LOW_ST), 0, 0 },
- { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
- { INPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, COND_REF },
- { INPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, COND_REF },
- { INPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, COND_REF },
- { INPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, COND_REF },
- { INPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, COND_REF },
- { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, COND_REF },
- { INPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, COND_REF },
- { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, COND_REF },
- { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
- { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stm1_ops[] = {
- { INPUT, "reglist_hi_st", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_HI_ST), 0, 0 },
- { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
- { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF },
- { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, COND_REF },
- { INPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, COND_REF },
- { INPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, COND_REF },
- { INPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, COND_REF },
- { INPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, COND_REF },
- { INPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, COND_REF },
- { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
- { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_enter_ops[] = {
- { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
- { INPUT, "u10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U10), 0, 0 },
- { OUTPUT, "h_memory_tmp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
- { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_leave_ops[] = {
- { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
- { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { INPUT, "h_memory_sub__VM_reg__VM_h_gr_15_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_xchb_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
- { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
- { 0 }
-};
-
-#undef INPUT
-#undef OUTPUT
-#undef COND_REF
-
/* Instruction formats. */
#define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
FR30_INSN_ADD, "add", "add",
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_add, { 0xa600 },
- (PTR) & fmt_add_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* add $u4,$Ri */
FR30_INSN_ADDI, "addi", "add",
{ { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
& fmt_addi, { 0xa400 },
- (PTR) & fmt_addi_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* add2 $m4,$Ri */
FR30_INSN_ADD2, "add2", "add2",
{ { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
& fmt_add2, { 0xa500 },
- (PTR) & fmt_add2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* addc $Rj,$Ri */
FR30_INSN_ADDC, "addc", "addc",
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_addc, { 0xa700 },
- (PTR) & fmt_addc_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* addn $Rj,$Ri */
FR30_INSN_ADDN, "addn", "addn",
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_addn, { 0xa200 },
- (PTR) & fmt_addn_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* addn $u4,$Ri */
FR30_INSN_ADDNI, "addni", "addn",
{ { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
& fmt_addni, { 0xa000 },
- (PTR) & fmt_addni_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* addn2 $m4,$Ri */
FR30_INSN_ADDN2, "addn2", "addn2",
{ { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
& fmt_addn2, { 0xa100 },
- (PTR) & fmt_addn2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* sub $Rj,$Ri */
FR30_INSN_SUB, "sub", "sub",
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_add, { 0xac00 },
- (PTR) & fmt_add_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* subc $Rj,$Ri */
FR30_INSN_SUBC, "subc", "subc",
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_addc, { 0xad00 },
- (PTR) & fmt_addc_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* subn $Rj,$Ri */
FR30_INSN_SUBN, "subn", "subn",
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_addn, { 0xae00 },
- (PTR) & fmt_addn_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmp $Rj,$Ri */
FR30_INSN_CMP, "cmp", "cmp",
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_cmp, { 0xaa00 },
- (PTR) & fmt_cmp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmp $u4,$Ri */
FR30_INSN_CMPI, "cmpi", "cmp",
{ { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
& fmt_cmpi, { 0xa800 },
- (PTR) & fmt_cmpi_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmp2 $m4,$Ri */
FR30_INSN_CMP2, "cmp2", "cmp2",
{ { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
& fmt_cmp2, { 0xa900 },
- (PTR) & fmt_cmp2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* and $Rj,$Ri */
FR30_INSN_AND, "and", "and",
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_and, { 0x8200 },
- (PTR) & fmt_and_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* or $Rj,$Ri */
FR30_INSN_OR, "or", "or",
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_and, { 0x9200 },
- (PTR) & fmt_and_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* eor $Rj,$Ri */
FR30_INSN_EOR, "eor", "eor",
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_and, { 0x9a00 },
- (PTR) & fmt_and_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* and $Rj,@$Ri */
FR30_INSN_ANDM, "andm", "and",
{ { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
& fmt_andm, { 0x8400 },
- (PTR) & fmt_andm_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* andh $Rj,@$Ri */
FR30_INSN_ANDH, "andh", "andh",
{ { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
& fmt_andh, { 0x8500 },
- (PTR) & fmt_andh_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* andb $Rj,@$Ri */
FR30_INSN_ANDB, "andb", "andb",
{ { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
& fmt_andb, { 0x8600 },
- (PTR) & fmt_andb_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* or $Rj,@$Ri */
FR30_INSN_ORM, "orm", "or",
{ { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
& fmt_andm, { 0x9400 },
- (PTR) & fmt_andm_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* orh $Rj,@$Ri */
FR30_INSN_ORH, "orh", "orh",
{ { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
& fmt_andh, { 0x9500 },
- (PTR) & fmt_andh_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* orb $Rj,@$Ri */
FR30_INSN_ORB, "orb", "orb",
{ { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
& fmt_andb, { 0x9600 },
- (PTR) & fmt_andb_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* eor $Rj,@$Ri */
FR30_INSN_EORM, "eorm", "eor",
{ { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
& fmt_andm, { 0x9c00 },
- (PTR) & fmt_andm_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* eorh $Rj,@$Ri */
FR30_INSN_EORH, "eorh", "eorh",
{ { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
& fmt_andh, { 0x9d00 },
- (PTR) & fmt_andh_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* eorb $Rj,@$Ri */
FR30_INSN_EORB, "eorb", "eorb",
{ { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
& fmt_andb, { 0x9e00 },
- (PTR) & fmt_andb_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bandl $u4,@$Ri */
FR30_INSN_BANDL, "bandl", "bandl",
{ { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
& fmt_bandl, { 0x8000 },
- (PTR) & fmt_bandl_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* borl $u4,@$Ri */
FR30_INSN_BORL, "borl", "borl",
{ { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
& fmt_bandl, { 0x9000 },
- (PTR) & fmt_bandl_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* beorl $u4,@$Ri */
FR30_INSN_BEORL, "beorl", "beorl",
{ { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
& fmt_bandl, { 0x9800 },
- (PTR) & fmt_bandl_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bandh $u4,@$Ri */
FR30_INSN_BANDH, "bandh", "bandh",
{ { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
& fmt_bandl, { 0x8100 },
- (PTR) & fmt_bandl_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* borh $u4,@$Ri */
FR30_INSN_BORH, "borh", "borh",
{ { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
& fmt_bandl, { 0x9100 },
- (PTR) & fmt_bandl_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* beorh $u4,@$Ri */
FR30_INSN_BEORH, "beorh", "beorh",
{ { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
& fmt_bandl, { 0x9900 },
- (PTR) & fmt_bandl_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* btstl $u4,@$Ri */
FR30_INSN_BTSTL, "btstl", "btstl",
{ { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
& fmt_btstl, { 0x8800 },
- (PTR) & fmt_btstl_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* btsth $u4,@$Ri */
FR30_INSN_BTSTH, "btsth", "btsth",
{ { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
& fmt_btstl, { 0x8900 },
- (PTR) & fmt_btstl_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* mul $Rj,$Ri */
FR30_INSN_MUL, "mul", "mul",
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_mul, { 0xaf00 },
- (PTR) & fmt_mul_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* mulu $Rj,$Ri */
FR30_INSN_MULU, "mulu", "mulu",
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_mulu, { 0xab00 },
- (PTR) & fmt_mulu_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* mulh $Rj,$Ri */
FR30_INSN_MULH, "mulh", "mulh",
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_mulh, { 0xbf00 },
- (PTR) & fmt_mulh_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* muluh $Rj,$Ri */
FR30_INSN_MULUH, "muluh", "muluh",
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_mulh, { 0xbb00 },
- (PTR) & fmt_mulh_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* div0s $Ri */
FR30_INSN_DIV0S, "div0s", "div0s",
{ { MNEM, ' ', OP (RI), 0 } },
& fmt_div0s, { 0x9740 },
- (PTR) & fmt_div0s_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* div0u $Ri */
FR30_INSN_DIV0U, "div0u", "div0u",
{ { MNEM, ' ', OP (RI), 0 } },
& fmt_div0u, { 0x9750 },
- (PTR) & fmt_div0u_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* div1 $Ri */
FR30_INSN_DIV1, "div1", "div1",
{ { MNEM, ' ', OP (RI), 0 } },
& fmt_div1, { 0x9760 },
- (PTR) & fmt_div1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* div2 $Ri */
FR30_INSN_DIV2, "div2", "div2",
{ { MNEM, ' ', OP (RI), 0 } },
& fmt_div2, { 0x9770 },
- (PTR) & fmt_div2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* div3 */
FR30_INSN_DIV3, "div3", "div3",
{ { MNEM, 0 } },
& fmt_div3, { 0x9f60 },
- (PTR) & fmt_div3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* div4s */
FR30_INSN_DIV4S, "div4s", "div4s",
{ { MNEM, 0 } },
& fmt_div4s, { 0x9f70 },
- (PTR) & fmt_div4s_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lsl $Rj,$Ri */
FR30_INSN_LSL, "lsl", "lsl",
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_lsl, { 0xb600 },
- (PTR) & fmt_lsl_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lsl $u4,$Ri */
FR30_INSN_LSLI, "lsli", "lsl",
{ { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
& fmt_lsli, { 0xb400 },
- (PTR) & fmt_lsli_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lsl2 $u4,$Ri */
FR30_INSN_LSL2, "lsl2", "lsl2",
{ { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
& fmt_lsli, { 0xb500 },
- (PTR) & fmt_lsli_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lsr $Rj,$Ri */
FR30_INSN_LSR, "lsr", "lsr",
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_lsl, { 0xb200 },
- (PTR) & fmt_lsl_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lsr $u4,$Ri */
FR30_INSN_LSRI, "lsri", "lsr",
{ { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
& fmt_lsli, { 0xb000 },
- (PTR) & fmt_lsli_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lsr2 $u4,$Ri */
FR30_INSN_LSR2, "lsr2", "lsr2",
{ { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
& fmt_lsli, { 0xb100 },
- (PTR) & fmt_lsli_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* asr $Rj,$Ri */
FR30_INSN_ASR, "asr", "asr",
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_lsl, { 0xba00 },
- (PTR) & fmt_lsl_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* asr $u4,$Ri */
FR30_INSN_ASRI, "asri", "asr",
{ { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
& fmt_lsli, { 0xb800 },
- (PTR) & fmt_lsli_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* asr2 $u4,$Ri */
FR30_INSN_ASR2, "asr2", "asr2",
{ { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
& fmt_lsli, { 0xb900 },
- (PTR) & fmt_lsli_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldi:8 $i8,$Ri */
FR30_INSN_LDI8, "ldi8", "ldi:8",
{ { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
& fmt_ldi8, { 0xc000 },
- (PTR) & fmt_ldi8_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldi:20 $i20,$Ri */
FR30_INSN_LDI20, "ldi20", "ldi:20",
{ { MNEM, ' ', OP (I20), ',', OP (RI), 0 } },
& fmt_ldi20, { 0x9b00 },
- (PTR) & fmt_ldi20_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* ldi:32 $i32,$Ri */
FR30_INSN_LDI32, "ldi32", "ldi:32",
{ { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
& fmt_ldi32, { 0x9f80 },
- (PTR) & fmt_ldi32_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* ld @$Rj,$Ri */
FR30_INSN_LD, "ld", "ld",
{ { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
& fmt_ld, { 0x400 },
- (PTR) & fmt_ld_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lduh @$Rj,$Ri */
FR30_INSN_LDUH, "lduh", "lduh",
{ { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
& fmt_lduh, { 0x500 },
- (PTR) & fmt_lduh_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldub @$Rj,$Ri */
FR30_INSN_LDUB, "ldub", "ldub",
{ { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
& fmt_ldub, { 0x600 },
- (PTR) & fmt_ldub_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld @($R13,$Rj),$Ri */
FR30_INSN_LDR13, "ldr13", "ld",
{ { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
& fmt_ldr13, { 0x0 },
- (PTR) & fmt_ldr13_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lduh @($R13,$Rj),$Ri */
FR30_INSN_LDR13UH, "ldr13uh", "lduh",
{ { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
& fmt_ldr13uh, { 0x100 },
- (PTR) & fmt_ldr13uh_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldub @($R13,$Rj),$Ri */
FR30_INSN_LDR13UB, "ldr13ub", "ldub",
{ { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
& fmt_ldr13ub, { 0x200 },
- (PTR) & fmt_ldr13ub_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld @($R14,$disp10),$Ri */
FR30_INSN_LDR14, "ldr14", "ld",
{ { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } },
& fmt_ldr14, { 0x2000 },
- (PTR) & fmt_ldr14_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lduh @($R14,$disp9),$Ri */
FR30_INSN_LDR14UH, "ldr14uh", "lduh",
{ { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } },
& fmt_ldr14uh, { 0x4000 },
- (PTR) & fmt_ldr14uh_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldub @($R14,$disp8),$Ri */
FR30_INSN_LDR14UB, "ldr14ub", "ldub",
{ { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } },
& fmt_ldr14ub, { 0x6000 },
- (PTR) & fmt_ldr14ub_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld @($R15,$udisp6),$Ri */
FR30_INSN_LDR15, "ldr15", "ld",
{ { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } },
& fmt_ldr15, { 0x300 },
- (PTR) & fmt_ldr15_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld @$R15+,$Ri */
FR30_INSN_LDR15GR, "ldr15gr", "ld",
{ { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } },
& fmt_ldr15gr, { 0x700 },
- (PTR) & fmt_ldr15gr_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld @$R15+,$Rs2 */
FR30_INSN_LDR15DR, "ldr15dr", "ld",
{ { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } },
& fmt_ldr15dr, { 0x780 },
- (PTR) & fmt_ldr15dr_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld @$R15+,$ps */
FR30_INSN_LDR15PS, "ldr15ps", "ld",
{ { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } },
& fmt_ldr15ps, { 0x790 },
- (PTR) & fmt_ldr15ps_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* st $Ri,@$Rj */
FR30_INSN_ST, "st", "st",
{ { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
& fmt_st, { 0x1400 },
- (PTR) & fmt_st_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* sth $Ri,@$Rj */
FR30_INSN_STH, "sth", "sth",
{ { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
& fmt_sth, { 0x1500 },
- (PTR) & fmt_sth_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stb $Ri,@$Rj */
FR30_INSN_STB, "stb", "stb",
{ { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
& fmt_stb, { 0x1600 },
- (PTR) & fmt_stb_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $Ri,@($R13,$Rj) */
FR30_INSN_STR13, "str13", "st",
{ { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
& fmt_str13, { 0x1000 },
- (PTR) & fmt_str13_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* sth $Ri,@($R13,$Rj) */
FR30_INSN_STR13H, "str13h", "sth",
{ { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
& fmt_str13h, { 0x1100 },
- (PTR) & fmt_str13h_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stb $Ri,@($R13,$Rj) */
FR30_INSN_STR13B, "str13b", "stb",
{ { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
& fmt_str13b, { 0x1200 },
- (PTR) & fmt_str13b_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $Ri,@($R14,$disp10) */
FR30_INSN_STR14, "str14", "st",
{ { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
& fmt_str14, { 0x3000 },
- (PTR) & fmt_str14_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* sth $Ri,@($R14,$disp9) */
FR30_INSN_STR14H, "str14h", "sth",
{ { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
& fmt_str14h, { 0x5000 },
- (PTR) & fmt_str14h_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stb $Ri,@($R14,$disp8) */
FR30_INSN_STR14B, "str14b", "stb",
{ { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
& fmt_str14b, { 0x7000 },
- (PTR) & fmt_str14b_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $Ri,@($R15,$udisp6) */
FR30_INSN_STR15, "str15", "st",
{ { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } },
& fmt_str15, { 0x1300 },
- (PTR) & fmt_str15_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $Ri,@-$R15 */
FR30_INSN_STR15GR, "str15gr", "st",
{ { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } },
& fmt_str15gr, { 0x1700 },
- (PTR) & fmt_str15gr_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $Rs2,@-$R15 */
FR30_INSN_STR15DR, "str15dr", "st",
{ { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } },
& fmt_str15dr, { 0x1780 },
- (PTR) & fmt_str15dr_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $ps,@-$R15 */
FR30_INSN_STR15PS, "str15ps", "st",
{ { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } },
& fmt_str15ps, { 0x1790 },
- (PTR) & fmt_str15ps_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* mov $Rj,$Ri */
FR30_INSN_MOV, "mov", "mov",
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_mov, { 0x8b00 },
- (PTR) & fmt_mov_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* mov $Rs1,$Ri */
FR30_INSN_MOVDR, "movdr", "mov",
{ { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
& fmt_movdr, { 0xb700 },
- (PTR) & fmt_movdr_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* mov $ps,$Ri */
FR30_INSN_MOVPS, "movps", "mov",
{ { MNEM, ' ', OP (PS), ',', OP (RI), 0 } },
& fmt_movps, { 0x1710 },
- (PTR) & fmt_movps_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* mov $Ri,$Rs1 */
FR30_INSN_MOV2DR, "mov2dr", "mov",
{ { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
& fmt_mov2dr, { 0xb300 },
- (PTR) & fmt_mov2dr_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* mov $Ri,$ps */
FR30_INSN_MOV2PS, "mov2ps", "mov",
{ { MNEM, ' ', OP (RI), ',', OP (PS), 0 } },
& fmt_mov2ps, { 0x710 },
- (PTR) & fmt_mov2ps_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* jmp @$Ri */
FR30_INSN_JMP, "jmp", "jmp",
{ { MNEM, ' ', '@', OP (RI), 0 } },
& fmt_jmp, { 0x9700 },
- (PTR) & fmt_jmp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* jmp:d @$Ri */
FR30_INSN_JMPD, "jmpd", "jmp:d",
{ { MNEM, ' ', '@', OP (RI), 0 } },
& fmt_jmp, { 0x9f00 },
- (PTR) & fmt_jmp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* call @$Ri */
FR30_INSN_CALLR, "callr", "call",
{ { MNEM, ' ', '@', OP (RI), 0 } },
& fmt_callr, { 0x9710 },
- (PTR) & fmt_callr_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* call:d @$Ri */
FR30_INSN_CALLRD, "callrd", "call:d",
{ { MNEM, ' ', '@', OP (RI), 0 } },
& fmt_callr, { 0x9f10 },
- (PTR) & fmt_callr_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* call $label12 */
FR30_INSN_CALL, "call", "call",
{ { MNEM, ' ', OP (LABEL12), 0 } },
& fmt_call, { 0xd000 },
- (PTR) & fmt_call_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* call:d $label12 */
FR30_INSN_CALLD, "calld", "call:d",
{ { MNEM, ' ', OP (LABEL12), 0 } },
& fmt_call, { 0xd800 },
- (PTR) & fmt_call_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* ret */
FR30_INSN_RET, "ret", "ret",
{ { MNEM, 0 } },
& fmt_ret, { 0x9720 },
- (PTR) & fmt_ret_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* ret:d */
FR30_INSN_RET_D, "ret:d", "ret:d",
{ { MNEM, 0 } },
& fmt_ret, { 0x9f20 },
- (PTR) & fmt_ret_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* int $u8 */
FR30_INSN_INT, "int", "int",
{ { MNEM, ' ', OP (U8), 0 } },
& fmt_int, { 0x1f00 },
- (PTR) & fmt_int_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* inte */
FR30_INSN_INTE, "inte", "inte",
{ { MNEM, 0 } },
& fmt_inte, { 0x9f30 },
- (PTR) & fmt_inte_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* reti */
FR30_INSN_RETI, "reti", "reti",
{ { MNEM, 0 } },
& fmt_reti, { 0x9730 },
- (PTR) & fmt_reti_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bra:d $label9 */
FR30_INSN_BRAD, "brad", "bra:d",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_brad, { 0xf000 },
- (PTR) & fmt_brad_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bra $label9 */
FR30_INSN_BRA, "bra", "bra",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_brad, { 0xe000 },
- (PTR) & fmt_brad_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* bno:d $label9 */
FR30_INSN_BNOD, "bnod", "bno:d",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_brad, { 0xf100 },
- (PTR) & fmt_brad_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bno $label9 */
FR30_INSN_BNO, "bno", "bno",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_brad, { 0xe100 },
- (PTR) & fmt_brad_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* beq:d $label9 */
FR30_INSN_BEQD, "beqd", "beq:d",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_beqd, { 0xf200 },
- (PTR) & fmt_beqd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* beq $label9 */
FR30_INSN_BEQ, "beq", "beq",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_beqd, { 0xe200 },
- (PTR) & fmt_beqd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bne:d $label9 */
FR30_INSN_BNED, "bned", "bne:d",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_beqd, { 0xf300 },
- (PTR) & fmt_beqd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bne $label9 */
FR30_INSN_BNE, "bne", "bne",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_beqd, { 0xe300 },
- (PTR) & fmt_beqd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bc:d $label9 */
FR30_INSN_BCD, "bcd", "bc:d",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bcd, { 0xf400 },
- (PTR) & fmt_bcd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bc $label9 */
FR30_INSN_BC, "bc", "bc",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bcd, { 0xe400 },
- (PTR) & fmt_bcd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bnc:d $label9 */
FR30_INSN_BNCD, "bncd", "bnc:d",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bcd, { 0xf500 },
- (PTR) & fmt_bcd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bnc $label9 */
FR30_INSN_BNC, "bnc", "bnc",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bcd, { 0xe500 },
- (PTR) & fmt_bcd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bn:d $label9 */
FR30_INSN_BND, "bnd", "bn:d",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bnd, { 0xf600 },
- (PTR) & fmt_bnd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bn $label9 */
FR30_INSN_BN, "bn", "bn",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bnd, { 0xe600 },
- (PTR) & fmt_bnd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bp:d $label9 */
FR30_INSN_BPD, "bpd", "bp:d",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bnd, { 0xf700 },
- (PTR) & fmt_bnd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bp $label9 */
FR30_INSN_BP, "bp", "bp",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bnd, { 0xe700 },
- (PTR) & fmt_bnd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bv:d $label9 */
FR30_INSN_BVD, "bvd", "bv:d",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bvd, { 0xf800 },
- (PTR) & fmt_bvd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bv $label9 */
FR30_INSN_BV, "bv", "bv",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bvd, { 0xe800 },
- (PTR) & fmt_bvd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bnv:d $label9 */
FR30_INSN_BNVD, "bnvd", "bnv:d",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bvd, { 0xf900 },
- (PTR) & fmt_bvd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bnv $label9 */
FR30_INSN_BNV, "bnv", "bnv",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bvd, { 0xe900 },
- (PTR) & fmt_bvd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* blt:d $label9 */
FR30_INSN_BLTD, "bltd", "blt:d",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bltd, { 0xfa00 },
- (PTR) & fmt_bltd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* blt $label9 */
FR30_INSN_BLT, "blt", "blt",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bltd, { 0xea00 },
- (PTR) & fmt_bltd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bge:d $label9 */
FR30_INSN_BGED, "bged", "bge:d",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bltd, { 0xfb00 },
- (PTR) & fmt_bltd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bge $label9 */
FR30_INSN_BGE, "bge", "bge",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bltd, { 0xeb00 },
- (PTR) & fmt_bltd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* ble:d $label9 */
FR30_INSN_BLED, "bled", "ble:d",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bled, { 0xfc00 },
- (PTR) & fmt_bled_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* ble $label9 */
FR30_INSN_BLE, "ble", "ble",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bled, { 0xec00 },
- (PTR) & fmt_bled_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bgt:d $label9 */
FR30_INSN_BGTD, "bgtd", "bgt:d",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bled, { 0xfd00 },
- (PTR) & fmt_bled_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bgt $label9 */
FR30_INSN_BGT, "bgt", "bgt",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bled, { 0xed00 },
- (PTR) & fmt_bled_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bls:d $label9 */
FR30_INSN_BLSD, "blsd", "bls:d",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_blsd, { 0xfe00 },
- (PTR) & fmt_blsd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bls $label9 */
FR30_INSN_BLS, "bls", "bls",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_blsd, { 0xee00 },
- (PTR) & fmt_blsd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bhi:d $label9 */
FR30_INSN_BHID, "bhid", "bhi:d",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_blsd, { 0xff00 },
- (PTR) & fmt_blsd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bhi $label9 */
FR30_INSN_BHI, "bhi", "bhi",
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_blsd, { 0xef00 },
- (PTR) & fmt_blsd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* dmov $R13,@$dir10 */
FR30_INSN_DMOVR13, "dmovr13", "dmov",
{ { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
& fmt_dmovr13, { 0x1800 },
- (PTR) & fmt_dmovr13_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* dmovh $R13,@$dir9 */
FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
{ { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
& fmt_dmovr13h, { 0x1900 },
- (PTR) & fmt_dmovr13h_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* dmovb $R13,@$dir8 */
FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
{ { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
& fmt_dmovr13b, { 0x1a00 },
- (PTR) & fmt_dmovr13b_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* dmov @$R13+,@$dir10 */
FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov",
{ { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
& fmt_dmovr13pi, { 0x1c00 },
- (PTR) & fmt_dmovr13pi_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* dmovh @$R13+,@$dir9 */
FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh",
{ { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
& fmt_dmovr13pih, { 0x1d00 },
- (PTR) & fmt_dmovr13pih_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* dmovb @$R13+,@$dir8 */
FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb",
{ { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
& fmt_dmovr13pib, { 0x1e00 },
- (PTR) & fmt_dmovr13pib_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* dmov @$R15+,@$dir10 */
FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov",
{ { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
& fmt_dmovr15pi, { 0x1b00 },
- (PTR) & fmt_dmovr15pi_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* dmov @$dir10,$R13 */
FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
{ { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
& fmt_dmov2r13, { 0x800 },
- (PTR) & fmt_dmov2r13_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* dmovh @$dir9,$R13 */
FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
{ { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
& fmt_dmov2r13h, { 0x900 },
- (PTR) & fmt_dmov2r13h_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* dmovb @$dir8,$R13 */
FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
{ { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
& fmt_dmov2r13b, { 0xa00 },
- (PTR) & fmt_dmov2r13b_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* dmov @$dir10,@$R13+ */
FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov",
{ { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } },
& fmt_dmov2r13pi, { 0xc00 },
- (PTR) & fmt_dmov2r13pi_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* dmovh @$dir9,@$R13+ */
FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh",
{ { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } },
& fmt_dmov2r13pih, { 0xd00 },
- (PTR) & fmt_dmov2r13pih_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* dmovb @$dir8,@$R13+ */
FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb",
{ { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } },
& fmt_dmov2r13pib, { 0xe00 },
- (PTR) & fmt_dmov2r13pib_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* dmov @$dir10,@-$R15 */
FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
{ { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } },
& fmt_dmov2r15pd, { 0xb00 },
- (PTR) & fmt_dmov2r15pd_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* ldres @$Ri+,$u4 */
FR30_INSN_LDRES, "ldres", "ldres",
{ { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
& fmt_ldres, { 0xbc00 },
- (PTR) & fmt_ldres_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stres $u4,@$Ri+ */
FR30_INSN_STRES, "stres", "stres",
{ { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
& fmt_ldres, { 0xbd00 },
- (PTR) & fmt_ldres_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* copop $u4c,$ccc,$CRj,$CRi */
FR30_INSN_ANDCCR, "andccr", "andccr",
{ { MNEM, ' ', OP (U8), 0 } },
& fmt_andccr, { 0x8300 },
- (PTR) & fmt_andccr_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* orccr $u8 */
FR30_INSN_ORCCR, "orccr", "orccr",
{ { MNEM, ' ', OP (U8), 0 } },
& fmt_andccr, { 0x9300 },
- (PTR) & fmt_andccr_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stilm $u8 */
FR30_INSN_STILM, "stilm", "stilm",
{ { MNEM, ' ', OP (U8), 0 } },
& fmt_stilm, { 0x8700 },
- (PTR) & fmt_stilm_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* addsp $s10 */
FR30_INSN_ADDSP, "addsp", "addsp",
{ { MNEM, ' ', OP (S10), 0 } },
& fmt_addsp, { 0xa300 },
- (PTR) & fmt_addsp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* extsb $Ri */
FR30_INSN_EXTSB, "extsb", "extsb",
{ { MNEM, ' ', OP (RI), 0 } },
& fmt_extsb, { 0x9780 },
- (PTR) & fmt_extsb_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* extub $Ri */
FR30_INSN_EXTUB, "extub", "extub",
{ { MNEM, ' ', OP (RI), 0 } },
& fmt_extub, { 0x9790 },
- (PTR) & fmt_extub_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* extsh $Ri */
FR30_INSN_EXTSH, "extsh", "extsh",
{ { MNEM, ' ', OP (RI), 0 } },
& fmt_extsh, { 0x97a0 },
- (PTR) & fmt_extsh_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* extuh $Ri */
FR30_INSN_EXTUH, "extuh", "extuh",
{ { MNEM, ' ', OP (RI), 0 } },
& fmt_extuh, { 0x97b0 },
- (PTR) & fmt_extuh_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldm0 ($reglist_low_ld) */
FR30_INSN_LDM0, "ldm0", "ldm0",
{ { MNEM, ' ', '(', OP (REGLIST_LOW_LD), ')', 0 } },
& fmt_ldm0, { 0x8c00 },
- (PTR) & fmt_ldm0_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* ldm1 ($reglist_hi_ld) */
FR30_INSN_LDM1, "ldm1", "ldm1",
{ { MNEM, ' ', '(', OP (REGLIST_HI_LD), ')', 0 } },
& fmt_ldm1, { 0x8d00 },
- (PTR) & fmt_ldm1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* stm0 ($reglist_low_st) */
FR30_INSN_STM0, "stm0", "stm0",
{ { MNEM, ' ', '(', OP (REGLIST_LOW_ST), ')', 0 } },
& fmt_stm0, { 0x8e00 },
- (PTR) & fmt_stm0_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* stm1 ($reglist_hi_st) */
FR30_INSN_STM1, "stm1", "stm1",
{ { MNEM, ' ', '(', OP (REGLIST_HI_ST), ')', 0 } },
& fmt_stm1, { 0x8f00 },
- (PTR) & fmt_stm1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* enter $u10 */
FR30_INSN_ENTER, "enter", "enter",
{ { MNEM, ' ', OP (U10), 0 } },
& fmt_enter, { 0xf00 },
- (PTR) & fmt_enter_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* leave */
FR30_INSN_LEAVE, "leave", "leave",
{ { MNEM, 0 } },
& fmt_leave, { 0x9f90 },
- (PTR) & fmt_leave_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* xchb @$Rj,$Ri */
FR30_INSN_XCHB, "xchb", "xchb",
{ { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
& fmt_xchb, { 0x8a00 },
- (PTR) & fmt_xchb_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
};
{ CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
};
-/* Operand references. */
-
-#define INPUT CGEN_OPERAND_INSTANCE_INPUT
-#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
-#define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
-
-static const CGEN_OPERAND_INSTANCE fmt_mulo_ops[] = {
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_mulo1_ops[] = {
- { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_mulo2_ops[] = {
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
- { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_mulo3_ops[] = {
- { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
- { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_remo_ops[] = {
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_remo1_ops[] = {
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
- { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_remo2_ops[] = {
- { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_remo3_ops[] = {
- { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
- { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_not_ops[] = {
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_not1_ops[] = {
- { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_not2_ops[] = {
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_not3_ops[] = {
- { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_emul_ops[] = {
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_emul1_ops[] = {
- { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_emul2_ops[] = {
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
- { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_emul3_ops[] = {
- { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
- { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_movl_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "f_src1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_src1_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_movl1_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_movt_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "f_src1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_src1_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_src1_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_movt1_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_movq_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "f_src1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_src1_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_src1_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_src1_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_movq1_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_modpc_ops[] = {
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_lda_offset_ops[] = {
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_offset_ops[] = {
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_ops[] = {
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_index_ops[] = {
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_lda_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_lda_index_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_index_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ld_offset_ops[] = {
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_offset_ops[] = {
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_ops[] = {
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_index_ops[] = {
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ld_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ld_index_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_index_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldob_offset_ops[] = {
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_offset_ops[] = {
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_ops[] = {
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_index_ops[] = {
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldob_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldob_index_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_index_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldos_offset_ops[] = {
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_offset_ops[] = {
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_ops[] = {
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_index_ops[] = {
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldos_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldos_index_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_index_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldib_offset_ops[] = {
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_offset_ops[] = {
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_ops[] = {
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_index_ops[] = {
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldib_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldib_index_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_index_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldis_offset_ops[] = {
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_offset_ops[] = {
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_ops[] = {
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_index_ops[] = {
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldis_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldis_index_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_index_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldl_offset_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_offset_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_index_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldl_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldl_index_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_index_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldt_offset_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_offset_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_index_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldt_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldt_index_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_index_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldq_offset_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_offset_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_index_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldq_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldq_index_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_index_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_st_offset_ops[] = {
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_st_indirect_offset_ops[] = {
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_st_indirect_ops[] = {
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_st_indirect_index_ops[] = {
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_st_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_st_indirect_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_st_index_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_st_indirect_index_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stob_offset_ops[] = {
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_offset_ops[] = {
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_ops[] = {
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_index_ops[] = {
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stob_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stob_index_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_index_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stos_offset_ops[] = {
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_offset_ops[] = {
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_ops[] = {
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_index_ops[] = {
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stos_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stos_index_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_index_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stl_offset_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_offset_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_offset_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_index_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stl_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stl_index_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_index_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stt_offset_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_offset_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_offset_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_offset_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_index_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stt_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stt_index_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_index_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stq_offset_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_offset_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_offset_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_offset_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_offset_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_abase_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_index_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stq_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stq_index_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_index_disp_ops[] = {
- { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_cmpobe_reg_ops[] = {
- { INPUT, "br_src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC1), 0, 0 },
- { INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC2), 0, 0 },
- { INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_cmpobe_lit_ops[] = {
- { INPUT, "br_lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (BR_LIT1), 0, 0 },
- { INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC2), 0, 0 },
- { INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_cmpobl_reg_ops[] = {
- { INPUT, "br_src1", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (BR_SRC1), 0, 0 },
- { INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (BR_SRC2), 0, 0 },
- { INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_cmpobl_lit_ops[] = {
- { INPUT, "br_lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (BR_LIT1), 0, 0 },
- { INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (BR_SRC2), 0, 0 },
- { INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_bbc_lit_ops[] = {
- { INPUT, "br_lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (BR_LIT1), 0, 0 },
- { INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC2), 0, 0 },
- { INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
- { OUTPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_cmpi1_ops[] = {
- { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (LIT1), 0, 0 },
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
- { OUTPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_cmpi2_ops[] = {
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
- { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (LIT2), 0, 0 },
- { OUTPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_cmpi3_ops[] = {
- { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (LIT1), 0, 0 },
- { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (LIT2), 0, 0 },
- { OUTPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_testno_reg_ops[] = {
- { INPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "br_src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC1), 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_bno_ops[] = {
- { INPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "ctrl_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (CTRL_DISP), 0, COND_REF },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_b_ops[] = {
- { INPUT, "ctrl_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (CTRL_DISP), 0, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_offset_ops[] = {
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_ops[] = {
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_index_ops[] = {
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
- { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_bx_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_disp_ops[] = {
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_callx_disp_ops[] = {
- { INPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
- { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
- { INPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
- { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
- { INPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
- { INPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
- { INPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
- { INPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
- { INPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
- { INPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
- { INPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
- { INPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
- { INPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
- { INPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
- { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
- { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
- { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
- { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
- { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
- { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
- { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
- { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
- { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
- { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
- { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
- { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
- { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
- { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
- { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
- { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { OUTPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_callx_indirect_ops[] = {
- { INPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
- { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
- { INPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
- { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
- { INPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
- { INPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
- { INPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
- { INPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
- { INPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
- { INPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
- { INPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
- { INPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
- { INPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
- { INPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
- { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
- { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
- { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
- { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
- { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
- { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
- { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
- { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
- { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
- { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
- { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
- { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
- { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
- { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
- { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { OUTPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_callx_indirect_offset_ops[] = {
- { INPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
- { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
- { INPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
- { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
- { INPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
- { INPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
- { INPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
- { INPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
- { INPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
- { INPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
- { INPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
- { INPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
- { INPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
- { INPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
- { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
- { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
- { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
- { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
- { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
- { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
- { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
- { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
- { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
- { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
- { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
- { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
- { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
- { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
- { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
- { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
- { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { OUTPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_ret_ops[] = {
- { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
- { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
- { OUTPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
- { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
- { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
- { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
- { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
- { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
- { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
- { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
- { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
- { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
- { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
- { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
- { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
- { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
- { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
- { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_calls_ops[] = {
- { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_fmark_ops[] = {
- { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
- { 0 }
-};
-
-#undef INPUT
-#undef OUTPUT
-#undef COND_REF
-
/* Instruction formats. */
#define F(f) & i960_cgen_ifld_table[CONCAT2 (I960_,f)]
I960_INSN_MULO, "mulo", "mulo",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo, { 0x70000080 },
- (PTR) & fmt_mulo_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* mulo $lit1, $src2, $dst */
I960_INSN_MULO1, "mulo1", "mulo",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo1, { 0x70000880 },
- (PTR) & fmt_mulo1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* mulo $src1, $lit2, $dst */
I960_INSN_MULO2, "mulo2", "mulo",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo2, { 0x70001080 },
- (PTR) & fmt_mulo2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* mulo $lit1, $lit2, $dst */
I960_INSN_MULO3, "mulo3", "mulo",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo3, { 0x70001880 },
- (PTR) & fmt_mulo3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* remo $src1, $src2, $dst */
I960_INSN_REMO, "remo", "remo",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x70000400 },
- (PTR) & fmt_remo_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* remo $lit1, $src2, $dst */
I960_INSN_REMO1, "remo1", "remo",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x70000c00 },
- (PTR) & fmt_remo1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* remo $src1, $lit2, $dst */
I960_INSN_REMO2, "remo2", "remo",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x70001400 },
- (PTR) & fmt_remo2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* remo $lit1, $lit2, $dst */
I960_INSN_REMO3, "remo3", "remo",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x70001c00 },
- (PTR) & fmt_remo3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* divo $src1, $src2, $dst */
I960_INSN_DIVO, "divo", "divo",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x70000580 },
- (PTR) & fmt_remo_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* divo $lit1, $src2, $dst */
I960_INSN_DIVO1, "divo1", "divo",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x70000d80 },
- (PTR) & fmt_remo1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* divo $src1, $lit2, $dst */
I960_INSN_DIVO2, "divo2", "divo",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x70001580 },
- (PTR) & fmt_remo2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* divo $lit1, $lit2, $dst */
I960_INSN_DIVO3, "divo3", "divo",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x70001d80 },
- (PTR) & fmt_remo3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* remi $src1, $src2, $dst */
I960_INSN_REMI, "remi", "remi",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x74000400 },
- (PTR) & fmt_remo_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* remi $lit1, $src2, $dst */
I960_INSN_REMI1, "remi1", "remi",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x74000c00 },
- (PTR) & fmt_remo1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* remi $src1, $lit2, $dst */
I960_INSN_REMI2, "remi2", "remi",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x74001400 },
- (PTR) & fmt_remo2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* remi $lit1, $lit2, $dst */
I960_INSN_REMI3, "remi3", "remi",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x74001c00 },
- (PTR) & fmt_remo3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* divi $src1, $src2, $dst */
I960_INSN_DIVI, "divi", "divi",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x74000580 },
- (PTR) & fmt_remo_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* divi $lit1, $src2, $dst */
I960_INSN_DIVI1, "divi1", "divi",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x74000d80 },
- (PTR) & fmt_remo1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* divi $src1, $lit2, $dst */
I960_INSN_DIVI2, "divi2", "divi",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x74001580 },
- (PTR) & fmt_remo2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* divi $lit1, $lit2, $dst */
I960_INSN_DIVI3, "divi3", "divi",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x74001d80 },
- (PTR) & fmt_remo3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* addo $src1, $src2, $dst */
I960_INSN_ADDO, "addo", "addo",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo, { 0x59000000 },
- (PTR) & fmt_mulo_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* addo $lit1, $src2, $dst */
I960_INSN_ADDO1, "addo1", "addo",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo1, { 0x59000800 },
- (PTR) & fmt_mulo1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* addo $src1, $lit2, $dst */
I960_INSN_ADDO2, "addo2", "addo",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo2, { 0x59001000 },
- (PTR) & fmt_mulo2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* addo $lit1, $lit2, $dst */
I960_INSN_ADDO3, "addo3", "addo",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo3, { 0x59001800 },
- (PTR) & fmt_mulo3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* subo $src1, $src2, $dst */
I960_INSN_SUBO, "subo", "subo",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x59000100 },
- (PTR) & fmt_remo_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* subo $lit1, $src2, $dst */
I960_INSN_SUBO1, "subo1", "subo",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x59000900 },
- (PTR) & fmt_remo1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* subo $src1, $lit2, $dst */
I960_INSN_SUBO2, "subo2", "subo",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x59001100 },
- (PTR) & fmt_remo2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* subo $lit1, $lit2, $dst */
I960_INSN_SUBO3, "subo3", "subo",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x59001900 },
- (PTR) & fmt_remo3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* notbit $src1, $src2, $dst */
I960_INSN_NOTBIT, "notbit", "notbit",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo, { 0x58000000 },
- (PTR) & fmt_mulo_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* notbit $lit1, $src2, $dst */
I960_INSN_NOTBIT1, "notbit1", "notbit",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo1, { 0x58000800 },
- (PTR) & fmt_mulo1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* notbit $src1, $lit2, $dst */
I960_INSN_NOTBIT2, "notbit2", "notbit",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo2, { 0x58001000 },
- (PTR) & fmt_mulo2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* notbit $lit1, $lit2, $dst */
I960_INSN_NOTBIT3, "notbit3", "notbit",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo3, { 0x58001800 },
- (PTR) & fmt_mulo3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* and $src1, $src2, $dst */
I960_INSN_AND, "and", "and",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo, { 0x58000080 },
- (PTR) & fmt_mulo_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* and $lit1, $src2, $dst */
I960_INSN_AND1, "and1", "and",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo1, { 0x58000880 },
- (PTR) & fmt_mulo1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* and $src1, $lit2, $dst */
I960_INSN_AND2, "and2", "and",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo2, { 0x58001080 },
- (PTR) & fmt_mulo2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* and $lit1, $lit2, $dst */
I960_INSN_AND3, "and3", "and",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo3, { 0x58001880 },
- (PTR) & fmt_mulo3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* andnot $src1, $src2, $dst */
I960_INSN_ANDNOT, "andnot", "andnot",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x58000100 },
- (PTR) & fmt_remo_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* andnot $lit1, $src2, $dst */
I960_INSN_ANDNOT1, "andnot1", "andnot",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x58000900 },
- (PTR) & fmt_remo1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* andnot $src1, $lit2, $dst */
I960_INSN_ANDNOT2, "andnot2", "andnot",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x58001100 },
- (PTR) & fmt_remo2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* andnot $lit1, $lit2, $dst */
I960_INSN_ANDNOT3, "andnot3", "andnot",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x58001900 },
- (PTR) & fmt_remo3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* setbit $src1, $src2, $dst */
I960_INSN_SETBIT, "setbit", "setbit",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo, { 0x58000180 },
- (PTR) & fmt_mulo_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* setbit $lit1, $src2, $dst */
I960_INSN_SETBIT1, "setbit1", "setbit",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo1, { 0x58000980 },
- (PTR) & fmt_mulo1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* setbit $src1, $lit2, $dst */
I960_INSN_SETBIT2, "setbit2", "setbit",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo2, { 0x58001180 },
- (PTR) & fmt_mulo2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* setbit $lit1, $lit2, $dst */
I960_INSN_SETBIT3, "setbit3", "setbit",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo3, { 0x58001980 },
- (PTR) & fmt_mulo3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* notand $src1, $src2, $dst */
I960_INSN_NOTAND, "notand", "notand",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x58000200 },
- (PTR) & fmt_remo_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* notand $lit1, $src2, $dst */
I960_INSN_NOTAND1, "notand1", "notand",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x58000a00 },
- (PTR) & fmt_remo1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* notand $src1, $lit2, $dst */
I960_INSN_NOTAND2, "notand2", "notand",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x58001200 },
- (PTR) & fmt_remo2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* notand $lit1, $lit2, $dst */
I960_INSN_NOTAND3, "notand3", "notand",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x58001a00 },
- (PTR) & fmt_remo3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* xor $src1, $src2, $dst */
I960_INSN_XOR, "xor", "xor",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo, { 0x58000300 },
- (PTR) & fmt_mulo_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* xor $lit1, $src2, $dst */
I960_INSN_XOR1, "xor1", "xor",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo1, { 0x58000b00 },
- (PTR) & fmt_mulo1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* xor $src1, $lit2, $dst */
I960_INSN_XOR2, "xor2", "xor",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo2, { 0x58001300 },
- (PTR) & fmt_mulo2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* xor $lit1, $lit2, $dst */
I960_INSN_XOR3, "xor3", "xor",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo3, { 0x58001b00 },
- (PTR) & fmt_mulo3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* or $src1, $src2, $dst */
I960_INSN_OR, "or", "or",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo, { 0x58000380 },
- (PTR) & fmt_mulo_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* or $lit1, $src2, $dst */
I960_INSN_OR1, "or1", "or",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo1, { 0x58000b80 },
- (PTR) & fmt_mulo1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* or $src1, $lit2, $dst */
I960_INSN_OR2, "or2", "or",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo2, { 0x58001380 },
- (PTR) & fmt_mulo2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* or $lit1, $lit2, $dst */
I960_INSN_OR3, "or3", "or",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo3, { 0x58001b80 },
- (PTR) & fmt_mulo3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* nor $src1, $src2, $dst */
I960_INSN_NOR, "nor", "nor",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x58000400 },
- (PTR) & fmt_remo_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* nor $lit1, $src2, $dst */
I960_INSN_NOR1, "nor1", "nor",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x58000c00 },
- (PTR) & fmt_remo1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* nor $src1, $lit2, $dst */
I960_INSN_NOR2, "nor2", "nor",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x58001400 },
- (PTR) & fmt_remo2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* nor $lit1, $lit2, $dst */
I960_INSN_NOR3, "nor3", "nor",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x58001c00 },
- (PTR) & fmt_remo3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* not $src1, $src2, $dst */
I960_INSN_NOT, "not", "not",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_not, { 0x58000500 },
- (PTR) & fmt_not_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* not $lit1, $src2, $dst */
I960_INSN_NOT1, "not1", "not",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_not1, { 0x58000d00 },
- (PTR) & fmt_not1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* not $src1, $lit2, $dst */
I960_INSN_NOT2, "not2", "not",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_not2, { 0x58001500 },
- (PTR) & fmt_not2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* not $lit1, $lit2, $dst */
I960_INSN_NOT3, "not3", "not",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_not3, { 0x58001d00 },
- (PTR) & fmt_not3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* clrbit $src1, $src2, $dst */
I960_INSN_CLRBIT, "clrbit", "clrbit",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo, { 0x58000600 },
- (PTR) & fmt_mulo_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* clrbit $lit1, $src2, $dst */
I960_INSN_CLRBIT1, "clrbit1", "clrbit",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo1, { 0x58000e00 },
- (PTR) & fmt_mulo1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* clrbit $src1, $lit2, $dst */
I960_INSN_CLRBIT2, "clrbit2", "clrbit",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo2, { 0x58001600 },
- (PTR) & fmt_mulo2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* clrbit $lit1, $lit2, $dst */
I960_INSN_CLRBIT3, "clrbit3", "clrbit",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo3, { 0x58001e00 },
- (PTR) & fmt_mulo3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shlo $src1, $src2, $dst */
I960_INSN_SHLO, "shlo", "shlo",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x59000600 },
- (PTR) & fmt_remo_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shlo $lit1, $src2, $dst */
I960_INSN_SHLO1, "shlo1", "shlo",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x59000e00 },
- (PTR) & fmt_remo1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shlo $src1, $lit2, $dst */
I960_INSN_SHLO2, "shlo2", "shlo",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x59001600 },
- (PTR) & fmt_remo2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shlo $lit1, $lit2, $dst */
I960_INSN_SHLO3, "shlo3", "shlo",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x59001e00 },
- (PTR) & fmt_remo3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shro $src1, $src2, $dst */
I960_INSN_SHRO, "shro", "shro",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x59000400 },
- (PTR) & fmt_remo_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shro $lit1, $src2, $dst */
I960_INSN_SHRO1, "shro1", "shro",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x59000c00 },
- (PTR) & fmt_remo1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shro $src1, $lit2, $dst */
I960_INSN_SHRO2, "shro2", "shro",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x59001400 },
- (PTR) & fmt_remo2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shro $lit1, $lit2, $dst */
I960_INSN_SHRO3, "shro3", "shro",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x59001c00 },
- (PTR) & fmt_remo3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shli $src1, $src2, $dst */
I960_INSN_SHLI, "shli", "shli",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x59000700 },
- (PTR) & fmt_remo_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shli $lit1, $src2, $dst */
I960_INSN_SHLI1, "shli1", "shli",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x59000f00 },
- (PTR) & fmt_remo1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shli $src1, $lit2, $dst */
I960_INSN_SHLI2, "shli2", "shli",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x59001700 },
- (PTR) & fmt_remo2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shli $lit1, $lit2, $dst */
I960_INSN_SHLI3, "shli3", "shli",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x59001f00 },
- (PTR) & fmt_remo3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shri $src1, $src2, $dst */
I960_INSN_SHRI, "shri", "shri",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x59000580 },
- (PTR) & fmt_remo_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shri $lit1, $src2, $dst */
I960_INSN_SHRI1, "shri1", "shri",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x59000d80 },
- (PTR) & fmt_remo1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shri $src1, $lit2, $dst */
I960_INSN_SHRI2, "shri2", "shri",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x59001580 },
- (PTR) & fmt_remo2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shri $lit1, $lit2, $dst */
I960_INSN_SHRI3, "shri3", "shri",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x59001d80 },
- (PTR) & fmt_remo3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* emul $src1, $src2, $dst */
I960_INSN_EMUL, "emul", "emul",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_emul, { 0x67000000 },
- (PTR) & fmt_emul_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* emul $lit1, $src2, $dst */
I960_INSN_EMUL1, "emul1", "emul",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_emul1, { 0x67000800 },
- (PTR) & fmt_emul1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* emul $src1, $lit2, $dst */
I960_INSN_EMUL2, "emul2", "emul",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_emul2, { 0x67001000 },
- (PTR) & fmt_emul2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* emul $lit1, $lit2, $dst */
I960_INSN_EMUL3, "emul3", "emul",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_emul3, { 0x67001800 },
- (PTR) & fmt_emul3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* mov $src1, $dst */
I960_INSN_MOV, "mov", "mov",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
& fmt_not2, { 0x5c001600 },
- (PTR) & fmt_not2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* mov $lit1, $dst */
I960_INSN_MOV1, "mov1", "mov",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
& fmt_not3, { 0x5c001e00 },
- (PTR) & fmt_not3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* movl $src1, $dst */
I960_INSN_MOVL, "movl", "movl",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
& fmt_movl, { 0x5d001600 },
- (PTR) & fmt_movl_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* movl $lit1, $dst */
I960_INSN_MOVL1, "movl1", "movl",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
& fmt_movl1, { 0x5d001e00 },
- (PTR) & fmt_movl1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* movt $src1, $dst */
I960_INSN_MOVT, "movt", "movt",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
& fmt_movt, { 0x5e001600 },
- (PTR) & fmt_movt_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* movt $lit1, $dst */
I960_INSN_MOVT1, "movt1", "movt",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
& fmt_movt1, { 0x5e001e00 },
- (PTR) & fmt_movt1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* movq $src1, $dst */
I960_INSN_MOVQ, "movq", "movq",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
& fmt_movq, { 0x5f001600 },
- (PTR) & fmt_movq_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* movq $lit1, $dst */
I960_INSN_MOVQ1, "movq1", "movq",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
& fmt_movq1, { 0x5f001e00 },
- (PTR) & fmt_movq1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* modpc $src1, $src2, $dst */
I960_INSN_MODPC, "modpc", "modpc",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_modpc, { 0x65000280 },
- (PTR) & fmt_modpc_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* modac $src1, $src2, $dst */
I960_INSN_MODAC, "modac", "modac",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_modpc, { 0x64000280 },
- (PTR) & fmt_modpc_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lda $offset, $dst */
I960_INSN_LDA_OFFSET, "lda-offset", "lda",
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
& fmt_lda_offset, { 0x8c000000 },
- (PTR) & fmt_lda_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lda $offset($abase), $dst */
I960_INSN_LDA_INDIRECT_OFFSET, "lda-indirect-offset", "lda",
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_lda_indirect_offset, { 0x8c002000 },
- (PTR) & fmt_lda_indirect_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lda ($abase), $dst */
I960_INSN_LDA_INDIRECT, "lda-indirect", "lda",
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_lda_indirect, { 0x8c001000 },
- (PTR) & fmt_lda_indirect_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lda ($abase)[$index*S$scale], $dst */
I960_INSN_LDA_INDIRECT_INDEX, "lda-indirect-index", "lda",
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_lda_indirect_index, { 0x8c001c00 },
- (PTR) & fmt_lda_indirect_index_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lda $optdisp, $dst */
I960_INSN_LDA_DISP, "lda-disp", "lda",
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
& fmt_lda_disp, { 0x8c003000 },
- (PTR) & fmt_lda_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lda $optdisp($abase), $dst */
I960_INSN_LDA_INDIRECT_DISP, "lda-indirect-disp", "lda",
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_lda_indirect_disp, { 0x8c003400 },
- (PTR) & fmt_lda_indirect_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lda $optdisp[$index*S$scale], $dst */
I960_INSN_LDA_INDEX_DISP, "lda-index-disp", "lda",
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_lda_index_disp, { 0x8c003800 },
- (PTR) & fmt_lda_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lda $optdisp($abase)[$index*S$scale], $dst */
I960_INSN_LDA_INDIRECT_INDEX_DISP, "lda-indirect-index-disp", "lda",
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_lda_indirect_index_disp, { 0x8c003c00 },
- (PTR) & fmt_lda_indirect_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld $offset, $dst */
I960_INSN_LD_OFFSET, "ld-offset", "ld",
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
& fmt_ld_offset, { 0x90000000 },
- (PTR) & fmt_ld_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld $offset($abase), $dst */
I960_INSN_LD_INDIRECT_OFFSET, "ld-indirect-offset", "ld",
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ld_indirect_offset, { 0x90002000 },
- (PTR) & fmt_ld_indirect_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld ($abase), $dst */
I960_INSN_LD_INDIRECT, "ld-indirect", "ld",
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ld_indirect, { 0x90001000 },
- (PTR) & fmt_ld_indirect_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld ($abase)[$index*S$scale], $dst */
I960_INSN_LD_INDIRECT_INDEX, "ld-indirect-index", "ld",
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ld_indirect_index, { 0x90001c00 },
- (PTR) & fmt_ld_indirect_index_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld $optdisp, $dst */
I960_INSN_LD_DISP, "ld-disp", "ld",
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
& fmt_ld_disp, { 0x90003000 },
- (PTR) & fmt_ld_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld $optdisp($abase), $dst */
I960_INSN_LD_INDIRECT_DISP, "ld-indirect-disp", "ld",
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ld_indirect_disp, { 0x90003400 },
- (PTR) & fmt_ld_indirect_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld $optdisp[$index*S$scale], $dst */
I960_INSN_LD_INDEX_DISP, "ld-index-disp", "ld",
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ld_index_disp, { 0x90003800 },
- (PTR) & fmt_ld_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld $optdisp($abase)[$index*S$scale], $dst */
I960_INSN_LD_INDIRECT_INDEX_DISP, "ld-indirect-index-disp", "ld",
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ld_indirect_index_disp, { 0x90003c00 },
- (PTR) & fmt_ld_indirect_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldob $offset, $dst */
I960_INSN_LDOB_OFFSET, "ldob-offset", "ldob",
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
& fmt_ldob_offset, { 0x80000000 },
- (PTR) & fmt_ldob_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldob $offset($abase), $dst */
I960_INSN_LDOB_INDIRECT_OFFSET, "ldob-indirect-offset", "ldob",
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldob_indirect_offset, { 0x80002000 },
- (PTR) & fmt_ldob_indirect_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldob ($abase), $dst */
I960_INSN_LDOB_INDIRECT, "ldob-indirect", "ldob",
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldob_indirect, { 0x80001000 },
- (PTR) & fmt_ldob_indirect_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldob ($abase)[$index*S$scale], $dst */
I960_INSN_LDOB_INDIRECT_INDEX, "ldob-indirect-index", "ldob",
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldob_indirect_index, { 0x80001c00 },
- (PTR) & fmt_ldob_indirect_index_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldob $optdisp, $dst */
I960_INSN_LDOB_DISP, "ldob-disp", "ldob",
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
& fmt_ldob_disp, { 0x80003000 },
- (PTR) & fmt_ldob_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldob $optdisp($abase), $dst */
I960_INSN_LDOB_INDIRECT_DISP, "ldob-indirect-disp", "ldob",
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldob_indirect_disp, { 0x80003400 },
- (PTR) & fmt_ldob_indirect_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldob $optdisp[$index*S$scale], $dst */
I960_INSN_LDOB_INDEX_DISP, "ldob-index-disp", "ldob",
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldob_index_disp, { 0x80003800 },
- (PTR) & fmt_ldob_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldob $optdisp($abase)[$index*S$scale], $dst */
I960_INSN_LDOB_INDIRECT_INDEX_DISP, "ldob-indirect-index-disp", "ldob",
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldob_indirect_index_disp, { 0x80003c00 },
- (PTR) & fmt_ldob_indirect_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldos $offset, $dst */
I960_INSN_LDOS_OFFSET, "ldos-offset", "ldos",
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
& fmt_ldos_offset, { 0x88000000 },
- (PTR) & fmt_ldos_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldos $offset($abase), $dst */
I960_INSN_LDOS_INDIRECT_OFFSET, "ldos-indirect-offset", "ldos",
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldos_indirect_offset, { 0x88002000 },
- (PTR) & fmt_ldos_indirect_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldos ($abase), $dst */
I960_INSN_LDOS_INDIRECT, "ldos-indirect", "ldos",
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldos_indirect, { 0x88001000 },
- (PTR) & fmt_ldos_indirect_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldos ($abase)[$index*S$scale], $dst */
I960_INSN_LDOS_INDIRECT_INDEX, "ldos-indirect-index", "ldos",
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldos_indirect_index, { 0x88001c00 },
- (PTR) & fmt_ldos_indirect_index_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldos $optdisp, $dst */
I960_INSN_LDOS_DISP, "ldos-disp", "ldos",
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
& fmt_ldos_disp, { 0x88003000 },
- (PTR) & fmt_ldos_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldos $optdisp($abase), $dst */
I960_INSN_LDOS_INDIRECT_DISP, "ldos-indirect-disp", "ldos",
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldos_indirect_disp, { 0x88003400 },
- (PTR) & fmt_ldos_indirect_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldos $optdisp[$index*S$scale], $dst */
I960_INSN_LDOS_INDEX_DISP, "ldos-index-disp", "ldos",
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldos_index_disp, { 0x88003800 },
- (PTR) & fmt_ldos_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldos $optdisp($abase)[$index*S$scale], $dst */
I960_INSN_LDOS_INDIRECT_INDEX_DISP, "ldos-indirect-index-disp", "ldos",
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldos_indirect_index_disp, { 0x88003c00 },
- (PTR) & fmt_ldos_indirect_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldib $offset, $dst */
I960_INSN_LDIB_OFFSET, "ldib-offset", "ldib",
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
& fmt_ldib_offset, { 0xc0000000 },
- (PTR) & fmt_ldib_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldib $offset($abase), $dst */
I960_INSN_LDIB_INDIRECT_OFFSET, "ldib-indirect-offset", "ldib",
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldib_indirect_offset, { 0xc0002000 },
- (PTR) & fmt_ldib_indirect_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldib ($abase), $dst */
I960_INSN_LDIB_INDIRECT, "ldib-indirect", "ldib",
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldib_indirect, { 0xc0001000 },
- (PTR) & fmt_ldib_indirect_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldib ($abase)[$index*S$scale], $dst */
I960_INSN_LDIB_INDIRECT_INDEX, "ldib-indirect-index", "ldib",
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldib_indirect_index, { 0xc0001c00 },
- (PTR) & fmt_ldib_indirect_index_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldib $optdisp, $dst */
I960_INSN_LDIB_DISP, "ldib-disp", "ldib",
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
& fmt_ldib_disp, { 0xc0003000 },
- (PTR) & fmt_ldib_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldib $optdisp($abase), $dst */
I960_INSN_LDIB_INDIRECT_DISP, "ldib-indirect-disp", "ldib",
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldib_indirect_disp, { 0xc0003400 },
- (PTR) & fmt_ldib_indirect_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldib $optdisp[$index*S$scale], $dst */
I960_INSN_LDIB_INDEX_DISP, "ldib-index-disp", "ldib",
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldib_index_disp, { 0xc0003800 },
- (PTR) & fmt_ldib_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldib $optdisp($abase)[$index*S$scale], $dst */
I960_INSN_LDIB_INDIRECT_INDEX_DISP, "ldib-indirect-index-disp", "ldib",
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldib_indirect_index_disp, { 0xc0003c00 },
- (PTR) & fmt_ldib_indirect_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldis $offset, $dst */
I960_INSN_LDIS_OFFSET, "ldis-offset", "ldis",
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
& fmt_ldis_offset, { 0xc8000000 },
- (PTR) & fmt_ldis_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldis $offset($abase), $dst */
I960_INSN_LDIS_INDIRECT_OFFSET, "ldis-indirect-offset", "ldis",
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldis_indirect_offset, { 0xc8002000 },
- (PTR) & fmt_ldis_indirect_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldis ($abase), $dst */
I960_INSN_LDIS_INDIRECT, "ldis-indirect", "ldis",
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldis_indirect, { 0xc8001000 },
- (PTR) & fmt_ldis_indirect_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldis ($abase)[$index*S$scale], $dst */
I960_INSN_LDIS_INDIRECT_INDEX, "ldis-indirect-index", "ldis",
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldis_indirect_index, { 0xc8001c00 },
- (PTR) & fmt_ldis_indirect_index_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldis $optdisp, $dst */
I960_INSN_LDIS_DISP, "ldis-disp", "ldis",
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
& fmt_ldis_disp, { 0xc8003000 },
- (PTR) & fmt_ldis_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldis $optdisp($abase), $dst */
I960_INSN_LDIS_INDIRECT_DISP, "ldis-indirect-disp", "ldis",
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldis_indirect_disp, { 0xc8003400 },
- (PTR) & fmt_ldis_indirect_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldis $optdisp[$index*S$scale], $dst */
I960_INSN_LDIS_INDEX_DISP, "ldis-index-disp", "ldis",
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldis_index_disp, { 0xc8003800 },
- (PTR) & fmt_ldis_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldis $optdisp($abase)[$index*S$scale], $dst */
I960_INSN_LDIS_INDIRECT_INDEX_DISP, "ldis-indirect-index-disp", "ldis",
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldis_indirect_index_disp, { 0xc8003c00 },
- (PTR) & fmt_ldis_indirect_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldl $offset, $dst */
I960_INSN_LDL_OFFSET, "ldl-offset", "ldl",
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
& fmt_ldl_offset, { 0x98000000 },
- (PTR) & fmt_ldl_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldl $offset($abase), $dst */
I960_INSN_LDL_INDIRECT_OFFSET, "ldl-indirect-offset", "ldl",
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldl_indirect_offset, { 0x98002000 },
- (PTR) & fmt_ldl_indirect_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldl ($abase), $dst */
I960_INSN_LDL_INDIRECT, "ldl-indirect", "ldl",
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldl_indirect, { 0x98001000 },
- (PTR) & fmt_ldl_indirect_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldl ($abase)[$index*S$scale], $dst */
I960_INSN_LDL_INDIRECT_INDEX, "ldl-indirect-index", "ldl",
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldl_indirect_index, { 0x98001c00 },
- (PTR) & fmt_ldl_indirect_index_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldl $optdisp, $dst */
I960_INSN_LDL_DISP, "ldl-disp", "ldl",
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
& fmt_ldl_disp, { 0x98003000 },
- (PTR) & fmt_ldl_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldl $optdisp($abase), $dst */
I960_INSN_LDL_INDIRECT_DISP, "ldl-indirect-disp", "ldl",
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldl_indirect_disp, { 0x98003400 },
- (PTR) & fmt_ldl_indirect_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldl $optdisp[$index*S$scale], $dst */
I960_INSN_LDL_INDEX_DISP, "ldl-index-disp", "ldl",
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldl_index_disp, { 0x98003800 },
- (PTR) & fmt_ldl_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldl $optdisp($abase)[$index*S$scale], $dst */
I960_INSN_LDL_INDIRECT_INDEX_DISP, "ldl-indirect-index-disp", "ldl",
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldl_indirect_index_disp, { 0x98003c00 },
- (PTR) & fmt_ldl_indirect_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldt $offset, $dst */
I960_INSN_LDT_OFFSET, "ldt-offset", "ldt",
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
& fmt_ldt_offset, { 0xa0000000 },
- (PTR) & fmt_ldt_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldt $offset($abase), $dst */
I960_INSN_LDT_INDIRECT_OFFSET, "ldt-indirect-offset", "ldt",
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldt_indirect_offset, { 0xa0002000 },
- (PTR) & fmt_ldt_indirect_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldt ($abase), $dst */
I960_INSN_LDT_INDIRECT, "ldt-indirect", "ldt",
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldt_indirect, { 0xa0001000 },
- (PTR) & fmt_ldt_indirect_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldt ($abase)[$index*S$scale], $dst */
I960_INSN_LDT_INDIRECT_INDEX, "ldt-indirect-index", "ldt",
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldt_indirect_index, { 0xa0001c00 },
- (PTR) & fmt_ldt_indirect_index_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldt $optdisp, $dst */
I960_INSN_LDT_DISP, "ldt-disp", "ldt",
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
& fmt_ldt_disp, { 0xa0003000 },
- (PTR) & fmt_ldt_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldt $optdisp($abase), $dst */
I960_INSN_LDT_INDIRECT_DISP, "ldt-indirect-disp", "ldt",
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldt_indirect_disp, { 0xa0003400 },
- (PTR) & fmt_ldt_indirect_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldt $optdisp[$index*S$scale], $dst */
I960_INSN_LDT_INDEX_DISP, "ldt-index-disp", "ldt",
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldt_index_disp, { 0xa0003800 },
- (PTR) & fmt_ldt_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldt $optdisp($abase)[$index*S$scale], $dst */
I960_INSN_LDT_INDIRECT_INDEX_DISP, "ldt-indirect-index-disp", "ldt",
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldt_indirect_index_disp, { 0xa0003c00 },
- (PTR) & fmt_ldt_indirect_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldq $offset, $dst */
I960_INSN_LDQ_OFFSET, "ldq-offset", "ldq",
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
& fmt_ldq_offset, { 0xb0000000 },
- (PTR) & fmt_ldq_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldq $offset($abase), $dst */
I960_INSN_LDQ_INDIRECT_OFFSET, "ldq-indirect-offset", "ldq",
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldq_indirect_offset, { 0xb0002000 },
- (PTR) & fmt_ldq_indirect_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldq ($abase), $dst */
I960_INSN_LDQ_INDIRECT, "ldq-indirect", "ldq",
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldq_indirect, { 0xb0001000 },
- (PTR) & fmt_ldq_indirect_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldq ($abase)[$index*S$scale], $dst */
I960_INSN_LDQ_INDIRECT_INDEX, "ldq-indirect-index", "ldq",
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldq_indirect_index, { 0xb0001c00 },
- (PTR) & fmt_ldq_indirect_index_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldq $optdisp, $dst */
I960_INSN_LDQ_DISP, "ldq-disp", "ldq",
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
& fmt_ldq_disp, { 0xb0003000 },
- (PTR) & fmt_ldq_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldq $optdisp($abase), $dst */
I960_INSN_LDQ_INDIRECT_DISP, "ldq-indirect-disp", "ldq",
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldq_indirect_disp, { 0xb0003400 },
- (PTR) & fmt_ldq_indirect_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldq $optdisp[$index*S$scale], $dst */
I960_INSN_LDQ_INDEX_DISP, "ldq-index-disp", "ldq",
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldq_index_disp, { 0xb0003800 },
- (PTR) & fmt_ldq_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldq $optdisp($abase)[$index*S$scale], $dst */
I960_INSN_LDQ_INDIRECT_INDEX_DISP, "ldq-indirect-index-disp", "ldq",
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldq_indirect_index_disp, { 0xb0003c00 },
- (PTR) & fmt_ldq_indirect_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $st_src, $offset */
I960_INSN_ST_OFFSET, "st-offset", "st",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
& fmt_st_offset, { 0x92000000 },
- (PTR) & fmt_st_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $st_src, $offset($abase) */
I960_INSN_ST_INDIRECT_OFFSET, "st-indirect-offset", "st",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
& fmt_st_indirect_offset, { 0x92002000 },
- (PTR) & fmt_st_indirect_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $st_src, ($abase) */
I960_INSN_ST_INDIRECT, "st-indirect", "st",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
& fmt_st_indirect, { 0x92001000 },
- (PTR) & fmt_st_indirect_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $st_src, ($abase)[$index*S$scale] */
I960_INSN_ST_INDIRECT_INDEX, "st-indirect-index", "st",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_st_indirect_index, { 0x92001c00 },
- (PTR) & fmt_st_indirect_index_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $st_src, $optdisp */
I960_INSN_ST_DISP, "st-disp", "st",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
& fmt_st_disp, { 0x92003000 },
- (PTR) & fmt_st_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $st_src, $optdisp($abase) */
I960_INSN_ST_INDIRECT_DISP, "st-indirect-disp", "st",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
& fmt_st_indirect_disp, { 0x92003400 },
- (PTR) & fmt_st_indirect_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $st_src, $optdisp[$index*S$scale */
I960_INSN_ST_INDEX_DISP, "st-index-disp", "st",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
& fmt_st_index_disp, { 0x92003800 },
- (PTR) & fmt_st_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $st_src, $optdisp($abase)[$index*S$scale] */
I960_INSN_ST_INDIRECT_INDEX_DISP, "st-indirect-index-disp", "st",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_st_indirect_index_disp, { 0x92003c00 },
- (PTR) & fmt_st_indirect_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, $offset */
I960_INSN_STOB_OFFSET, "stob-offset", "stob",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
& fmt_stob_offset, { 0x82000000 },
- (PTR) & fmt_stob_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, $offset($abase) */
I960_INSN_STOB_INDIRECT_OFFSET, "stob-indirect-offset", "stob",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
& fmt_stob_indirect_offset, { 0x82002000 },
- (PTR) & fmt_stob_indirect_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, ($abase) */
I960_INSN_STOB_INDIRECT, "stob-indirect", "stob",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
& fmt_stob_indirect, { 0x82001000 },
- (PTR) & fmt_stob_indirect_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, ($abase)[$index*S$scale] */
I960_INSN_STOB_INDIRECT_INDEX, "stob-indirect-index", "stob",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_stob_indirect_index, { 0x82001c00 },
- (PTR) & fmt_stob_indirect_index_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, $optdisp */
I960_INSN_STOB_DISP, "stob-disp", "stob",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
& fmt_stob_disp, { 0x82003000 },
- (PTR) & fmt_stob_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, $optdisp($abase) */
I960_INSN_STOB_INDIRECT_DISP, "stob-indirect-disp", "stob",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
& fmt_stob_indirect_disp, { 0x82003400 },
- (PTR) & fmt_stob_indirect_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, $optdisp[$index*S$scale */
I960_INSN_STOB_INDEX_DISP, "stob-index-disp", "stob",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
& fmt_stob_index_disp, { 0x82003800 },
- (PTR) & fmt_stob_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, $optdisp($abase)[$index*S$scale] */
I960_INSN_STOB_INDIRECT_INDEX_DISP, "stob-indirect-index-disp", "stob",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_stob_indirect_index_disp, { 0x82003c00 },
- (PTR) & fmt_stob_indirect_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, $offset */
I960_INSN_STOS_OFFSET, "stos-offset", "stos",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
& fmt_stos_offset, { 0x8a000000 },
- (PTR) & fmt_stos_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, $offset($abase) */
I960_INSN_STOS_INDIRECT_OFFSET, "stos-indirect-offset", "stos",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
& fmt_stos_indirect_offset, { 0x8a002000 },
- (PTR) & fmt_stos_indirect_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, ($abase) */
I960_INSN_STOS_INDIRECT, "stos-indirect", "stos",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
& fmt_stos_indirect, { 0x8a001000 },
- (PTR) & fmt_stos_indirect_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, ($abase)[$index*S$scale] */
I960_INSN_STOS_INDIRECT_INDEX, "stos-indirect-index", "stos",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_stos_indirect_index, { 0x8a001c00 },
- (PTR) & fmt_stos_indirect_index_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, $optdisp */
I960_INSN_STOS_DISP, "stos-disp", "stos",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
& fmt_stos_disp, { 0x8a003000 },
- (PTR) & fmt_stos_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, $optdisp($abase) */
I960_INSN_STOS_INDIRECT_DISP, "stos-indirect-disp", "stos",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
& fmt_stos_indirect_disp, { 0x8a003400 },
- (PTR) & fmt_stos_indirect_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, $optdisp[$index*S$scale */
I960_INSN_STOS_INDEX_DISP, "stos-index-disp", "stos",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
& fmt_stos_index_disp, { 0x8a003800 },
- (PTR) & fmt_stos_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, $optdisp($abase)[$index*S$scale] */
I960_INSN_STOS_INDIRECT_INDEX_DISP, "stos-indirect-index-disp", "stos",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_stos_indirect_index_disp, { 0x8a003c00 },
- (PTR) & fmt_stos_indirect_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, $offset */
I960_INSN_STL_OFFSET, "stl-offset", "stl",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
& fmt_stl_offset, { 0x9a000000 },
- (PTR) & fmt_stl_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, $offset($abase) */
I960_INSN_STL_INDIRECT_OFFSET, "stl-indirect-offset", "stl",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
& fmt_stl_indirect_offset, { 0x9a002000 },
- (PTR) & fmt_stl_indirect_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, ($abase) */
I960_INSN_STL_INDIRECT, "stl-indirect", "stl",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
& fmt_stl_indirect, { 0x9a001000 },
- (PTR) & fmt_stl_indirect_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, ($abase)[$index*S$scale] */
I960_INSN_STL_INDIRECT_INDEX, "stl-indirect-index", "stl",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_stl_indirect_index, { 0x9a001c00 },
- (PTR) & fmt_stl_indirect_index_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, $optdisp */
I960_INSN_STL_DISP, "stl-disp", "stl",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
& fmt_stl_disp, { 0x9a003000 },
- (PTR) & fmt_stl_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, $optdisp($abase) */
I960_INSN_STL_INDIRECT_DISP, "stl-indirect-disp", "stl",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
& fmt_stl_indirect_disp, { 0x9a003400 },
- (PTR) & fmt_stl_indirect_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, $optdisp[$index*S$scale */
I960_INSN_STL_INDEX_DISP, "stl-index-disp", "stl",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
& fmt_stl_index_disp, { 0x9a003800 },
- (PTR) & fmt_stl_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, $optdisp($abase)[$index*S$scale] */
I960_INSN_STL_INDIRECT_INDEX_DISP, "stl-indirect-index-disp", "stl",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_stl_indirect_index_disp, { 0x9a003c00 },
- (PTR) & fmt_stl_indirect_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, $offset */
I960_INSN_STT_OFFSET, "stt-offset", "stt",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
& fmt_stt_offset, { 0xa2000000 },
- (PTR) & fmt_stt_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, $offset($abase) */
I960_INSN_STT_INDIRECT_OFFSET, "stt-indirect-offset", "stt",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
& fmt_stt_indirect_offset, { 0xa2002000 },
- (PTR) & fmt_stt_indirect_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, ($abase) */
I960_INSN_STT_INDIRECT, "stt-indirect", "stt",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
& fmt_stt_indirect, { 0xa2001000 },
- (PTR) & fmt_stt_indirect_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, ($abase)[$index*S$scale] */
I960_INSN_STT_INDIRECT_INDEX, "stt-indirect-index", "stt",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_stt_indirect_index, { 0xa2001c00 },
- (PTR) & fmt_stt_indirect_index_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, $optdisp */
I960_INSN_STT_DISP, "stt-disp", "stt",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
& fmt_stt_disp, { 0xa2003000 },
- (PTR) & fmt_stt_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, $optdisp($abase) */
I960_INSN_STT_INDIRECT_DISP, "stt-indirect-disp", "stt",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
& fmt_stt_indirect_disp, { 0xa2003400 },
- (PTR) & fmt_stt_indirect_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, $optdisp[$index*S$scale */
I960_INSN_STT_INDEX_DISP, "stt-index-disp", "stt",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
& fmt_stt_index_disp, { 0xa2003800 },
- (PTR) & fmt_stt_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, $optdisp($abase)[$index*S$scale] */
I960_INSN_STT_INDIRECT_INDEX_DISP, "stt-indirect-index-disp", "stt",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_stt_indirect_index_disp, { 0xa2003c00 },
- (PTR) & fmt_stt_indirect_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, $offset */
I960_INSN_STQ_OFFSET, "stq-offset", "stq",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
& fmt_stq_offset, { 0xb2000000 },
- (PTR) & fmt_stq_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, $offset($abase) */
I960_INSN_STQ_INDIRECT_OFFSET, "stq-indirect-offset", "stq",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
& fmt_stq_indirect_offset, { 0xb2002000 },
- (PTR) & fmt_stq_indirect_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, ($abase) */
I960_INSN_STQ_INDIRECT, "stq-indirect", "stq",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
& fmt_stq_indirect, { 0xb2001000 },
- (PTR) & fmt_stq_indirect_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, ($abase)[$index*S$scale] */
I960_INSN_STQ_INDIRECT_INDEX, "stq-indirect-index", "stq",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_stq_indirect_index, { 0xb2001c00 },
- (PTR) & fmt_stq_indirect_index_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, $optdisp */
I960_INSN_STQ_DISP, "stq-disp", "stq",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
& fmt_stq_disp, { 0xb2003000 },
- (PTR) & fmt_stq_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, $optdisp($abase) */
I960_INSN_STQ_INDIRECT_DISP, "stq-indirect-disp", "stq",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
& fmt_stq_indirect_disp, { 0xb2003400 },
- (PTR) & fmt_stq_indirect_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, $optdisp[$index*S$scale */
I960_INSN_STQ_INDEX_DISP, "stq-index-disp", "stq",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
& fmt_stq_index_disp, { 0xb2003800 },
- (PTR) & fmt_stq_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, $optdisp($abase)[$index*S$scale] */
I960_INSN_STQ_INDIRECT_INDEX_DISP, "stq-indirect-index-disp", "stq",
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_stq_indirect_index_disp, { 0xb2003c00 },
- (PTR) & fmt_stq_indirect_index_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmpobe $br_src1, $br_src2, $br_disp */
I960_INSN_CMPOBE_REG, "cmpobe-reg", "cmpobe",
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_reg, { 0x32000000 },
- (PTR) & fmt_cmpobe_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobe $br_lit1, $br_src2, $br_disp */
I960_INSN_CMPOBE_LIT, "cmpobe-lit", "cmpobe",
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_lit, { 0x32002000 },
- (PTR) & fmt_cmpobe_lit_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobne $br_src1, $br_src2, $br_disp */
I960_INSN_CMPOBNE_REG, "cmpobne-reg", "cmpobne",
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_reg, { 0x35000000 },
- (PTR) & fmt_cmpobe_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobne $br_lit1, $br_src2, $br_disp */
I960_INSN_CMPOBNE_LIT, "cmpobne-lit", "cmpobne",
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_lit, { 0x35002000 },
- (PTR) & fmt_cmpobe_lit_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobl $br_src1, $br_src2, $br_disp */
I960_INSN_CMPOBL_REG, "cmpobl-reg", "cmpobl",
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobl_reg, { 0x34000000 },
- (PTR) & fmt_cmpobl_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobl $br_lit1, $br_src2, $br_disp */
I960_INSN_CMPOBL_LIT, "cmpobl-lit", "cmpobl",
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobl_lit, { 0x34002000 },
- (PTR) & fmt_cmpobl_lit_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpoble $br_src1, $br_src2, $br_disp */
I960_INSN_CMPOBLE_REG, "cmpoble-reg", "cmpoble",
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobl_reg, { 0x36000000 },
- (PTR) & fmt_cmpobl_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpoble $br_lit1, $br_src2, $br_disp */
I960_INSN_CMPOBLE_LIT, "cmpoble-lit", "cmpoble",
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobl_lit, { 0x36002000 },
- (PTR) & fmt_cmpobl_lit_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobg $br_src1, $br_src2, $br_disp */
I960_INSN_CMPOBG_REG, "cmpobg-reg", "cmpobg",
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobl_reg, { 0x31000000 },
- (PTR) & fmt_cmpobl_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobg $br_lit1, $br_src2, $br_disp */
I960_INSN_CMPOBG_LIT, "cmpobg-lit", "cmpobg",
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobl_lit, { 0x31002000 },
- (PTR) & fmt_cmpobl_lit_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobge $br_src1, $br_src2, $br_disp */
I960_INSN_CMPOBGE_REG, "cmpobge-reg", "cmpobge",
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobl_reg, { 0x33000000 },
- (PTR) & fmt_cmpobl_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobge $br_lit1, $br_src2, $br_disp */
I960_INSN_CMPOBGE_LIT, "cmpobge-lit", "cmpobge",
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobl_lit, { 0x33002000 },
- (PTR) & fmt_cmpobl_lit_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibe $br_src1, $br_src2, $br_disp */
I960_INSN_CMPIBE_REG, "cmpibe-reg", "cmpibe",
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_reg, { 0x3a000000 },
- (PTR) & fmt_cmpobe_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibe $br_lit1, $br_src2, $br_disp */
I960_INSN_CMPIBE_LIT, "cmpibe-lit", "cmpibe",
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_lit, { 0x3a002000 },
- (PTR) & fmt_cmpobe_lit_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibne $br_src1, $br_src2, $br_disp */
I960_INSN_CMPIBNE_REG, "cmpibne-reg", "cmpibne",
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_reg, { 0x3d000000 },
- (PTR) & fmt_cmpobe_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibne $br_lit1, $br_src2, $br_disp */
I960_INSN_CMPIBNE_LIT, "cmpibne-lit", "cmpibne",
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_lit, { 0x3d002000 },
- (PTR) & fmt_cmpobe_lit_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibl $br_src1, $br_src2, $br_disp */
I960_INSN_CMPIBL_REG, "cmpibl-reg", "cmpibl",
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_reg, { 0x3c000000 },
- (PTR) & fmt_cmpobe_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibl $br_lit1, $br_src2, $br_disp */
I960_INSN_CMPIBL_LIT, "cmpibl-lit", "cmpibl",
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_lit, { 0x3c002000 },
- (PTR) & fmt_cmpobe_lit_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpible $br_src1, $br_src2, $br_disp */
I960_INSN_CMPIBLE_REG, "cmpible-reg", "cmpible",
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_reg, { 0x3e000000 },
- (PTR) & fmt_cmpobe_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpible $br_lit1, $br_src2, $br_disp */
I960_INSN_CMPIBLE_LIT, "cmpible-lit", "cmpible",
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_lit, { 0x3e002000 },
- (PTR) & fmt_cmpobe_lit_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibg $br_src1, $br_src2, $br_disp */
I960_INSN_CMPIBG_REG, "cmpibg-reg", "cmpibg",
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_reg, { 0x39000000 },
- (PTR) & fmt_cmpobe_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibg $br_lit1, $br_src2, $br_disp */
I960_INSN_CMPIBG_LIT, "cmpibg-lit", "cmpibg",
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_lit, { 0x39002000 },
- (PTR) & fmt_cmpobe_lit_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibge $br_src1, $br_src2, $br_disp */
I960_INSN_CMPIBGE_REG, "cmpibge-reg", "cmpibge",
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_reg, { 0x3b000000 },
- (PTR) & fmt_cmpobe_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibge $br_lit1, $br_src2, $br_disp */
I960_INSN_CMPIBGE_LIT, "cmpibge-lit", "cmpibge",
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_lit, { 0x3b002000 },
- (PTR) & fmt_cmpobe_lit_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bbc $br_src1, $br_src2, $br_disp */
I960_INSN_BBC_REG, "bbc-reg", "bbc",
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_reg, { 0x30000000 },
- (PTR) & fmt_cmpobe_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bbc $br_lit1, $br_src2, $br_disp */
I960_INSN_BBC_LIT, "bbc-lit", "bbc",
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_bbc_lit, { 0x30002000 },
- (PTR) & fmt_bbc_lit_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bbs $br_src1, $br_src2, $br_disp */
I960_INSN_BBS_REG, "bbs-reg", "bbs",
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_reg, { 0x37000000 },
- (PTR) & fmt_cmpobe_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bbs $br_lit1, $br_src2, $br_disp */
I960_INSN_BBS_LIT, "bbs-lit", "bbs",
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_bbc_lit, { 0x37002000 },
- (PTR) & fmt_bbc_lit_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpi $src1, $src2 */
I960_INSN_CMPI, "cmpi", "cmpi",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), 0 } },
& fmt_cmpi, { 0x5a002080 },
- (PTR) & fmt_cmpi_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmpi $lit1, $src2 */
I960_INSN_CMPI1, "cmpi1", "cmpi",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), 0 } },
& fmt_cmpi1, { 0x5a002880 },
- (PTR) & fmt_cmpi1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmpi $src1, $lit2 */
I960_INSN_CMPI2, "cmpi2", "cmpi",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), 0 } },
& fmt_cmpi2, { 0x5a003080 },
- (PTR) & fmt_cmpi2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmpi $lit1, $lit2 */
I960_INSN_CMPI3, "cmpi3", "cmpi",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), 0 } },
& fmt_cmpi3, { 0x5a003880 },
- (PTR) & fmt_cmpi3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmpo $src1, $src2 */
I960_INSN_CMPO, "cmpo", "cmpo",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), 0 } },
& fmt_cmpi, { 0x5a002000 },
- (PTR) & fmt_cmpi_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmpo $lit1, $src2 */
I960_INSN_CMPO1, "cmpo1", "cmpo",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), 0 } },
& fmt_cmpi1, { 0x5a002800 },
- (PTR) & fmt_cmpi1_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmpo $src1, $lit2 */
I960_INSN_CMPO2, "cmpo2", "cmpo",
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), 0 } },
& fmt_cmpi2, { 0x5a003000 },
- (PTR) & fmt_cmpi2_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmpo $lit1, $lit2 */
I960_INSN_CMPO3, "cmpo3", "cmpo",
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), 0 } },
& fmt_cmpi3, { 0x5a003800 },
- (PTR) & fmt_cmpi3_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* testno $br_src1 */
I960_INSN_TESTNO_REG, "testno-reg", "testno",
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
& fmt_testno_reg, { 0x20000000 },
- (PTR) & fmt_testno_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* testg $br_src1 */
I960_INSN_TESTG_REG, "testg-reg", "testg",
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
& fmt_testno_reg, { 0x21000000 },
- (PTR) & fmt_testno_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* teste $br_src1 */
I960_INSN_TESTE_REG, "teste-reg", "teste",
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
& fmt_testno_reg, { 0x22000000 },
- (PTR) & fmt_testno_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* testge $br_src1 */
I960_INSN_TESTGE_REG, "testge-reg", "testge",
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
& fmt_testno_reg, { 0x23000000 },
- (PTR) & fmt_testno_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* testl $br_src1 */
I960_INSN_TESTL_REG, "testl-reg", "testl",
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
& fmt_testno_reg, { 0x24000000 },
- (PTR) & fmt_testno_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* testne $br_src1 */
I960_INSN_TESTNE_REG, "testne-reg", "testne",
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
& fmt_testno_reg, { 0x25000000 },
- (PTR) & fmt_testno_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* testle $br_src1 */
I960_INSN_TESTLE_REG, "testle-reg", "testle",
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
& fmt_testno_reg, { 0x26000000 },
- (PTR) & fmt_testno_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* testo $br_src1 */
I960_INSN_TESTO_REG, "testo-reg", "testo",
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
& fmt_testno_reg, { 0x27000000 },
- (PTR) & fmt_testno_reg_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* bno $ctrl_disp */
I960_INSN_BNO, "bno", "bno",
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
& fmt_bno, { 0x10000000 },
- (PTR) & fmt_bno_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bg $ctrl_disp */
I960_INSN_BG, "bg", "bg",
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
& fmt_bno, { 0x11000000 },
- (PTR) & fmt_bno_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* be $ctrl_disp */
I960_INSN_BE, "be", "be",
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
& fmt_bno, { 0x12000000 },
- (PTR) & fmt_bno_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bge $ctrl_disp */
I960_INSN_BGE, "bge", "bge",
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
& fmt_bno, { 0x13000000 },
- (PTR) & fmt_bno_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bl $ctrl_disp */
I960_INSN_BL, "bl", "bl",
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
& fmt_bno, { 0x14000000 },
- (PTR) & fmt_bno_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bne $ctrl_disp */
I960_INSN_BNE, "bne", "bne",
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
& fmt_bno, { 0x15000000 },
- (PTR) & fmt_bno_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* ble $ctrl_disp */
I960_INSN_BLE, "ble", "ble",
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
& fmt_bno, { 0x16000000 },
- (PTR) & fmt_bno_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bo $ctrl_disp */
I960_INSN_BO, "bo", "bo",
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
& fmt_bno, { 0x17000000 },
- (PTR) & fmt_bno_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* b $ctrl_disp */
I960_INSN_B, "b", "b",
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
& fmt_b, { 0x8000000 },
- (PTR) & fmt_b_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* bx $offset($abase) */
I960_INSN_BX_INDIRECT_OFFSET, "bx-indirect-offset", "bx",
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
& fmt_bx_indirect_offset, { 0x84002000 },
- (PTR) & fmt_bx_indirect_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* bx ($abase) */
I960_INSN_BX_INDIRECT, "bx-indirect", "bx",
{ { MNEM, ' ', '(', OP (ABASE), ')', 0 } },
& fmt_bx_indirect, { 0x84001000 },
- (PTR) & fmt_bx_indirect_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* bx ($abase)[$index*S$scale] */
I960_INSN_BX_INDIRECT_INDEX, "bx-indirect-index", "bx",
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_bx_indirect_index, { 0x84001c00 },
- (PTR) & fmt_bx_indirect_index_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* bx $optdisp */
I960_INSN_BX_DISP, "bx-disp", "bx",
{ { MNEM, ' ', OP (OPTDISP), 0 } },
& fmt_bx_disp, { 0x84003000 },
- (PTR) & fmt_bx_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* bx $optdisp($abase) */
I960_INSN_BX_INDIRECT_DISP, "bx-indirect-disp", "bx",
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
& fmt_bx_indirect_disp, { 0x84003400 },
- (PTR) & fmt_bx_indirect_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* callx $optdisp */
I960_INSN_CALLX_DISP, "callx-disp", "callx",
{ { MNEM, ' ', OP (OPTDISP), 0 } },
& fmt_callx_disp, { 0x86003000 },
- (PTR) & fmt_callx_disp_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* callx ($abase) */
I960_INSN_CALLX_INDIRECT, "callx-indirect", "callx",
{ { MNEM, ' ', '(', OP (ABASE), ')', 0 } },
& fmt_callx_indirect, { 0x86001000 },
- (PTR) & fmt_callx_indirect_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* callx $offset($abase) */
I960_INSN_CALLX_INDIRECT_OFFSET, "callx-indirect-offset", "callx",
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
& fmt_callx_indirect_offset, { 0x86002000 },
- (PTR) & fmt_callx_indirect_offset_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* ret */
I960_INSN_RET, "ret", "ret",
{ { MNEM, 0 } },
& fmt_ret, { 0xa000000 },
- (PTR) & fmt_ret_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* calls $src1 */
I960_INSN_CALLS, "calls", "calls",
{ { MNEM, ' ', OP (SRC1), 0 } },
& fmt_calls, { 0x66003000 },
- (PTR) & fmt_calls_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* fmark */
I960_INSN_FMARK, "fmark", "fmark",
{ { MNEM, 0 } },
& fmt_fmark, { 0x66003e00 },
- (PTR) & fmt_fmark_ops[0],
+ (PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* flushreg */
projects / binutils-gdb.git / commitdiff