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diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn
index 6793f9440d02e3ba7d82ad9d7f7774d7af711103..23c69a49188dad00849e8caa60325469200f3bd1 100644 (file)
--- a/openpower/sv/mv.swizzle.mdwn
+++ b/openpower/sv/mv.swizzle.mdwn
@@ -72,6 +72,10 @@ this gives a 12 bit immediate across bits 16 to 25 and 29-30.
 * 3 bits Z
 * 3 bits W
 
+| 0.2 |3.5 |6.8|9.11|
+|-----|----|---|----|
+|X    | Y  | Z | W  |
+
 the options are:
 
 * 0b000 to indicate "skip".  this is equivalent to predicate masking
@@ -82,8 +86,9 @@ the options are:
 
 Evaluating efforts to encode 12 bit swizzle into less proved unsuccessful: 7^4 comes out to 2,400 which is larger than 11 bits.
 
-Note that 7 options are needed (not 6) because the 7th option allows predicate masking to be encoded within the swizzle immediate.
-For example this allows "W..Y" to be specified, "copy W to position X,
+Note that 7 options are needed (not 6) because the 7th option allows static 
+predicate masking to be encoded within the swizzle immediate.
+For example this allows "W..Y" to specify: "copy W to position X,
 and Y to position W, leave the other two positions Y and Z unaltered"
 
 # RM Mode Concept: