gdb: Fix decoding of ARM neon memory hint insns.

gdb/ChangeLog:

2017-10-05  Jose E. Marchesi  <jose.marchesi@oracle.com>

	PR build/22188
	* arm-tdep.c (arm_decode_misc_memhint_neon): Fix decoding of CPS
	and SETEND.

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 59eb04a9d6a9d10d3e00097738b2d3beffd977bf..966472c45e7c6c6b17eb18e7c9dd3dd2f6f5c28d 100644 (file)
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,9 @@
+2017-10-05  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       PR build/22188
+       * arm-tdep.c (arm_decode_misc_memhint_neon): Fix decoding of CPS
+       and SETEND.
+
 2017-10-05  Pedro Alves  <palves@redhat.com>
 
        * linux-nat.c (linux_child_follow_fork): When following the parent

diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 27093217b8dd8572acd2cf67632433e9de8062f0..d8569e051aca6574b0d3932b2869e629b9454371 100644 (file)
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -6406,9 +6406,9 @@ arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn,
   unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7);
   unsigned int rn = bits (insn, 16, 19);
 
-  if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
+  if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0x1) == 0x0)
     return arm_copy_unmodified (gdbarch, insn, "cps", dsc);
-  else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
+  else if (op1 == 0x10 && op2 == 0x0 && (rn & 0x1) == 0x1)
     return arm_copy_unmodified (gdbarch, insn, "setend", dsc);
   else if ((op1 & 0x60) == 0x20)
     return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc);